Latches and Flip-Flops: Dr. Paul D. Franzon

1
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

ECE 733 Class Notes
Latches and Flip-Flops
Dr. Paul D. Franzon
Outline
Design Goals
Basic Latches and Flip-flops
Optimizing Timing
Single Sided Designs
Differential Designs
Some comparisons
References
Dally & Poulton, Chapters 4, 12.1
Kang & Leblecici, Chs 8-9
Bernstein, Ch. 5
2
ECE 733 Class Notes
Objectives and Motivation
Objectives:
Understand design goals and tradeoffs in flip-flops and how they are
measured
Be able to describe operation of a wide range of flips and recognize how the
roles of individual transistors determine operation
Motivation
Most complex high-speed digital circuit
Constrains performance of logic and I/O
3
ECE 733 Class Notes
Revision
D-Latch:
level-sensitive
Tracks data while clock high
Stores data while clock low
D-Flip-flop
edge-sensitive
Stores data on clock edge
D Q
Ck
Ck
D
Q
t
hold
t
SetUp
t
clock-Q
t
aperture
Ck
D
Q
t
hold
t
SetUp
t
clock-Q
t
aperture
t
D-Q
4
ECE 733 Class Notes
Edge-Triggered Flip-Flops
Created from latches:
Two styles:
5
ECE 733 Class Notes
Goals of Flip-Flop Design
Timing and Clock Speed:
Goal:
Minimize t
DQ
=t
Ck-Q
+ t
setup
max log max max clock ck Q ic setup skew
t t t t t

Logic
clock
skew
6
ECE 733 Class Notes
Goals
Timing Closure:
Ability to withstand max-min process and
temperature variations depends on how
much of the clock-period is taken up by
setup and hold times
Goal:
Constrains maximum t
aperture
= t
setup
+t
hold
Register Register
Comb
Logic
+/-t
skew
D1
Q1
D2
Q2
t
Logic-delay
clock
clock
clock
D2
tskew
tset-up
t
hold
tskew
t
ck-Q-max
+ t
logic-max
t
ck-Q-min
-t
logic-min
7
ECE 733 Class Notes
Goals of flip-flop design
Timing Related:
To get fastest clock period:
Minimize tD-Q
soft clock edge
NOT (or reduce) propagate clock skew to Q
Removes or reduces impact of tskew on clock period
Note : Latches have this property for signals that arrive after clock
rising edge!
Incorporate logic into flip-flop
And remove from before/after flip-flop
clock
D
Q
skew
clock
D
Q
skew
=t_su + t_ck-Q
8
ECE 733 Class Notes
Timing Related:
Be able to drive good loads
Typical fan-out: 2-8 FO4 inputs (50 200 fF in 0.18 m)
Minimum susceptibility to clock slope (edge rate)
Most FFs have an max rise/fall time specification
9
ECE 733 Class Notes
Power Related
Minimize internal power
Minimize clock load
Note : Speed-power tradeoff
Can design to minimize Power.Delay or Energy.Delay Product
Measured in fJ gives minimum energy per transition (and energy-delay
product for constant fclock)
Bit Error Rate Related
Minimize suceptibility to:
Noise on clocks or signals (e.g. due to crosstalk)
Clock edge rate variations
Charge-sharing failures
Charge leakage failures, including alpha particle strikes
Power & ground noise
Other
Facilitate test and debug (Be static & scannable)
10
ECE 733 Class Notes
Flip-Flop Basics
Generic Flip-Flop:
Sampling Stage:
Must ensure input is sampled for both high and low D
Fastest if no DC path from Vdd to Gnd during sampling
Output Stage:
Drives load without disrupting stored state
Sampler storage Output
Static:
Dynamic:
etc.
11
ECE 733 Class Notes
Basic Bistable Static Storage Element
Cross-coupled inverter pair
V2
V1
V3
V2
V1
V3
V2
V2
V1
Inverter loaded with
itself:
Regenerative feedback
Unstable (high gain)
Stable operating point
Stable operating point
V1
V1
Qualitative View:
Energy
V2
12
ECE 733 Class Notes
Noise Margin
Add noise at one input:
V2
V1
V2
V1
Vn
Assume nominal V2 =1
Small Vn
V2
V1
Large Vn
High gain no longer stable
V2
V1
Size of boxes
determine NMs
Unity gain
13
ECE 733 Class Notes
Basic Latches
To store a logic level (change state):
Must overcome the potential hill
between two stable states
Some Methods:
Use Transmission gates to break feedback
path
D-latch
Break supply current path (RS latch)
Reset/Set
D latch:
Clk
D Q
S R
Q
Q
NOR RS latch
R
S
Q
Q
Q
Q
clk
D
Can replace
INV with logic
14
ECE 733 Class Notes
Latch Basics
Other Methods To Change State:
Directly over-powering regenerative
feedback in storage cell
Must generate a negative noise margin
by the write (clk=high)
In this case:
Sizes p1, p2 = 2 m / 0.35 m
Sizes n3, n4 = 3 m / 0.35 m
Sizes n1, n2, n5, n6 = 5 m / 0.35 m
provides sufficient write margin
Q
p2
Q
D
clk
p1
n1
n2
D
clk
n3
n4
n5
n6
V2
V1
Negative Voltage Margin
Write
RH inverter (D=0)
LH inverter (D=1)
15
ECE 733 Class Notes
Revision: Flip-flop Design Goals
Timing:
Goals :
Minimize t
DQ
= t
clock-Q
+ t
SU
Constrain upper limt for t
aperture
= t
setup
+ t
hold
max max max log max

skew setup ic Q ck clock
t t t t t
Logic
clock
skew
16
ECE 733 Class Notes
Timing
Tradeoff between tclock-Q and tsu / thold:
Why?
t
clock-Q
t
SU
t
hold
clock
D
Q
D
clk
X
Smaller t
SU
V
X
smaller
-Amplification Voltage growth exponential with time
V
Q
e
-t/
Amplifier delay increases exponentially with decreasing
t
SU
Q metastable during amplification
Q
Q
(I.E. with smaller Vx)
17
ECE 733 Class Notes
Doing this in Project
Illustrate for D: 0 1 transition:
Clock
D
Q
t
su
t
ck-Q
Conservative tsu:
One point on
curve on previous page
t
su
t
ck-Q
Aggressive tsu:
Another point
<t
su
Failure:
Failure!
NOT a valid t
su
Reminder: Goal most likely to minimize t
DQ
, not t
su
18
ECE 733 Class Notes
Project Characterization
T_hold
<t
hold
Failure:
Failure!
NOT a valid t
hold
Ck
D
Q
t
hold
Good:
Good! (NO change in Q due to D)
t
hold
Ck
D
Q
19
ECE 733 Class Notes
Timing
Objective : Minimize t
D-Q
= t
SU
+ t
clock-Q
Often results in negative setup time
t
clock-Q
t
D-Q
(ps)
t
SU
(ps)
-60 -40 -20 0 20 40 60 80
400
350
300
250
clock
D
Q
t
SU
t
D-Q
Forbidden
e.g. strong-ARM flip-flop
20
ECE 733 Class Notes
Other Timing Parameters
Hold period:
-80 -60 -40 -20 0 20 40 60 80
400
350
300
250
H
o
l
d
t
SU
(ps)
clock
D
t
SU
Hold period
(no transitions
allowed)
F
o
r
b
i
d
d
e
n
21
ECE 733 Class Notes
Other Timing Parameters
Effect of clock edge rate
Flip-flop timing can be sensitive to clock edge rate (slope)
Can cause race-through in Master-Slave
e.g. pass-gate FF:
Clk
D
Q
Clk
Q
clk
clk
T1
T2
Vinv
Vt
Vt
T1 open
T2 open
Problem if T2 open longer than T
inv-delay
past this time
22
ECE 733 Class Notes
Latches Flip-Flops Characterized
Single-Sided
C2MOS
TSPC
Transmission Gate
Double-Sided (complementary or differential)
DCVS
Single Transistor Clock
Hybrid Latch Flip-flop
Semi Dynamic Flip-flop
Sense Amp Flip Flop
K6 Flip Flop
Comparisons
23
ECE 733 Class Notes
Common Questions
How is the signal sampled on the clock 0 1 transition?
What determines:
tsetup ?
thold ?
tck-Q ?
How is the data stored?
What prevents false transitions from occuring when
D changes after thold ?
When clock goes low ?
24
ECE 733 Class Notes
C2MOS Flip-Flop
Edge triggered Master-Slave device:
Tri-state inverter
Clock Buffer
Samples while clk Low
Samples while clk High
Regenerate when clock high
25
ECE 733 Class Notes
C2MOS Operation
Track (ck = 0)
Track (ck 1)
Tracking input
Recycling previous value
Sampling input
Holding sampled value
=on
26
ECE 733 Class Notes
Timing
What determines t_setup and t_hold?
What determines t_clock-Q?
D can not change during this interval
clk
ckb
ck
tsu
t_hold
Clock buffer delay + delay through second tri-state buffer
27
ECE 733 Class Notes
True Single Phase Clocked (TSPC) Latches & Flip-Flops
Based on the following dynamic latches:
Transparent while clock high: When clock low:
Note : Only clock is needed, not clock or a second clock phase
True single phase lowest skew in distribution
Make latches and flip-flops by mixing stages.
(Source : Yuang and Svenson)
D
clk
SP
D
clk
PP
D
clk
SN
D
clk
PP
28
ECE 733 Class Notes
TSPC Flip Flops
Example:
Positive edge triggered static-input flip flop
SP + SP + SN + SN
Observation:
SP stage simply inverts a while clk lo
Not needed if Q OK..
Note, nodes a, b, Q float for part of clock
period
Watch for inadvertant charge sharing
Note can put logic in PU and PD chains
D
clk
a
b
D
clk
a
b
Q
29
ECE 733 Class Notes
Operation
D=0, clk=0 ck 1
D1, clk=1 (Q should not change)
D
clk
a
b
Q
1
1
D
clk
a
b
Q
x1
0
1
Note: a/b floats high or low (x0, x1)
D
clk
a
b
Q
0
x0
1
30
ECE 733 Class Notes
Operation
D=1, clk=0 ck 1
D0, clk=1 (Q should not change)
Note: a/b floats high or low (x0, x1)
D
clk
a
b
Q
0
1
D
clk
a
b
Q
0
x1
0
D
clk
a
b
Q
x0
x1
0
31
ECE 733 Class Notes
TSPC Issues
Timing:
tclock-Q is very quick
Must have logic between stages to prevent hold violation
Can be sensitive to clock slope (next page)
Has floating nodes during evaluate
Very high clock load
32
ECE 733 Class Notes
Clock Slope
Example : Sensitivity of TSPC flip-flop:
Possible failure:
Possible Fixes :
D
clk
a
b
Q
n1
p1
p2
clock
b
Q
D remains high
a low when clock low
p1 & p2
On
p1 off
before p2 on
Reduce Wn1; enforce clock slope rules
33
ECE 733 Class Notes
Transmission Gate Master-Slave
PowerPC 603
Clock Load
High
Power
Low
low power feedback
Positive setup
Q buffer makes timing less sensitive to load variations
TG delay determines t_su INV(s) + TG gate determines t_ck-Q
(first INV only matters if tsu very small)
34
ECE 733 Class Notes
Differential Latches and Flip Flops
i.e. Requires both D and D
Conventional Latches and Master-Slave Designs
DCVS
True Single Phase Clocked Latch
DSTC and SSTC
Pulse-triggered Latches:
HLFF
DSFF
SAFF
ETL
35
ECE 733 Class Notes
Differential Cascode Voltage Switch
Variants:
Static RAM style Latch
Operation explained earlier
Transparent when clk hi
Simple DCVS:
Latch or flip-flop?
Dynamic or static?
Susceptibility to charge sharing can be
reduced by placing inverters on Q and
Q
Q
p2
Q
D
clk
p1
n1
n2
D
n3
n4
n5
Q
p2
Q
D
clk
p1
n1
n2
D
clk
n5
n6
Latch
Dynamic
36
ECE 733 Class Notes
DCVS
Combine to make Master-Slave Flip-flop
Better than single-sided flip-flops
Fewer gates than C2MOS
Fully static storage
Smaller clock load
Complementary faster operation
Q
p2
Q
clk
p1
n1
n2
n3
n4
n5
p4
D
clk
p3
n6
D
n7
p5
37
ECE 733 Class Notes
Operation
Clock = low:
Master turned on
One of n1 or n5 turned on
Clock high
n1 or n5 overpowers latch
After thold, what prevents a false transition?
If D changes, can NOT result in the off n1 or n5 turning ON, as no PU path in
master
D changing can only result in the on transistor turning OFF: OK as latch has
already stored new value
Q
p2
Q
clk
p1
n1
n2
n3
n4
n5
p4
D
clk
p3
n6
D
n7
p5
Master
Slave
38
ECE 733 Class Notes
Operation
Ck=0; D=1
Q
p2
Q
clk
p1
n1
n2
n3 n4
n5
p4
D
clk
p3
n6
D
n7
p5
Master
Slave
39
ECE 733 Class Notes
Operation
Ck1; D=1
Q
p2
Q
clk
p1
n1
n2
n3 n4
n5
p4
D
clk
p3
n6
D
n7
p5
Master
Slave
Float Hi
Q=0
40
ECE 733 Class Notes
Operation
Ck=1; D0
(expect to see no transition)
Q
p2
Q
clk
p1
n1
n2
n3 n4
n5
p4
D
clk
p3
n6
D
n7
p5
Master
Slave
0
Q=0
n5 off
n6 off
41
ECE 733 Class Notes
DCVS
Variant : Ratio insensitive Latch
Removes need to overcome X-coupled
latch to change state
Especially hard to overcome nFETs in
X-coupled inverters
Reduces sensitivity to process
variations
p5, p4 ensures Vdd/Gnd path broken
when changing stored state
p3 ties the on p1 or p2 to Vdd when
clock is low and latch is holding its
outputs
Q
p2
Q
clk
p1
n1
n2
n3
n4
n5
p3
clk
p5
p4
D
D
0
1
e.g. 0 held:
D has not changed:
D has changed:
1
0
Vdd path
42
ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
Q
p2
Q
clk
p1
n1
n2
n3
n4
n5
p3
clk
p5
p4
D
D
HI
Q
p2
Q
clk
p1
n1
n2
n3
n4
n5
p3
clk
p5
p4
D
D
HI
Q=1
P3 OFF allows latch state to change easilly
43
ECE 733 Class Notes
Operation
Ck0; D=1 (latch event) Ck=0; D0 (expect no change)
Q
p2
Q
clk
p1
n1
n2
n3
n4
n5
p3
clk
p5
p4
D
D
HI
Q=1
Q
p2
Q
clk
p1
n1
n2
n3
n4
n5
p3
clk
p5
p4
D
D
HI
Q=1
P3 ON means latch data is preserved
44
ECE 733 Class Notes
DCVS latch with pre-charge
Add pre-charge to increase speed:
Simple Latched Dual Rail Domino structure:
Q Q
A
B
A B
clk
clk
clk
Q
Q
D
D
clk
clk
clk
latch pair
Dynamic D latch with pre-charge
D latch with merged logic
45
ECE 733 Class Notes
Single Transistor Clocked MS latches
Yuan & Svensson 97
Small clock load; charge sharing issues
(Dynamic)
(Semi-static)
Min. sizes. Ensures static
operation if D changes while
clk high.
X
n1 n2
n3 n4
p3
p1
p2
p4
p5
n1 n2 n3
n4 n5 n6 n8
n9 n10
p2
p3
p4
p5 p6
46
ECE 733 Class Notes
operation
Ck=0; D=1 Ck1; D=1
n1 n2
n3
p3
p1
p2
p4
p5
n1 n2
n3
p3
p1
p2
p4
p5
47
ECE 733 Class Notes
Operation
Ck=1; D->0
n1 n2
n3
p3
p1
p2
p4
p5
48
ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
Lo Lo
Hi
n1 n2 n3
n4 n5 n6 n8
n9 n10
p2
p3
p4
p5 p6
n1 n2 n3
n4 n5 n6 n8
n9 n10
p2
p3
p4
p5 p6
49
ECE 733 Class Notes
Operation
Ck=1; D0
Lo
INV and nFETs it drives
help discharge floating node
n1 n2 n3
n4 n5 n6 n8
n9 n10
p2
p3
p4
p5 p6
50
ECE 733 Class Notes
Pulse-triggered Latch
Principle of Operation:
Hybrid Latch Flip-Flop (HLFF) (AMD, K6, Portovi, 1996)
Clocked Transistors
X
X pre-charged (clock low)
Pulse samples D onto X
Master
Slave
Storage
n1
n2
n3
n4
n5
n6
p2
p3
p4
p1
51
ECE 733 Class Notes
HLFF
Operation:
Absorbs skew
Fully static (retains Q)
Negative setup
Allows cycle stealing
Can add logic
thold c.f. tD-Q
Precharge
(clock low)
Precharge
(clock high)
D high
D low
X
Storage
n3
n2
n1
n6
n5
n4
p2
p3
p4
p1
52
ECE 733 Class Notes
HLFF Operation
Basic Structure
Precharge dynamic inverter master
Clock-evaluate inverter slave
Clock Low
Precharge X
Clock High
n1 on; n3 on for 3 INV delay
D high X low p4 pulls Q hi
D low X charge shared with n1_S; p2
turn on, pulling X high
After thold
p3 (weak) turns on starts pulling X
high to help precharge
D : Hi Lo : n2 off : no change as n3 off
D : Lo Hi : n2 on : no change as n3 off
and p3 keeps X high
p1 p2
p3
p4
n1
n2
n3
n4
n5
n6
X
tsu:
Can be negative
Criteria:
thold
Determined by:
As long as n2 turns on while n1, n3 Hi
time n3 on after optimal tsu point
53
ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
Q=1
Critical path larger transistors
= turning off
= turning on
X
n3
n2
n1
n4
n5
n6
p2 p3 p4 p1
n3
n2
n1
n4
n5
n6
p2 p3 p4 p1
54
ECE 733 Class Notes
Operation
Ck=1; X precharges Ck=1; D0
weak
Q=1
X
Q=1
Precharge helps defines size of weak pull-up
n3
n2
n1
n4
n5
n6
p2 p3 p4 p1
n3
n2
n1
n4
n5
n6
p2 p3 p4 p1
55
ECE 733 Class Notes
Operation
Ck=0; D=0 Ck1; D=0
weak
Q=0
X
Easier transition than 01.
Tsu determined by time for RHS sampler to replace role of LHS sampler if D=1
At clock going high, and then changes to 0 during pulse
n3
n2
n1
n4
n5
n6
p2 p3 p4 p1
n3
n2
n1
n4
n5
n6
p2 p3 p4 p1
56
ECE 733 Class Notes
Operation
Ck=1; X precharges Ck=1; D1
weak p3 reduces dip in X, as a result of
charge-sharing through n2, making
sure p4 does not turn on
weak
Q=1
X
Q=1
Helps defines size of weak pull-up
n3
n2
n1
n4
n5
n6
p2 p3 p4 p1
n3
n2
n1
n4
n5
n6
p2 p3 p4 p1
57
ECE 733 Class Notes
HLFF Waveforms
charge share X to nfet n1
Weak p3 pulling X high
n3
n2
n1
n4
n5
n6
p2 p3 p4 p1
58
ECE 733 Class Notes
Semi-Dynamic Flip Flop
Sun UltraSparc, Klass, VLSI Circuits 98
n3
n2
n1
n4
n5
p2
p1
59
ECE 733 Class Notes
SDFF
Operation
X
Clk = low : X precharged to 1, N1 is ON
Clk hi :
D=0 :
X stays high, N1 on then off, Q pulled down; 0 stored
D=1:
N1
X goes low, leaving N1 on. Pulls Q high
No P/G connection on LHS X latched low by X-coupled inverters)
After thold if D 1:
N1 is off : No change
After thold if D 0:
n3
n2
n1
n4
n5
p2
p1
60
ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
0
1
1
01
10
1
Q=1
Defines critical path
Tsu: 3 nfets on long enough for 10 transistion
n3
n2
n1
n4
n5
p2
p1
n3
n2
n1
n4
n5
p2
p1
61
ECE 733 Class Notes
Operation
Ck=1; D0 D=1; Ck0
1
0
1
Q=1
0
0
01
1
Q=1
Q does not change
n3
n2
n1
n4
n5
p2
p1
n3
n2
n1
n4
n5
p2
p1
62
ECE 733 Class Notes
Operation
Ck=0; D=0 Ck1; D=0
0
1
1
01
1
10
Q=0
If D went high while Delayed ck
nFET is turning off, a different Q could result
(i.e. tsu could be negative, and the action
In LHS pull down chain defines tsu)
n3
n2
n1
n4
n5
p2
p1
n3
n2
n1
n4
n5
p2
p1
63
ECE 733 Class Notes
Operation
Ck=1; D1 Ck0
1
1
0
Q=0
1
0
1
1
Q=0
1
Because top left nFET turned
off, Q does not change
n3
n2
n1
n4
n5
p2
p1
n3
n2
n1
n4
n5
p2
p1
64
ECE 733 Class Notes
SDFF Timing Waveforms
65
ECE 733 Class Notes
Sense Amp Flip Flop
Matsui, et.al. 1994, DEC Alpha 21264; StrongArm
110
First stage : Sense Amp
Precharged to Hi when clk=0
p2, p3 :
n3, n4 :
Clk1
Diff Amp amplfies change in D
p2 or p3 turn on, latching value onto
storage cell
S or R go low
Role of N5
Keeps both INVs grounded even if D
changes
If D changes after thold
N5 reduces swing onto INVs
Strength of N5?
SR latch
Ideal for low-swing inputs
Clocked T
Storage
DiffAmp
Off
On
Weak
66
ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
0
1
1
0
Data stored in latch at top center
2
3 4
1
2
3 4
1
67
ECE 733 Class Notes
Operation
Ck=1; D0 Ck0; D=1
0
0
0
1
1
0
0
0
1
1
1
0
RS latch unaffected as S, R = 1
Mn5 prevents change in latch
1 2
3 4
2
3 4
1
68
ECE 733 Class Notes
SAFF Timing
Ck->1
0
1
1
0
tsu
tforbidden
Tck-Q
1 2
3 4
1
N2 not on long enough to pull down
2 long enough to start turning N3 off.
Once N3 is enough, D-> 1 will no longer work
N3 is sufficiently off to prevent full transition
but on enough to start one
N6-N1-N3 pulls 1 down
S->0
Delay in SR latch
69
ECE 733 Class Notes
SAFF
70
ECE 733 Class Notes
71
ECE 733 Class Notes
Modified SAFF
72
ECE 733 Class Notes
K6 ETL
n3
n2
n1
n4
p2 p1
p3
p4
73
ECE 733 Class Notes
Operation
Clock Low:
Clock Hi
Nothing
D or Db sampled onto Q or Qb
by clock pulse
An input of NOR 1
rst Lo, 3 INV delays later
q, qb Hi
rst off
Self reset, Why?
Reduces clock load
Pulsed output!
-Must ensure output pulse
is sufficiently wide
n3
n1
n4
p2 p1
p3
p4
n2
74
ECE 733 Class Notes
Flip Flop Comparison
75
ECE 733 Class Notes
K6
Sense
Amp
StrongArm
SDFF
76
ECE 733 Class Notes
HLFF
PowerPC
C2MOS
77
ECE 733 Class Notes
Delay Comparison
78
ECE 733 Class Notes
Power Delay Product
79
ECE 733 Class Notes
Clock Power Consumption
80
ECE 733 Class Notes
General Characteristics
81
ECE 733 Class Notes
Reduced Clock Swing FlipFlop
Goal : Reduce clock power
Clock 20% - 40% of overall chip power
82
ECE 733 Class Notes
Low Swing Double-Edge Triggered Flip-Flop
83
ECE 733 Class Notes
Flip Flop Design Summary
In high performance circuits, what are some of the goals of Flip-Flop design?
What design characteristics tend to produce the best flip-flops?
Fast total t
D-Q
= t
su
+ t
clk-Q
Minimum Power consumption
(internal + clock load)
Capture tradeoff:
-Power Delay product
(=Energy.Delay at constant fclk)
Narrow aperture time (t
SU
+t
hold
)
Minimize sensitivity to clock slope; charge sharing; crosstalk; Vdd/Gnd noise
Use latch concepts in FFs; esp. pulsed clocked latches
- gives narrow aperture WITH negative t
SU
Strive for reduced node swings

Latches and Flip-Flops: Dr. Paul D. Franzon

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Latches and Flip-Flops: Dr. Paul D. Franzon

Uploaded by

Copyright:

Available Formats

1

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

You might also like