Online Instructors Manual

to accompany
Intel Microprocessors
Eighth Edition
Barry B. Brey
Upper Saddle River, New Jersey
Columbus, Ohio
__________________________________________________________________________________
Copyright 2009 by Pearson Education Inc. !pper "addle #i$er %e& 'ersey 0()*+.
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Preface
$his is the ei"hth edition o# this te:t and since its inception there have been many
chan"es in the covera"e $he ,ntel architecture and the personal computer have proved to
be resilient and ever improvin" technolo"y with no end in si"ht Over the years there
have been many attempts at displacin" this technolo"y, but none have succeeded ;hat
may not have been understood is that the hardware is relatively ine:pensive, especially
today, and so#tware continues to become more e:pensive ;hether this is the best
technolo"y is a moot point $he so#tware has caused it to survive and thrive and as time
passes the assaults become #ewer and wea%er $he ,ntel architecture has truly become the
standard to master
,n the be"innin" o# this architecture we had a relatively primitive machine '2024<2022(
that has evolved into a very power#ul machine 'Pentium Core8 with two cores( ;hat the
#uture holds is parallel processin" 'an 20 core version has been demonstrated by ,ntel(
and somewhat hi"her cloc% #re=uencies and applications that communicate throu"h li"ht
waves in place o# wires +ven thou"h , write o# this wonder#ul technolo"y , sometimes
doubt my sanity since , #irst learned di"ital technolo"y usin" vacuum tubes , recall
buildin" my #irst decade counter usin" #our dual triode vacuum tubes #or the #lip9#lops,
neon lamps as indicators, and a power supply volta"e o# 800 volts , recall when the 3600
N!N* "ate #irst appeared #or >/115 , was ama?ed when the ,ntel 6006 appeared in
/13/, a year a#ter , started teachin" di"ital electronics and computers ,# you are
relatively youn", can you ima"ine what you will see in your li#etime in this incredible
#ield@
, than% each and every one o# you #or your continued support ,# you have any comments
or su""estions, please do not hesitate to write because , do answer all my e9mail
bbreyAeenet
Bou mi"ht also enCoy visitin" my website at)
http)<<memberseenet<brey
$he publisher also has a set PowerPoint slides #or this te:t #or instructors only ,# you
need them contact your representative
Chapter One
/ Charles -abba"e
7 Herman Hollerith
5 $o decode the +ni"ma code durin" ;orld ;as ,,
3 ,ntel Corporation
1 Drace Hopper
// 2020
/7 2024<2022
/5 6D bytes
/3 /115
/1 20624 throu"h the Core8
8/ Comple: ,nstruction Set Computer
87 /086
85 /086
83 /,000,000
81 8D or 7D #or 789bit mode and currently 2D #or 469bit mode
7/ /D
77 Currently /$ byte usin" a 609bit address
75 Protected memory or e:tended memory
73 !n early operatin" system called the *is% Operatin" System
71 Eideo +lectronics Standards !ssociation
6/ Universal Serial -us
67 +:tended Femory System
65 System !rea
63 $he -,OS controls the computer at its most basic level and provides #or
compatibility between computers
61 $he microprocessor is the controllin" element in a computer system
5/ !ddress bus
57 $he ,<O read si"nal causes an ,<O device to be read
55 'a( de#ines a byte or bytes o# memory 'b( de#ines a =uadword or =uadwords o#
memory 'c( de#ines a word or words o# memory 'd( de#ines a doubleword or
doublewords o# memory
53 'a( /785 'b( 53/235 'c( 677/85 'd( 30485
51 'a( /47/235 'b( 81335 'c( /38251735 'd( 60///235 'e( 700005032/85
4/ 'a( 0/0/ 05 0! 'b( 00000/0/ 0086 00! 'c( 0/0/0000/ 0508 0!/
'd( 0// 04 0C 'e( 0//// 036 0&
47 'a( C8 'b( /0&* 'c( -C 'd( /0 'e( 2-!
45 'a( 0/// //// 'b( 0/0/ 0/00 'c( 0/0/ 000/ 'd( /000 0000
43 'a( 64 58 6& 63, 'b( 6/ 38 47, 'c( 53 4/ 36 45 38, and 'd( 53 45 4C 4C
41 $he Unicode is the /49bit alphanumeric code used with ;indows
3/ 'a( 00/0 0000 'b( //// 0/00 'c( 0//0 0/00 'd( /0/0 0/00
37 *- 976
/
/8
76
!/
88
-/
00
35 'a( 'b( 'c(
33 *; /876H
31 'a( G/82 'b( 5/ 'c( G//0 'd( G//2
2/ 'a( 0 0/////// /0000000000000000000000
'b( / /00000/0 0/0/0/00000000000000000
'c( 0 /0000/0/ /00/000/000000000000000
'd( / /000/00/ 00/0//00000000000000000
Chapter /&o
/ Pro"ram visible re"ister are the re"isters that are directly used in an instruction
7 $he 20724 throu"h the Core8
5 CH, CI, +CI, or RCI
3 ,NC and *+C
1 Odd
// $he 20724 throu"h the Core8
/7 'a( /0000HJ/&&&&H 'b( /8760HJ8877&H 'c( 87000HJ78&&&H
'd( +0000HJ+&&&&H 'e( !-000HJ-!&&&H
/5 /00000H
/3 +!I, +-I, +CI, +*I, +-P, +S,, and +*,
/1 Stac%
8/ 'a( 87000H 'b( /C000H 'c( C!000H 'd( 21000H 'e( /CC10H
87 !ny location in the memory system
85 2,/18
83 0/000000HJ0/00&&&&H
81 6
7/ *escriptor 80H, local table, a privile"e rin" /
75 D*$R
73 $he internal cache is loaded with the base address, o##set address, and access
ri"hts byte
71 $he D*$R address the Dlobal *escriptor $able
6/6,014
67 6F
65 70000000H
61 $he #lat mode memory system is used with 469bit operation o# the Core8
8
Chapter /hree
/ 'a( the contents o# -I is copied into !I 'b( $he contents o# !I are copied into
-I 'c( the contents o# CH are copied into -H 'd( the contents o# +-P are copied
into +SP 'e( the contents o# RCI are copied into R!I
7 !I, -I, CI, *I, SP, -P, S,, *,, CS, *S, +S, SS, &S, and DS
5 R!I, R-I, RCI, R*I, RSP, R-P, RS,, R*, and R2JR/5
3 $he re"ister si?es must be e=ual, /49bit cannot be #it into 29bits
1 'a( FOE +*I,+-I 'b( FOE CH,-H 'c( FOE -I,S, 'd( FOE !I,*S
'e( FOE !H,!H '#( FOE R/0,R2
// K
/7 CO*+
/5 Opcode
/3 ,t ends the pro"ram by e:itin" to the operatin" system
/1 $he S$!R$UP directive loads the *S re"ister
8/ ,ndirect addressin"
87 Femory to memory trans#ers are not allowed with the FOE instruction
85 ,NC ;OR* P$R L+*,M
83 *+C N;OR* P$R LR!IM
81 'a( 8///0H 'b( /0/00H 'c( 8/000H
7/ 'a( /8/00H 'b( /8750H 'c( /8880H
77 'a( //350H 'b( //150H 'c( //300H
75 'a( /5300H 'b( 05/00H 'c( 03/00H
71 5, the #irst byte is the opcode, #ollowed by a two byte se"ment address, #ollowed
by a two byte o##set address
6/ O78P
67 ! #ar Cump always a Cump to any location in the memory map
65 'a( short 'b( near 'c( short 'd( #ar
63 JFP N+!R
61 PUSH L*,M places the /49bit contents o# the location addressed by *S and *, onto
the stac%
5/ Places the 789bit contents o# he re"ister array onto the stac%
57 no
Chapter 0our
/ Opcode
7 $he FO* #ield speci#ies the type o# access #or the R<F #ield and the si?e o# the
displacement
5 ,# operated in the /49bit mode, a re"ister9si?e and<or address9si?e pre#i: is used to
speci#y a 789bit re"ister
3 'a( SS 'b( *S 'c( *S 'd( SS 'e( *S
1 FOE -I,L-PQ6C00HM
// 43 44 2- 70
/7 $he contents o# CS will chan"e causin" an unpredictable Cump
/5 78
7
/3 CS
/1 +!I, +-I, +CI, +*I, +SP, +-P, +*, and +S,
8/ $he -H re"ister is moved to memory location 080&&H and the -H re"ister is
moved to location 080&+H then SP is chan"ed to 00&+H
87 8
85 $he FOE *,,NUF- instruction copies the /49bit number in the data se"ment
location NUF- into *, while the H+! *,,NUF- loads *, with the o##set
address o# location NUF-
83 $he FOE with the O&&S+$ directive
81 H*S loads *S and HSS loads SS alon" with another /49bti re"ister #or the o##set
address
7/ ,# the direction #la" is cleared it selects auto9increment #or the strin" instructions
and i# the direction #la" is set is selects auto9decrement
77 FOES
75 ! 69bit number is loaded into R!R #rom the data se"ment memory location
addressed by +S, and then +S, is either incremented or decrement by 2 dependin" on
the settin" o# the direction #la"
73 $he S$OS; instruction copies !I into the e:tra se"ment memory location
addressed by *, then *, is either incremented or decremented by two as dictated
by the direction #la"
71 $he R+P pre#i: repeats a strin" instruction CI number o# times
6/ *I re"ister
67 TABLE DB 30H, 31H, 32H, 33H
DB 34H, 35H, 36H, 37H, 38H, 39H
BCD2A PROC NEAR
MOV BX,OFFSET TABLE
XLAT
RET
BCD2A ENDP
65 ,N !H, /8H copies the byte #rom ,<0 device /8H into !H
63 $he se"ment override pre#i: allows the de#ault se"ment to be chan"ed to any
se"ment
61 XCHG AX, BX
XCHG ECX, EDX
XCHG SI, DI
5/ *I is copied into CI i# a not ?ero or not e=ual condition e:ists
57 LIST1 DB 30 !"#$%
55 $he 424 directive in#orms the assembler that a Pentium Pro or newer
microprocessor is the tar"et o# the assembled pro"ram
53 models
51 $he pro"ram terminates and control is passed bac% to the operatin" system
4/ $he uses directive speci#ies which re"isters are saved on the stac% at the
be"innin" o# a procedure and popped at the end o# the procedure
47 ,# the model statement precedes the processor directive the code "enerated is /49
bit
6
Chapter 0i$e
/ 'a( !** !I,-I 'b( !** !H,/8H 'c( !** +-P,+*, 'd( !** CI,88H
'e( !** !H,LS,M '#( !** &ROD,CI '"( !** RCI,876H
7 No instruction is available to add to a se"ment re"ister
5 ADD AH,AL
ADD AH,BL
ADD AH,CL
ADD AH,DL
MOV DH,AH
3 MOV EDI,ECX
ADD EDI,EDX
ADD EDI,ESI
1 !*C *I,-I
// $he instruction does not speci#y the si?e o# the data addressed by -I and can be
corrected with a -B$+ P$R, ;OR* P$R, *;OR* P$R, or N;OR* P$R
/7 *H S 2/H, S S /, R S 0, C S 0, ! S 0, P S 0, O S /
/5 *+C +-I
/3 -oth instructions subtract, but compare doe not return the di##erence, it only
chan"es the #la" bits to re#lect the di##erence
/1 !H contains the most si"ni#icant part o# the result and !H contains the least
si"ni#icant part o# the result
8/ +*I and +!I as a 469bit product
87 ,FUH is si"ned multiplication while FUH is unsi"ned
85 !I
83 R!I
81 ,*,E is seined division, while *,E is unsi"ned division
7/ R!I
77 *!! and *!S
75 !!!, !!S, !!*, and !!F
73 P&SH AX
MOV AL,BL
ADD AL,DL
DAA
MOV AL,BH
ADC AL,DH
DAA
MOV BX,AX
POP AX
ADC AL,CL
DAA
XCHG AH,AL
ADC AL,CH
DAA
XCHG AH,AL
71 'a( !N* -I,*I 'b( !N* *H,0+!H 'c( !N* *,,-P
'd( !N* +!I,//88H 'e( !N* L-PM,CI '#( !N* *I,LS,G2M
'"( !N* ;H!$,!H
6/ 'a( OR !H,-H 'b( OR +CI,22H 'c( OR S,,*I 'd( OR -P,//88H
5
'e( OR LR-IM,RCI '#( OR !H,L-PQ60M '"( OR ;H+N,!H
67 'a( IOR !H,-H 'b( IOR CH,11H 'c( IOR *I,*, 'd( IOR RSP,/!87H
'e( IOR L+-IM,*I '#( IOR *,,L-PQ40M '"( IOR *,,;+HH
65 $he only di##erence is that the lo"ical product is lost a#ter $+S$
63 NO$ is one.s complement and N+D is two.s complement
61 !H is compared with the byte contents o# the e:tra se"ment memory location
addressed by *,
5/ $he * #la" selects whether S,<*, are incremented '* S 0( or decremented '* S /(
57 !n e=ual condition or i# CI decrements to 0
55 MOV DI,OFFSET LIST
MOV CX,300H
CLD
MOV AL,66H
REPNE SCASB
Chapter "i1
/ ! short Cump allows a pro"ram to branch #orward /83 bytes or bac%wards /82
bytes #rom the ne:t instruction.s address in the pro"ram
7 &ar Cump
5 O8D
3 ! label #ollowed by a sin"le colon is a short o# near address and a double colon
denotes a #ar address
1 $he code se"ment re"ister and the instruction address re"ister
// ! JFP *, copies the contents o# *, into the instruction address re"ister and a
JFP L*,M copies the /49bit number #rom the data se"ment memory location addressed
by *, into the instruction address re"ister
/7 Si"n 'S(, Rero 'R(, Carry 'C(, Over#low 'O(, and Parity 'P(
/5 ! JO instruction Cumps on an over#low condition
/3 JNR, JN+, JR, J+, J-, J-+, J!, J!+
/1 $ests the contents o# CI and Cumps i# it is ?ero
8/ CI
87 RCI
85 $he HOOP+ instruction Cumps is an e=ual condition e:ists and CI is not a ?ero
and it also decrements CI on each iteration o# the loop
83 MOV SI,OFFSET BLOC'
MOV &P,0
MOV DO(N,0
MOV CX,100H
MOV AL,42H
CLD
L1) SCASB
*E L3
*A L2
INC DO(N
*MP L3
L2) INC &P
L3) LOOP L1
4
81 !n in#inite loop is created
7/ ! -R+!P can be used to brea% out o# a ;H,H+ construct
77 $he main di##erence between a near and a #ar call is the distance #rom the call and
the type o# call and return that assembles
75 $he near return retrieves the return address #rom the stac% and places it into the
instruction address re"ister
73 PROC
71 $he R+$ 4 deletes 4 bytes #rom the stac% be#ore returnin" #rom a procedure
6/ S&MS PROC NEAR
MOV EDI,0
ADD EAX,EBX
*NC S&MA1
MOV EDI,1
S&MS1) ADD EAX,ECX
*NC S&MS2
MOV EDI,1
S&MS2) ADD EAX,EDX
*NC S&M3
MOV EDI,1
S&MS3)
S&MS ENDP
67 ,N$
65 !n interrupt vector contains the o##set address #ollowed by the se"ment address in
6 bytes o# memory
63 $he ,R+$* instruction pops the #la"s, a 789bit o##set address, and the protected
mode selector #or the CS re"ister
61 $he ,R+$N instruction is used in the 469bit mode to return #rom an interrupt
service procedure
5/ /00HJ/07H
57 ;!,$
55 /4
53 +SC
Chapter "e$en
/ No, macro se=uences and dot commands are not supported by the inline
assembler
7 Habels are de#ined in the inline assembler e:actly as they are in the assembler
5 +!I
3 *ot commands are not usable in the inline assembler
1 $he pro"ram uses S, and S, is not saved by the inline assembler so it must be
saved and restored usin" a PUSH and POP
// $he main di##erence is that when usin" the /49bit version a pro"ram should
attempt to use only 29 and /49 bit re"isters, while when usin" the 789bit version a
pro"ram should attempt to use 29 and 789bit re"isters
/7 $he conio header allows the putch'( "etche'( #unctions to be used in a pro"ram
3
/5 +mbedded applications use di##erent ,<O than the PC so the conio library would
not be used in an embedded application
/3 $he disp procedure divides by the number base and saves the remainders to
"enerate a number in any number base
/1 $he PU-H,C statement identi#ies a label as bein" available outside o# the module
8/ ,t de#ines that the Det,t #unction has a sin"le inte"er passed to it and returns
nothin"
87 ! control is usually some visible obCect that is obtained #rom the tool bo: in most
cases
85 ,t is a 789bit pointer
83 +:ternal procedures are de#ined usin" the e:tern prototype
81 ,t uses a 789bit '*;OR*( number
7/ +,- R.-/-0L01-3 #+,- ,!2304%
5
+1 # # ,!2304 6 0720000000 % 88 0720000000 %
5
,!2304 998 3:
,!2304 ;8 1:
<
0=>0
,!2304 998 3:
40-!4, ,!2304:
<
77 $he "reen arrow is clic%ed in the development environment
75 !n !ctiveI control is a control such as an edit bo: or te:tbo: used to build a
visual application
Chapter Eight
/ ObCect
7 Hibrary
5 +I$RN indicates that a label is outside o# the current pro"ram module
3 Only the #unction used #rom the library #ile are placed in a pro"ram
1 ! macro se=uence is a short list o# instruction placed in a pro"ram when the
macro is invo%ed
// ADD32 MACRO
ADD AX,CX
ADC BX,DX
ENDM
/7 ADDLIST MACRO PARA1,PARA2
P&SH AX
P&SH DI
P&SH SI
P&SH BX
MOV BX,OFFSET PARA1
MOV DI,PARA2
?REPEAT
MOV AL,@DIA
ADD AL,@BXA
2
MOV @DIA,AL
INC DI
INC BX
?&NTILCXB
POP CX
POP BX
POP DI
POP AX
ENDM
/5 $he include directive allows a #ile containin" macros to be included in a pro"ram
/3 "4+C/-0) SD>-02))V.+ -07-B.71E'0DD.F,#SD>-02))O3G0H-I >0,04,
SD>-02))(+,.F>))F.42>))'0DEC0,-A4J>I 0%
5 KK -L+> +> H/==0 1+4>-
M0DH/,=0 8 -4!0:
+1 #0NO'0DC.0 O8 '0D>))N!2P/0 66 0NO'0DC.0 98 '0D>))N!2P/9 ;;
0NO'0DC.0 O8 '0D>))D0 66 0NO'0DC.0 98 '0D>))D9 66
0NOSL+1- 88 1/=>0 ;;
0NO'0DC.0 O8 '0D>))A 66 0NO'0DC.0 98 '0D>))F ;;
0NO'0DC.0 88 '0D>))B/HM%
5
M0DH/,=0 8 1/=>0:
4/,.2PP: KK +,H4020,- 4/,.2F ,!2304
<
<
/1 "4+C/-0) SD>-02))V.+ -07-B.71E'0DP40>>#SD>-02))O3G0H-I >0,04,
SD>-02))(+,.F>))F.42>))'0DP40>>EC0,-A4J>I 0%
5
+1 #0NO'0DCL/4 O8 Q/Q 66 0NO'0DCL/4 98 Q1Q%
5
0NO'0DCL/4 N8 32:
<
+1 #0NO'0DCL/4 O8 QAQ 66 0NO'0DCL/4 98 QFQ%
5
0NO'0DCL/4 P8 32:
<
0=>0 +1 #0NO'0DCL/4 88 13%
5
+,- ,!2304 8 0:
1.4 #+,- / 8 0: / 9 -07-B.71NOT07-NOL0,J-L: /PP%
5
,!2304 8 C.,C04->#,!2304, -07-B.71NOT07-@/A%:
<
-07-B.72NOT07- 8 C.,C04-))T.S-4+,J#,!2304%:
M0DH/,=0 8 -4!0:
<
0NOH/,=0 8 M0DH/,=0:
<
8/ Re#er to $able 298
87 $he Fouse+vents!r" Clic%s is a 8 #or double clic%
85 $he Color class contains most common colors
83 !!F
81 ,# Horner.s al"orithm uses an 2 instead o# a /0 the number will be converted to
octal
7/ 70H
1
77 Subtract 70 #rom each di"it, multiply the result 'initial value o# 0( by /0, add a
di"it, and continue this #or all three di"its
75 char G0-I- #HL/4 -02"%
5
char =..M!"@A 8 5R0R,R1R,R2R,R3R,R4R,R5R,R6R,R7R,
R8R,R9R,RAR,RBR,RCR,RDR,RER,RFR<:
40-!4, =..M!"@-02"A:
<
73 $he master #ile table contains descriptors that describe the location o# the #ile or
#older
71 $he boot record 'trac% ?ero, sector ?ero( contains the bootstrap loader pro"ram
$he bootstrap loader pro"ram loads the operatin" system #rom the dis% into the
system
6/ 6P
67 Unicode
65 7
63 S-4+,JI 1+=0N/20 8 SC)TTT0>-1?-7-S:
/44/D9BD-0OI A44/D 8 JH,0F /44/D9BD-0O#512%:
-4D
5
F+=0S-40/2I 1> 8 F+=0))O"0,R0/#1+=0N/20%:
1>NOR0/#A44/D, 0, 512%:
1>NOC=.>0#%:
<
H/-HL #???%
5
M0>>/J0B.7))SL.F#SD+>M 044.4S%:
A""=+H/-+.,))E7+-#%:
<
61 $he remove #unction removes a #ile or #older #rom the dis%
Chapter Nine
/ $he main di##erences are the data bus width and the
,O< F
si"nal
7 'a( / 'b( 5 'c( 5
5 $hese bits indicate the se"ment bein" addressed by the current instruction
3 $he ;!,$ instruction waits #or the
$+S$
pin to become a lo"ic ?ero
1 Fa:imum mode
// Never
/7 *urin" a HOH*, the microprocessor stops processin" instructions and places the
address, data, and controls buses at the hi"h9impedance state
/5 $he
HOCP
pin becomes a lo"ic ?ero durin" instructions that pre pre#i:ed with the
HOCP) pre#i:
/3 $he cloc% si"nal is provided, the R+S+$ input is synchroni?ed, and the R+!*B
input is synchroni?ed
/0
/1 +&, input
8/ ?ero
87 !ddress<*ata bus
85 $he
-H+
si"nal is shared with a status bit 'S3(
83
*$< R
81 /0 Ts
7/ 85 F,PS
77 400 ns G //0 ns G 70 ns S 640 ns
75 U
73 0
71 ,t "enerates system control si"nals
Chapter Ten
/ !ll memory devices have address, data, and control connections
7 'a( 8062 #our bit numbers 'b( /086 one bit numbers 'c( 6014 ei"ht bit numbers
'd( /4,726 one bit numbers 'e( 45,574 #our bit numbers
5 ,t causes the memory device to read data #rom a location
3 'a( /P 'b( 8P 'c( 6P 'd( 2P 'e( /82P
1 &lash memory re=uires an e:tended amount o# time to accomplish an erase and
write
// $he
D
input cause a read, the
;
input causes a write, and the
S
input selects the
chip
/7 *ynamic random access memory
/5 $hese inputs strobe the column and row addresses into a *R!F
/3 Femory rarely #ills the entire memory, which re=uires some #orm o# decoder to
select the memory device #or a speci#ic ran"e o# memory addresses
//
/1
A 1 6
A 1 5
U 2 7 4 A L S 1 3 3
1
2
3
4
5
6
7
1 0
1 1
1 2
1 3
1 4
1 5
9
A 0 - - A 1 0
A 1 4
5 6
A 1 3
A 1 2
3 4
A 1 1
1 1 1 0
D 0 - - D 7
I O / M
5 6
V C C
1 2 _ _
9 8
A 1 9
R D
_ _ _
1 3 1 2
A 1 8
U 1 N M C 2 7 C 1 6 B
8
7
6
5
4
3
2
1
2 3
2 2
1 9
1 8
2 0
2 1
9
1 0
1 1
1 3
1 4
1 5
1 6
1 7
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 1 0
C E
O E
V P P
O 0
O 1
O 2
O 3
O 4
O 5
O 6
O 7
U 3 D 7 4 A L S 0 4
9 8
3 4
A 1 7
8/
A 1 3
U 1
7 4 H C T 1 3 8
1
2
3
1 5
1 4
1 3
1 2
1 1
1 0
9
7
6
4
5
A
B
C
Y 0
Y 1
Y 2
Y 3
Y 4
Y 5
Y 6
Y 7
G 1
G 2 A
G 2 B
A 1 5
A 1 6
A 1 9
A 1 7
A 1 4
U 2 A
7 4 H C T 0 0
1
2
3
A 1 8
87 $he 36HS/71 is a dual 89to96 line decoder
85 and or nand nor not
83
30J+,
ROM 98 A19 .4 #,.- A18% .4 A17 .4 MIO:
RAM 98 A18 /, A17 /, #,.- MIO%:
AX19 98 ,.- A19:
0, V1:
/8
81
A 0 - - A 1 4
U 3 A T 2 7 2 5 6
1 0
9
8
7
6
5
4
3
2 5
2 4
2 1
2 3
2
2 6
2 7
1 1
1 2
1 3
1 5
1 6
1 7
1 8
1 9
2 8
2 0
2 2
1
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
O 0
O 1
O 2
O 3
O 4
O 5
O 6
O 7
V C C
C E
O E
V P P
# R D
A 1 5
U 4 7 4 H C T 1 3 8
1
2
3
1 5
1 4
1 3
1 2
1 1
1 0
9
7
6
4
5
A
B
C
Y 0
Y 1
Y 2
Y 3
Y 4
Y 5
Y 6
Y 7
G 1
G 2 A
G 2 B
U 2 A T 2 7 2 5 6
1 0
9
8
7
6
5
4
3
2 5
2 4
2 1
2 3
2
2 6
2 7
1 1
1 2
1 3
1 5
1 6
1 7
1 8
1 9
2 8
2 0
2 2
1
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
O 0
O 1
O 2
O 3
O 4
O 5
O 6
O 7
V C C
C E
O E
V P P
A 1 6
A 1 7
A 1 8
U 1 A T 2 7 2 5 6
1 0
9
8
7
6
5
4
3
2 5
2 4
2 1
2 3
2
2 6
2 7
1 1
1 2
1 3
1 5
1 6
1 7
1 8
1 9
2 8
2 0
2 2
1
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
O 0
O 1
O 2
O 3
O 4
O 5
O 6
O 7
V C C
C E
O E
V P P
A 1 9
I O / # M
D 0 - - D 7
V C C
77 Sin"le bit error #la"
75 $he main di##erences are the data bus si?e and the ,<O, memory control si"nal
73 -an% low enable has replaced the !0 pin
71 Upper memory ban%
6/ ,t does not matter i# /49bit or 29bit are read because the microprocessor Cust
i"nores any data bus bits that are not needed
67
/7
A 2 0
# B H E
D 0 - D 7
A 2 1
A 1 - A 1 5
# W R
H M 6 2 2 5 6
1 0
9
8
7
6
5
4
3
2 5
2 4
2 1
2 3
2
2 6
1
2 0
2 2
2 7
1 1
1 2
1 3
1 5
1 6
1 7
1 8
1 9
2 8
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
C E
O E
W E
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
V C C
A 1 7
H M 6 2 2 5 6
1 0
9
8
7
6
5
4
3
2 5
2 4
2 1
2 3
2
2 6
1
2 0
2 2
2 7
1 1
1 2
1 3
1 5
1 6
1 7
1 8
1 9
2 8
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
C E
O E
W E
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
V C C
D 8 - D 1 5
H M 6 2 2 5 6
1 0
9
8
7
6
5
4
3
2 5
2 4
2 1
2 3
2
2 6
1
2 0
2 2
2 7
1 1
1 2
1 3
1 5
1 6
1 7
1 8
1 9
2 8
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
C E
O E
W E
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
V C C
H M 6 2 2 5 6
1 0
9
8
7
6
5
4
3
2 5
2 4
2 1
2 3
2
2 6
1
2 0
2 2
2 7
1 1
1 2
1 3
1 5
1 6
1 7
1 8
1 9
2 8
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 1 0
A 1 1
A 1 2
A 1 3
A 1 4
C E
O E
W E
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
V C C
A 1 8
A 2 3
A 0
A 1 6
# R D
U 1 8
G A L 2 2 L V 1 0 C / L C C
2
3
4
5
6
7
1 7
1 8
1 9
2 0
2 3
2 4
2 5
2 6
2 1
2 7
9
1 0
1 1
1 2
1 3
1 6
2 8
I / C L K
I
I
I
I
I
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I
I
I
I
I
I
V C C
V C C
A 2 2
A 1 9
63 ! cycle that does not read data, it only re#reshes a row o# memory
61 /5485 Ts
Chapter Eleven
/ $he ,N instruction inputs data #rom an e:ternal device into the accumulator and
the OU$ instruction sends data out to an e:ternal device #rom the accumulator
7 *I
5 !I
3 $he ,NS; inputs data #rom the ,<O port addressed by *I, as a word, into the
e:tra se"ment memory location addressed by *,V it then increments *, by 8
1 $he basic input inter#ace is a three9state bu##er that is enabled #or the ,N
instruction ;hen the bu##er is enabled data is "ated onto the data bus and into the
accumulator
// Handsha%in" is the act o# synchroni?in" two systems that operate asynchronously
/7 *2G*/5
/5
/6
U 1 A
7 4 H C T 3 2
1
2
3
# B L E
# H W R
# B H E
# W R
4
5
6
# L W R
/3
T T L I n p u t
L 1
E L A Y S P S T
4
3
1
2
" 1
2 N 2 2 2 2
1
1 # 2 K
1 2 V
D 1
/1
A 1
A 2
5 6 A 7
A 6 3 4
U 3 A 7 4 A L S 0 4
1 2 A 5
A 3 U 2 A 7 4 A L S 2 0
1
2
4
5
6
I O / # M
# B L E
U 1 7 4 A L S 1 3 8
1
2
3
1 5
1 4
1 3
1 2
1 1
1 0
9
7
6
4
5
A
B
C
Y 0
Y 1
Y 2
Y 3
Y 4
Y 5
Y 6
Y 7
G 1
G 2 A
G 2 B
A 4
8/
=+34/4D +000:
!>0 +000?>-E=.J+HE1164?/==:
0,-+-D DECODERE21 +>
".4- #
A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2,
A1) +, STDELOGIC:
S1000, S1002, S1004, S1006, S1008, S100A, S100C, S100E) .!- STDELOGIC
%:
0,:
/4HL+-0H-!40 V1 .1 DECODERE21 +>
30J+,
S1000 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
/5
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 A3 .4 A2 .4 A1:
S1002 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 A3 .4 A2
.4 #,.- A1%:
S1004 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 A3 .4 #,.- A2%
.4 A1:
S1006 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 A3 .4 #,.- A2%
.4 #,.- A1%:
S1008 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 #,.- A3% .4 A2
.4 A1:
S100A 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 #,.- A3% .4 A2
.4 #,.- A1%:
S100C 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 #,.- A3% .4 #,.- A2%
.4 A1:
S100E 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 #,.- A3% .4 #,.- A2%
.4 #,.- A1%:
0, V1:
87
=+34/4D +000:
!>0 +000?>-E=.J+HE1164?/==:
0,-+-D DECODERE23 +>
".4- #
BHE, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2,
A1) +, STDELOGIC:
S300D, S300B, S1005, S1007) .!- STDELOGIC
%:
0,:
/4HL+-0H-!40 V1 .1 DECODERE23 +>
30J+,
S300D 98 A15 .4 A14 .4 #,.- A13% .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 #,.- A3%
.4 #,.- A2% .4 A1 .4 BHE:
S300B 98 A15 .4 A14 .4 #,.- A13% .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 #,.- A3%
.4 A2 .4 #,.- A1% .4 BHE:
S1005 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 A3 .4 #,.- A2%
.4 A1 .4 BHE:
S1007 98 A15 .4 A14 .4 A13 .4 #,.- A12% .4 A11 .4 A10 .4 A11
.4 A10 .4 A9 .4 A8 .4 A7 .4 A6 .4 A5 .4 A4 .4 A3 .4 #,.- A2%
.4 #,.- A1% .4 BHE:
0, V1:
85 *0G*3
83 86
/4
81 !0 and !/
7/
=+34/4D +000:
!>0 +000?>-E=.J+HE1164?/==:
0,-+-D DECODERE31 +>
".4- #
BLE, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3)
+, STDELOGIC:
CS) .!- STDELOGIC
%:
0,:
/4HL+-0H-!40 V1 .1 DECODERE31 +>
30J+,
CS 98 A15 .4 A14 .4 A13 .4 A12 .4 A11 .4 A10 .4 #,.- A9% .4 #,.- A8%
.4 #,.- A7% .4 A6 .4 A5 .4 A4 .4 A3 .4 BLE
0, V1:
A 1 0
U 1 8 2 C 5 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
4
3
2
1
4 0
3 9
3 8
3 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
1 4
1 5
1 6
1 7
1 3
1 2
1 1
1 0
5
3 6
9
8
3 5
6
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 0
P B 1
P B 2
P B 3
P B 4
P B 5
P B 6
P B 7
P C 0
P C 1
P C 2
P C 3
P C 4
P C 5
P C 6
P C 7
D
W
A 0
A 1
E S E T
C S
V C C
A 1 1
A 3
A 4
D 0 - D 7
U 2 G A L 2 2 V 1 0 / L C C
2
3
4
5
6
7
1 7
1 8
1 9
2 0
2 3
2 4
2 5
2 6
2 1
2 7
9
1 0
1 1
1 2
1 3
1 6
2 8
I / C L K
I
I
I
I
I
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I
I
I
I
I
I
V C C
!
# W R
A 1
A 2
A 1 2
A 1 4
A 6
A 1 3
A 5
A 8
R E ! O " T
# R D
A 7
A 1 5
A 9
# B L E
77 Fodes 0, /, and 8
75 DELAU PROC NEAR
/3
MOV ECX, 479904
?REPEAT
?&NTIL ECX 88 0
RET
DELAU ENDP
73 $he 69coil stepper is moved by activatin" 'passin" current throu"h( a sin"le coil
at a time in round9robin #ashion to move the armature a step at a time
71 IN AL,PORTC
OR AL,80H
O&T PORTA,AL
6/ $he !CP si"nal is used by the ,<O device to in#orm the 2855 that the output data
has been processed by the output device
67 IN AL,PORTC
BT AL,4
*B IFEBERO
65 PC0, PC/, and PC8
63 ! display position is select by sendin" a command that contains the 39bit address
with the 2
th
and most si"ni#icant bit set
61 ! read command is issued and the le#tmost bit o# the data read #rom the HC*
display is the -USB bit
5/ /0G80 ms
57 /0 FH?
55
U 2 G A L 2 2 V 1 0 / L C C
2
3
4
5
6
7
1 7
1 8
1 9
2 0
2 3
2 4
2 5
2 6
2 1
2 7
9
1 0
1 1
1 2
1 3
1 6
2 8
I / C L K
I
I
I
I
I
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I
I
I
I
I
I
V C C
A 3
# B L E
A 2
V C C
A 3
A 3
D 0 - D 7
# W R
A 3
A 1
U 1 8 2 5 4
1 9
2 0
1 0
1 3
1 7
8
7
6
5
4
3
2
1
1 1
1 4
1 6
9
1 5
1 8
2 2
2 3
2 1
A 0
A 1
O U T 0
O U T 1
O U T 2
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
G 0
G 1
G 2
C L K 0
C L K 1
C L K 2
D
W
C S
A 3
# R D
=+34/4D +000:
!>0 +000?>-E=.J+HE1164?/==:
/2
0,-+-D DECODERE55 +>
".4- #
BLE, A7, A6, A5, A4, A3) +, STDELOGIC:
CS) .!- STDELOGIC
%:
0,:
/4HL+-0H-!40 V1 .1 DECODERE55 +>
30J+,
CS 98 A7 .4 A6 .4 A5 .4 #,.- A4% .4 A3 .4 BLE
0, V1:
53 700
51 $he counter is latched then the counter read9bac% control reads the counter at the
time o# the latchin"
4/ $he motor attempts to move #orward and reverse #or e=ual amounts o# time $his
causes it to remain stationary
47 $he number o# transmitted bits per second includin" data, start, stop and any other
bits that are trans#erred
45 4/6,600 H?
43 $he FR input pin resets the device
41 /0 Ts
37 /00 Ts
35 Start conversion
Chapter Twelve
/ !n interrupt interrupts the currently e:ecutin" pro"ram
7 $he interrupt service procedure is called by an interrupt
5 NF,, ,N$R, and
,N$!
3 $he interrupt vector is the address o# the interrupt service procedure
1 854
// ,N$ 0 occurs #or a divide error
/7 ! real mode interrupt vector is 6 bytes in len"th and contains the se"ment and
o##set address o# the interrupt service procedure, while a protected mode interrupt
vector is 2 bytes in len"th and contains the selector and 789bit o##set address o# the
interrupt service procedure
/5 $he -OUN* instruction tests the contents o# a /49bit re"ister with two numbers
stored in the memory ,# the re"ister contains a number that is outside o# the
boundaries set by the memory data, ,N$ 5 occurs
/3 ,N$ 66H is stored at vector locations //0HG//7H
/1
/1 ,N$ 3 is used to emulate a coprocessor
8/ $he , #la" controls whether the ,N$R pin si enabled or disabled
87 CH, and S$, clear and set the interrupt #la"
85 ,N$ 8
83 Hevel
81 Eector
7/
D 0 - D 7
D 7
# I # T A
V C C
U 1
7 4 A L S 2 4 4
2
4
6
8
1
1 8
1 6
1 4
1 2
1 1
1 3
1 5
1 7
9
7
5
3
1 9
A 1
A 2
A 3
A 4
1 O E
Y 1
Y 2
Y 3
Y 4
A 5
A 6
A 7
A 8
Y 5
Y 6
Y 7
Y 8
2 O E
1
1 0 K

77 $he pull9ups #orce the inputs o# the data bus to &&H when the interrupt
ac%nowled"e cycle e:ecutes
75 Since the si"nals are ORed to"ether to "enerate the interrupt, the only way to
determine which device caused the interrupt is to as% 'poll( the devices
73 1
71 $he C!S pins are used to cascade the 2851
6/ $he ,C; is the initiali?ation control word
67 7
65 H$,F in ,C;/
63 $he nonspeci#ic end o# interrupt is used to clear the most recent interrupt re=uest
61 $he interrupt re=uest re"ister can be used to determine the levels #ound on the
interrupt inputs
5/ ,N$ 30H throu"h ,N$ 33H
Chapter Thirteen
/ HOH* and HH*!
7 Femory to ,<O
5 !0G!3 and *0G*3 'where address bits !2G/5 appear(
3 ! memory9to9memory *F! trans#er occurs when one channel addresses the
source address and another channel address a destination address *ata are then
trans#erred #rom source to destination
1 $he *F! controller is in its hold state and the microprocessor operates normally
// 8008H and 8007H
80
/7 46P
/3 Ficro
/1 Sectors
8/ NRR recordin" is used because it erases old data when it records new data
85 $he dis% heads must be par%ed over a landin" ?one when power is removed so the
heads do not dama"e the sur#ace o# the dis%
83 ! write once optical dis% such as a C*9R or *E*9R
81 63D bytes
7/ Red, "reen, and blue
77 $he smallest video picture element
75 -y usin" 8 levels o# bri"htness #or each o# the three primary colors
73 -ecause the analo" si"nal are continuously variable an in#inite number o# colors
are possible
71 560
Chapter Fourteen
/ ,nte"er, -C*, and #loatin"9point
7 ! -C* number is stored in /0 bytes o# memory with 1 bytes containin" the -C*
inte"er ma"nitude as pac%ed -C* and the /0
th
byte containin" only the si"n o# the
number
5 'a( 0 /00000// //00//0000000000000000
'b( 0 /000/000 00///00000000000000000
'c( / ///////0 0/00000000000000000000
'd( 0 00000000 0000000000000000000000
'e( / /000/000 ////0/000/000000000000
3 $he coprocessor may be idle or it may e:ecute a coprocessor instruction at the
same time
1 $hese bits indicate the relative si?e o# a number a#ter a test or compare instruction
as well as i# the number is valid or invalid
// !n error bit
/7 -y pro"rammin" the roundin" control bits in the coprocessor control re"ister
/5 &&&2HG&&&&H
/3 ! N!N 'not a number( is a number with an e:ponent o# all ones and a si"ni#icand
not e=ual to ?ero
/1 $runcate
8/ +SC
87 'a( &ROD *N 8766 'b( *!$!7 ** G/87 'c( *!$!H ** G872
'd( *!$!8 *N @
85 !n inte"er is loaded #rom memory location *!$! to the top o# the stac%
83 &!** 'no operands( pops the top two stac% elements and adds them then returns
the sum 'pushes( to the top o# the stac%
81 ,t stores the -C* version o# the top o# the stac% into memory location *!$! hen
it pops the stac%
8/
7/ $he &COF, instruction replaces the &COF, &S$S; !I, and S!H& instructions
77 Usually an &COF, instruction must appear be#ore an &CFOE
75 &$S$ compares S$ a"ainst ?ero, while &I!F chan"es the status #la"s to indicate
the type o# number at S$ 'positive, ne"ative, a N!N, etc(
73 ,+
71 &H*/
6/ &S$+NE
67 AREA PROC NEAR
FLD L
FM&L (
FSTP A
RET
AREA ENDP
65 ROOT PROC NEAR
MOV ECX,9
MOV EBX,OFFSET ROOTS
?REPEAT
MOV EAX,11
S&B EAX,ECX
MOV TEMP,EAX :TEMP +> 01+,0 /> DD
FILD TEMP
FSVRT
FSTP D(ORD PTR @EBXA
ADD EBX,4
?&NTILCXB
RET
ROOT ENDP
63 One does a wait the other does not
61 COS PROC NEAR
MOV TEMP,EAX
FLD TEMP
FLDPI
FADD ST,ST#0%
FDIV
FCOS
FSPT TEMP
MOV EAX,TEMP
RET
COS ENDP
5/ M&LT PROC NEAR
MOV TEMP,EBX
FLDPI
FLD TEMP
FM&L
FSTP TEMP
MOV EBX,TEMP
RET
M&LT ENDP
57 LOG10 PROC NEAR
FLD1
FXCH ST#1%
FUL2X
FILD TEN
FLD1
88
FXCH ST#1%
FUL2X
FLD1
FDIVR
FM&L
RET
TEN D( 10
55 $he multimedia e:tension allows inte"er arithmetic and lo"ic on multiple data
with a sin"le instruction
53 $he FF re"isters use the coprocessor stac% re"isters
51 Unsi"ned saturation is where the carry is dropped a#ter the addition or borrow
a#ter a subtraction
4/ MOV ECX,64
REPEAT
PMOV MM0,V(ORD PTR ARRAU1@ECXW8N8A
PM&LL( MM0,V(ORD PTR ARRAU2@ECXW8N8A
PMOV V(ORD PTR ARRAU3@ECXW8N8A
PMOV MM0,V(ORD PTR ARRAU1@ECXW8N8A
PM&LH( MM0,V(ORD PTR ARRAU2@ECXW8N8A
PMOV V(ORD PTR ARRAU3@ECXW8N8P256A
?&NTILCXB
47 Streamin" S,F* e:tensions
45 6
43 !n octal word is a /829bit wide number
Chapter Fifteen
/ ,ndustry Standard !rchitecture
7 ,t was lon" a"o, but today because o# its relatively low speed, it is only suited to
,<O e:pansion
5
A 1 1
A 2
A 3
A 1 2
A 8
A 1 3
U 1 8 2 C 5 4
1 9
2 0
1 0
1 3
1 7
8
7
6
5
4
3
2
1
1 1
1 4
1 6
9
1 5
1 8
2 2
2 3
2 1
A 0
A 1
O U T 0
O U T 1
O U T 2
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
G 0
G 1
G 2
C L K 0
C L K 1
C L K 2
D
W
C S
A 1 4
U 2 G A L 2 2 L V 1 0 C / L C C
2
3
4
5
6
7
1 7
1 8
1 9
2 0
2 3
2 4
2 5
2 6
2 1
2 7
9
1 0
1 1
1 2
1 3
1 6
2 8
I / C L K
I
I
I
I
I
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I
I
I
I
I
I
V C C
A 1 5
A 1
A 0
A 7
# I O R
# I O W
A 5
V C C
A 6
A 1 0
A 9
A 4
3
87
A 1
A 1 1
U 1 7 4 A L S 3 7 4
3
4
7
8
1 3
1 4
1 7
1 8
1
1 1
2
5
6
9
1 2
1 5
1 6
1 9
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
O E
C L K
" 0
" 1
" 2
" 3
" 4
" 5
" 6
" 7
A 2
A 7
A 0
A 1 4
A 1 2
A 5
V C C
A 6
A 4
A 8
D 0 - D 7
A 1 5
A 9
A 3
# I O R
U 2 7 4 A L S 2 4 4
2
4
6
8
1
1 8
1 6
1 4
1 2
1 1
1 3
1 5
1 7
9
7
5
3
1 9
A 1
A 2
A 3
A 4
1 O E
Y 1
Y 2
Y 3
Y 4
A 5
A 6
A 7
A 8
Y 5
Y 6
Y 7
Y 8
2 O E
U 3 7 4 A L S 2 4 5
2
3
4
5
6
7
8
9
1 9
1
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
G
D I
B 0
B 1
B 2
B 3
B 4
B 5
B 6
B 7
A 1 3
A 1 0
U 4 G A L 2 2 L V 1 0 C / L C C
2
3
4
5
6
7
1 7
1 8
1 9
2 0
2 3
2 4
2 5
2 6
2 1
2 7
9
1 0
1 1
1 2
1 3
1 6
2 8
I / C L K
I
I
I
I
I
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I / O
I
I
I
I
I
I
V C C
# I O W
/7 On the #irst positive ed"e o# the cloc% a#ter
&R!F+
"oes low
/5 Plu" and Play is where the computer polls the PC, cards in a system to determine
what interrupts are re=uired and also the type o# the card
/3 ,# operatin" in *OS, the -,OS is tested #or PC, i# an 0-/0/H is placed in !I
#ollowed by an ,N$ /!H ,# carry is set upon return PC, is not present
/1 Speed and data width
8/ 732HG73&H
87 85 pins
81 NRR
7/ &or many applications it has replaced the ,S! and PC, bus
77 Non9return to ?ero inverted
75
# R $ I
D % & % t ' ( D ' t '
86
73 !CP ac%nowled"es the receipt o# data and N!P does not ac%nowled"e the
receipt o# data
71 8 D-ps
Chapter Sixteen
/ $he main di##erences are the internal timers, the chip selection unit, the additional
interrupt inputs, and in some models the serial communications ports and the
enhanced 69channel *F! controller
7 Headless chip carrier 'HCC( and pin "rid array 'PD!(
5 $he main di##erence is that the +- version contains /0 chip selection pins and a
pair o# serial communications ports
3 6
1 Femory access time is the amount o# time that the microprocessor allows the
memory to loo% up data ,# not enou"h time e:ists, wait states are inserted to allow
additional time #or access
// ,<O ports &&00HG&&&&H
/7 ,N$ /8<,N$ 0CH
/5 Faster and slave modes are available
/3 /
/1 $he +O, re"ister is used to clear the interrupt #rom the microprocessor ,# not, the
interrupt will never occur a"ain
8/ $imes 0 and /
87 ,# both compare re"isters are used one determines the len"th #or the lo"ic 0 output
and the other determines the len"th o# the lo"ic / output
85 $he P bit selects the system cloc% as the input to the timer
83 $he timer output pins are used to provide wither a sin"le pulse or an output with a
selectable lo"ic / and lo"ic 0 time
81 MOV AX,0
MOV DX,0FF50H
O&T DX,AX
MOV AX,105
MOV DX,0FF52H
O&T DX,AX
MOV AX,0C008H
MOV DX,0FF56H
O&T DX,AX
7/ 80
77 4
75 &&&&H
73 00000H
71 MOV AX,1F44H
MOV DX,0FFA8H
O&T DX,AX
6/ MOV AX,2002H
MOV DX,0FF8CH
O&T DX,AX
MOV AX,300AH
85
MOV DX,0FF8EH
O&T DX,AX
67 /4F
65 2024
63 Hoads the se"ment limit
61 Fultiple threads are handled by a scheduler that starts a new thread on each tic%
o# the scheduler
Chapter Seventeen
/ 6D
7 $he *I has a #ull 78 bit address bus, while the SI is a scaled down version with
a 869bit address bus
5 6 or 5 m! dependin" on the pin compared to the 2024 which has 8 m! on each
output pin
3 ! hardware reset causes the address bus to start at memory location &&&&&&&0H
1 ! cache memory is a hi"h9speed store o# data and<or instructions -ecause the
main memory is relatively slow, when data or instructions are accessed a second time,
they are accessed #rom the cache at a hi"h speed increasin" system per#ormance
// 200000&2HG200000&&H
/7 60FH?
/5 CR0 mainly selects protected mode and pa"in", CR/ is reserved by ,ntel, CR8
contains the linear #ault address #or debu""in", and CR7 contains the base address o#
the pa"e directory
/3 INT 1 or type /
/1 MOV EAX,CR0
8/ MOV FS)@DIA,EAX
87 Bes
85 Coprocessor not available interrupt
83 $he double #ault interrupt occurs when two interrupts occur simultaneously
81 ! descriptor describes a memory se"ment, or a "ate
7/ $he $, bit in the selector is set to select the local descriptor table
77 2P
75 ! se"ment descriptor de#ines a memory se"ment and a system descriptor de#ines
a memory location #or a call or interrupt or a tas% state se"ment
73 $he $SS is address by the tas% re"ister
71 $he switch occurs when a 0 is placed into the P+ bit o# CR0
6/ ;here ever he pro"rammer decides to place it as dictated by CR7
67 $he entry in the pa"e table and entry that corresponds to address *0000000H
contains a C0000000H
65 $he
&HUSH
input causes the internal cache to be erased
63 $he #la"s are almost identical e:cept #or the !C #la"
61 +ven
5/ /4
84
57 ! cache write9throu"h is when data are written into the cache and the *R!F at
the same time
Chapter Eighteen
/ 6D bytes
7 46 bits
5 44 FH?
3 !ddress parity
1
-R*B
// ,# the instructions are not dependent then two can be e:ecuted simultaneously,
one by each inte"er unit
/7 52 ns
/5 $he
SF,
input causes an interrupt to the system memory mana"ement interrupt at
address 72000H unless chan"ed to some other location in the #irst /F byte o#
memory
/3 $he SFF is e:ited by usin" the RSF instruction
/1 Fodi#y the dump base address re"ister at locations 7&+&2HG7&+&-H
8/ /
87 CR6
85 $he $SC counts system cloc% pulses in a 469bit counter located within the
microprocessor ,t can be used to time events by storin" its value when the event
be"ins and at the end o# the event read $CS and subtract the stored number to obtain
the count in cloc% pulses
83 $he ban% enable si"nals are multiple:ed with address '!/5G!2( in#ormation and
must be e:tracted #rom the address bus durin" the second cloc% cycle o# a bus cycle
81 P!+ and PS+ have been added to control the additional address bits '!78G!75(
7/ +rror correction code
Chapter Nineteen
/ 78P
7 $he Hevel 8 cache operated at the bus speed '44 FH?( in the Pentium and at W
the microprocessor speed in the Pentium ,,
5 8
3 No, the Pentium ,, is on a cartrid"e
1 Used #or serial messa"es between the Pentium ,, and !P,C
// 44 FH? or /00 FH?
/7 38 bits
/5 Eersion number and #eatures have been added to CPU,*
83
/3 MOV ECX, 175H
MOV EDX,0
MOV EAX,12H
(RMSR
/1 SBS+I,$
8/ Rin" 0
87 &S!E+ saves the state o# the coprocessor and &IS!E+ saves the state o# the
FFI unit
85 S,F* e:tension SS+8
82