I N VE N TI V E

Netlist Based IR Drop and Electromigration

Analysis Flow in Virtuoso
Virtuoso UltraSim
UltraSim
Irshad Alam
Custom IC Technical Field Operations, Cadence Design Systems (I) Pvt. Ltd.

USIM EMIR Analysis :

Agenda
Overview
Flow
Setup
Results
Conclusion
Q&A

October 18, 2007

USIM EMIR Analysis :

Overview
Overview
Flow
Setup
Results
Conclusion
Q&A

October 18, 2007

USIM EMIR Analysis : Overview

IR Drop & Impact
Vdd

R
I

Circuit

Every chip will have IR Drop

Designers need to understand impact of
IR Drop on functionality
Functional (Logic level) change due to
noise margin reduction
10% IR drop may increase delay upto 8%
Timing failures due to circuit slow down
or speedspeed-up

October 18, 2007

R
Vss

Vdd- V
CL

USIM EMIR Analysis : Overview

EM Effect & Impact
High Current Density with ULSI
microelectronic circuits
Material Degradation due to Current
Driven Migration of Metal Atoms
Defects like Voids or Hillocks
Cause interruptions or Short cuts in
the line
Signal Degradation causes Design
Failure

October 18, 2007

USIM EMIR Analysis : Overview

Existing Flow : VAVO/VAEO
Two Analysis Options in Virtuoso Platform
Virtuoso Analog VoltageStorm Option (VAVO)
Power Integrity Verification
IR Drop (Power & Ground rails)
Power Rail Electromigration

Virtuoso Analog Electron Storm Option (VAEO)

Signal Electromigration

Flow Dependency on other Cadence products

Assura
Assura--LVS
AssuraAssura-RCX
Spectre or UltraSim

October 18, 2007

USIM EMIR Analysis : Overview

Motivation

VAVO/VAEO provides EM/IR solutions for small and

medium size analog designs with powerful display features
VAVO/VAEO doesn
doesnt provide solution for larger designs
(>20K MOS) due to capacity limitation
VAVO/VAEO doesn
doesnt provide a solution for customers using
extraction tools other than Assura

October 18, 2007

USIM EMIR Analysis : Flow

Overview
Flow
Setup
Results
Conclusion
Q&A

October 18, 2007

USIM EMIR Analysis : Flow

Basic Flow Chart
Prelayout Netlist

DSPF/SPEF File

.usim_emir

R-coordinates, W, L

UltraSim
(32/64 Bit)

Design.emir0_bin
Design_phys.data
Design_phys.field
Design_phys.layer
Design_phys.name

October 18, 2007

Binary Database

Control File

UsimEmirUtil

Original Layout

Violation in VLE
(CDB, OA)

USIM EMIR Analysis : Flow

DFII GUI Flow

10

October 18, 2007

USIM EMIR Analysis :

Setup
Overview
Flow
Setup
Results
Conclusion
Q&A

11

October 18, 2007

USIM EMIR Analysis : Setup

Step 1 : Required Files

Prelayout Netlist File
Models
DSPF/SPEF files with necessary geometry information
EM Data File containing current density limits per layer
usimEmirUtil Control File (dictates how the violation maps are
generated)
Original layout design in DFII database to overlay the violation
maps on top of the original

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October 18, 2007

USIM EMIR Analysis : Setup

Step 2 : Define .usim_emir

.usim_emir [type=all | selected] [nets=net1 net2 ] format=[layout]
[start=time] [stop=time]
Type

- all
all : All the nets and resistors are considered
- selected
selected : User must explicitly specify nets
- Default is all
all

Nets

- Specify the nets for which the necessary information are

saved in the database
- Applicable only when type=selected
type=selected

Format

- layout
layout : To be specified for Netlist Based Flow

Start/Stop

- Define time window

- Default is beginning and end time of the transient
simulation

Example : .usim_emir type=selected nets=[vdd

nets=[vdd gnd]
gnd] format=layout
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October 18, 2007

USIM EMIR Analysis : Setup

Step 3 : usimEmirUtil
usimEmirUtil layout db dbFilename control Control_filename lib
LibName cell CellName view ViewName text TextFile log LogFile
dbFilename

- Binary data file [netlist.emir0_bin]

Control_filename

- Control File

LibName

- Library name of the Violation Map

CellName

- Cell name of the Violation Map

ViewName

- View name of the Violation Map

TextFile

- File name of the textual EM & IR Report

LogFile

- EmirLog filename [UsimEmirUtil.emirlog]

Example : usimEmirUtil layout db ./design/input.emir0_bin control

./design/control.txt lib myLib cell adc view new_emir

14

October 18, 2007

USIM EMIR Analysis : Setup

usimEmirUtil Control File
color level = 8
layout format = [cdb]
pwnet net=[i1.vdd] analysis=[vmax iavg] net=[i1.vss] analysis=[vmax
analysis=[vmax iavg]
signal net=[i1.*] analysis=[iavg]
emdata file = ./design/emDataFile.txt
./design/emDataFile.txt
report text=1

15

color

- Define number of colors [Default=10]

layout format

- Defines what format used for Violation Map

- Available options : cdb, oa, none

emdata file

- Specifies file containing Current Density Limits per layer

pwnet

- Defines nets for IR Analysis

- Analysis Options : vmax, vavg, imax, iavg

signal

- Defines nets for EM Analysis

- Analysis Options : vmax, vavg, imax, iavg

report

- 1 : Print Textual Report [Default]

- 0 : No Textual Report

October 18, 2007

USIM EMIR Analysis : Results

Overview
Flow
Setup
Results
Conclusion
Q&A

16

October 18, 2007

USIM EMIR Analysis : Results

Textual Report
IR
Report

17

October 18, 2007

EM
Report

USIM EMIR Analysis : Results

IR Report in GUI
Choose Tap,
Internal or All

Text
Sub window

Navigate
Pins

Color Bins
18

October 18, 2007

Cross
Probing

USIM EMIR Analysis : Results

IR Report in GUI

Full IR Drop
Violation
Map for
i1.vss
i1.vss net

19

October 18, 2007

USIM EMIR Analysis : Results

IR Report in GUI

Full IR Drop
Violation
Map for
i1.vss
i1.vss net
on top of the
Original
Layout

20

October 18, 2007

USIM EMIR Analysis : Results

IR Report in GUI

Cross Probing

21

October 18, 2007

USIM EMIR Analysis : Results

EM Report in GUI
Choose
Analysis Type

Text
Sub window

Navigate
Pins

Color Bins
22

October 18, 2007

Cross
Probing

USIM EMIR Analysis : Results

EM Report in GUI

Violation
Map of
Average
Current
Density for
i1.vdd
i1.vdd

23

October 18, 2007

USIM EMIR Analysis : Results

EM Report in GUI

Full Chip
Violation
Map

24

October 18, 2007

USIM EMIR Analysis : Results

EM Report in GUI

Cross Probing

25

October 18, 2007

USIM EMIR Analysis : Conclusion

Overview
Flow
Setup
Results
Conclusion
Q&A

26

October 18, 2007

USIM EMIR Analysis : Conclusion

UltraSim Netlist based EM/IR flow complements

VAVO/VAEO flow
UltraSim hierarchical stitching technique provides much
needed Capacity for large designs
Independent of the Extraction Tool
Supports overlaying the violation map over the layout in VLE
Cross referencing between violation report and layout
Searching/Sorting functionality in the violation report

27

October 18, 2007

USIM EMIR Analysis : Conclusion

Overview
Flow
Setup
Results
Conclusion
Q&A

28

October 18, 2007