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LAB 3: Carry Look Ahead Adder Simulations With Verilog-XL: Roza Gunes Bayrak, Barbara Gyasi - November 13, 2014
LAB 3: Carry Look Ahead Adder Simulations With Verilog-XL: Roza Gunes Bayrak, Barbara Gyasi - November 13, 2014
Abstract
In the previous lab logic primitives: inverter, NAND2, NOR2, NAND3 and XOR2 were constructed in
Verilog-XL. These primitives are used to design of a Carry Look Ahead Adder(CLAA) in Part II of this
exercise.
To reduce the computation time, CLAA work by creating two signals P and G known to be Carry
Propagator and Carry Generator. The carry propagator is propagated to the next level whereas
the carry generator is used to generate the output carry (1), regardless of input carry. The block
diagram of a n-bit Carry Lookahead Adder is shown here below -
PART II
1. 1-bit Carry Look Ahead Full Adder
Figure 2: Schematic view of 1-bit CLA full adder with P and G output signals
Propogation Delay
Results(ns)
Cout
S7
S6
S5
S4
S3
S2
S1
S0
1000 0000
21
19
17
15
13
11
3. 2s Complement
References
1. http://virtual-labs.ac.in/labs/cse10/cla_design.html