LAB 3: Carry Look Ahead Adder

Simulations with Verilog-XL

Roza Gunes Bayrak, Barbara Gyasi - November 18, 14 (edited)

Abstract
In the previous lab logic primitives: inverter, NAND2, NOR2, NAND3 and XOR2 were constructed in
Verilog-XL. These primitives are used to design of a Carry Look Ahead Adder(CLAA) in Part II of this
exercise.
To reduce the computation time, CLAA work by creating two signals P and G known to be Carry
Propagator and Carry Generator. The carry propagator is propagated to the next level whereas

the carry generator is used to generate the output carry (1), regardless of input carry. The block diagram of a n-bit Carry Lookahead Adder is shown here below Figure1: CLAA Block Diagram
The number of gate levels for the carry propagation can be found from the circuit of full adder. The
signal from input carry C0 to output carry Cout = Cn requires NAND and XOR gates in our design.
Pi = Ai Bi
Gi = Ai Bi
Sumi = Pi Ci
Ci+1 = Gi + ( Pi Ci)

PART II
1. 1-bit Carry Look Ahead Full Adder
Figure 2: Schematic view of 1-bit CLA full adder with P and G output signals

2. 8-bit Carry Look Ahead Full Adder

Figure 3: Schematic view of 8-bit CLA Full Adder

Figure 4: Symbol of 8-bit CLAA

Table 1: Stimuli for all Verilog-XL Simulations

Figure 5: Simulation results of the adder stimuli

Propogation Delay Results(ns)

Cout

S7

S6

S5

S4

S3

S2

S1

S0

1000 0000

21

19

17

15

13

11

0000 1110 (Cout=1)

Table 2: Propagation Delay Results for the Adder Design

3. 2s Complement
Figure 7: Schematic view of 2s Complement Generator

Figure 8: Verilog-XL Simulation Results of 2s Complement Generator

4. 8-bit CLA Adder/Subtractor

Figure 9: Schematic view for the Adder/ Subtractor Unit

Figure 10: Adder/Subtractor Symbol view

Figure 11: Verilog-XL Simulation Results for Subtractor Design

Propogation Delay Results(ns)

Cout

S7

S6

S5

S4

S3

S2

S1

S0

0111 1111 (Cout=1)

26

24

22

20

18

16

14

12

1111 0000

10

12

18

Table 3: Propagation Delay Results for the Subtractor Design