SKR Engineering College

Department of Electronics and Communication Engineering

Internal Test - 1
AP7202 ASIC AND FPGA DESIGN
Date :22.10.2013
Year / Sem :I/I

Time
Max Marks

Part A
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

: 03hrs
: 100
(10 x 2 = 20 marks)

Define cutset?
Define simulated Annealing?
Difference between PLA and PAL?
Define clock Latency?
What is meant by Back Annotation?
Define DRC?
What is slicing floor plan ?
Difference between FPGA and ASIC ?
What is the use of dogleg?
Difference between constructive and Iterative partitioning?

Part B (any FIVE)

(16x5=80 marks)

11. Explain in detail about Programming technology with neat diagram?

12. (i).Describe the types of ASICs in detail with neat diagram? (8M)
(ii).Draw ASIC Design flow and explain? (8M)
13. (i).Explain KL algorithms in detail with neat diagram? (10M)
(ii).Explain Look ahead Algorithm?(6M)
14. Explain channel routing Algorithm and the area routing algorithm in detail?
15. Explain Global routing in detail with neat diagram?
16. Explain placement concepts with any one algorithm?
17. Explain in detail about the concepts of floor planning with neat diagram?
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX