Total No.

of Questions :8]

[Total No. of Pages : 2

P1922
[3765]-573 M.E. (VLSI & Embedded Systems) ANALOG & DIGITAL CMOS IC DESIGN ( 2008 Course)
Time :3 Hours] [Max. Marks : 100

Instructions to the candidates: 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams should be drawn wherever necessary. 4) Use of electronic pocket calculator is allowed. 5) Assume suitable data, if necessary.

SECTION - I Q1) a) b) Q2) a) b) Q3) a) b) Explore current sink & source. What are the voltage compliances? How to improve them? [8] Design CMOS amplifier for voltage gain of 50, band width of 100 MHz. Compute Rout. [8] What are the techniques of voltage references? What are their performance parameters. [8] What is necessity of Bandgap reference? Brief the concept with mathematical expressions. [8] Design cascode amplifier for voltage gain of 40 dB. Compute Rout. Estimate bandwidth. Assume suitable data. [8] List and explain the techniques to improve bandwidth. [8] [18]

Q4) Write short notes on any three : a) b) c) d) Output amplifiers. Micropower opamp. Inverters & performance parameters. MOSFET as active resister. SECTION - II

Q5) Draw FSM diagram & write VHDL code for Tea/Coffee vending machine. Also write test bench assume suitable inputs & outputs. [16] P.T.O.

Q6) a) b) Q7) a) b) a) b) c) d)

Why is synchronization needed? What are the methods to achieve? [8] What are the sources & elimination techniques of hazards? [8]

Derive the expressions for static & dynamic dissipations. Compare them w.r.t technology scaling. [8] Design CMOS logic for F= ABCD + E (F + G). Compute area on chip.[8] [18] MOSFET sizing. Technology scaling & its effects. Transmission gate & its applications. NDRA logic.

Q8) Write short notes on any three :

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[3765]-573

Total No. of Questions :8]

[Total No. of Pages : 2

P1942
[3765]-579 M.E. (E & TC/ Electronics) (VLSI & Embedded Systems) MEMORY TECHNOLOGIES (Elective - II) ( 2008 Course) (Sem. - I)
Time :3 Hours] [Max. Marks : 100

Instructions to the candidates: 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Figures to the right indicate full marks. 5) Assume suitable data, if necessary.

SECTION - I Q1) a) b) Compare DCTL and ECL bipolar SRAM technologies. [8]

What is SOI technology? Enlist different SOI technologies. Hence draw and explain cross section of thin film SOI CMOS inverter. [10] Compare and Contrast bipolar and CMOS PROMs. [8]

Q2) a) b)

What is FLOTOX technology? Draw schematic of FLOTOX transistor structure and explain its operation with an energy band diagram. [8] Explain pattern sensitive faults. Support your answer with a suitable schematic. [8] Draw basic scheme for pseudo random testing and explain. [8]

Q3) a)

b) Q4) a)

Explain stack capacitor cell. What are its advantages over trench capacitor cell? [8] Write a short note on flash memory cell. [8]

b)

P.T.O.

SECTION - II Q5) a) b) Comment on semiconductor dielectric interface failures. Explain the following charge loss mechanisms for EPROMs. i) ii) iii) DC Erase. Program Disturb. DC Programming. [8] [8] [10] [8] [8] [8]

iv) Charge loss due to bake stressing. Q6) a) b) Q7) a) b) Q8) a) Explain total dose effect. Discuss radiation hardening process issues. Explain principle, construction and operation of FRAM cell. Write a short note on MRAM (Magneto-resistive RAM)

Compare insertion mount and surface mount technology with reference to memory packaging technology. [8] Explain 3-D memory cube technology. [8]

b)

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[3765]-579