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Digital Logic Design Lab

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K-Map simplification &

Magnitude comparator

TITLE

DATE OF
EXPERIMENT

: O1st December, 2014

LAB NUMBER

INSTRUCTOR
SUBMITTED BY
ROLL NO

: 08

: MUQARRAB BASEER
: _________________________
:

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Four Variable K-Map

Digital Logic Design Lab

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Four-variable K-Map: Observations

One square represents one minterm a term of 4 literals
Two adjacent squares
a term of 3 literals
Four adjacent squares
a term of 2 literal
Eight adjacent squares
a term of 1 literal
Sixteen adjacent squares
the function equals to 1

Digital Logic Design Lab

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Task-1:
One Bit Magnitude Comparator:
One Bit Magnitude Comparator is combination logic circuit which is used to compare
two input binary numbers (each having one bit length) to check weather two inputs are
equal or one less than other or greater then.
First of all we write Truth Table of 1 Bit Magnitude Comparator i.e.

Truth Table .

Inputs

Outputs

Ex=y

Gx>y

Lx<y

Task-2: 2 Bit Magnitude Comparator

Two Bit Magnitude Comparator which is used to compare two input binary numbers
(each having bit length of two ) to check weather two inputs are equal or one less
than other or greater then.
First of all we write Truth Table of 2 Bit magnitude Comparator.
Truth Table .

Inputs
A

Outputs
B

A1

A0

B1

B0

Digital Logic Design Lab

Ex=y

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Gx>y

Lx<y

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Task: 03
Use K-Map to minimize the following SOP expressions and implement the simplified
form.

BC+ABC+ABC+ABC
BCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD

Digital Logic Design Lab

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