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END COmponent;
COMPONENT INV_1
PORT( E: IN STD_LOGIC; F: OUT STD_LOGIC);
END COmponent;
for v0:and3 use entity work.and3(and3);
for v4:or4 use entity work.or4(or4);
for u0:inv_1 use entity work.inv_1(inv_1);
SIGNAL S0BAR,S1BAR,W,X,G,Z: STD_LOGIC;
BEGIN
U0: INV_1 PORT MAP (S0,S0BAR);
U1: INV_1 PORT MAP (S1,S1BAR);
V0: AND3 PORT MAP (A,S1BAR,S0BAR,W);
V1: AND3 PORT MAP (B,S1BAR,S0 ,X);
V2: AND3 PORT MAP (C,S1 ,S0BAR,G);
V3: AND3 PORT MAP (D,S1 ,S0 ,Z);
V4: OR4 PORT MAP ( W,X,G,Z,Y);
end MUX_STRU;
--1-bit comparator using behavioral style.
entity comp is
port ( a: in bit_vector(0 to 1);e: out bit_vector(2 downto 0));
end entity;
architecture comp_beha of comp is
begin
process(a)
variable temp : bit;
begin
case a is
when "00" => e <="100";
when "01" => e <="010";
when "10" => e <="001";
when "11" => e <="100";
when others => null;
end case;
end process;
end architecture;
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begin
process(a,b)
begin
if(a>b) then
agtb<= '1';
aeqb<='0';
altb<= '0';
elsif(a<b) then
agtb<= '0';
aeqb<='0';
altb<= '1';
elsif(a=b)then
agtb<= '0';
aeqb<='1';
altb<= '0';
end if;
end process;
end \4_comp_beh\;
--4-bit comparator using structural style model.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity \4_comp_stru\ is
port(
a : in STD_LOGIC_VECTOR(0 to 3);
b : in STD_LOGIC_VECTOR(0 to 3);
aeqb : inout STD_LOGIC;
agtb : inout STD_LOGIC;
altb : out STD_LOGIC
);
end \4_comp_stru\;
architecture \4_comp_str\ of \4_comp_stru\ is
component xnor2
port(l,m: in std_logic;n: out std_logic);
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end component;
component and2
port(x,y: in std_logic; z: out std_logic);
end component;
component inv
port (u: in std_logic; v: out std_logic);
end component;
component and3
port(l,m,o: in std_logic;n: out std_logic);
end component;
component or4
port(m1,m2,m3,m4: in std_logic; mf: out std_logic);
end component;
component and4
port(q1,q2,q3,q4: in std_logic; qf: out std_logic);
end component;
component and5
port (e1,e2,e3,e4,e5: in std_logic; ef: out std_logic);
end component;
component nor2
port(l1,l2: in std_logic; lf: out std_logic);
end component;
signal i0,i1,i2,i3,j0,j1,j2,j3,j4,j5,h0,h1,h2,h3: std_logic;
begin
m1: inv port map (b(3),i3);
m2: inv port map (b(2),i2);
m3: inv port map (b(1),i1);
m4: inv port map (b(0),i0);
m5: xnor2 port map (a(3),b(3),j3);
m6: xnor2 port map (a(2),b(2),j2);
m7: xnor2 port map (a(1),b(1),j1);
m8: xnor2 port map (a(0),b(0),j0);
m9: and2 port map (a(3),i3,h3);
m10: and3 port map (a(2),i2,j3,h2);
m11: and4 port map (a(1),i1,j2,j3,h1);
m12: and5 port map (a(0),i0,j1,j2,j3,h0);
m13: and4 port map (j0,j1,j2,j3,aeqb);
m14: or4 port map (h0,h1,h2,h3,agtb);
m15: nor2 port map (aeqb,agtb,altb);
end \4_comp_str\;
--vhdl code for halfadder using data flow style model.
entity ha is
port( a, b: in bit; sum,carry: out bit);
end entity;
architecture ha1 of ha is
begin
sum<= a xor b;
carry<= a and b;
end architecture;
--vhdl code for halfadder using structural style model.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ha is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end ha;
architecture ha_stru of ha is
component xor2
port(l,m: in STD_LOGIC; n: out STD_LOGIC);
end component;
component and2
port(x,y: in STD_LOGIC; z: out STD_LOGIC);
end component;
for x1: xor2 use entity work.xor2(xor2);
for a1: and2 use entity work.and2(and2);
begin
x1: xor2 port map( a, b, sum);
a1: and2 port map(a,b,carry);
end ha_stru;
end component;
component and2
port(x,y: in STD_LOGIC; z: out STD_LOGIC);
end component;
for i1: inv use entity work.inv(inv);
for x1: xor2 use entity work.xor2(xor2);
for a1: and2 use entity work.and2(and2);
signal nota: STD_LOGIC;
begin
i1:inv port map(a, nota);
x1: xor2 port map( a, b, sum);
a1: and2 port map(nota,b,borrow);
end hs_stru;
--vhdl code for full-adder using Behavioral style model.
entity fa is
port( a, b: in bit;carry: inout bit; sum: out bit);
end entity;
architecture fa1 of fa is
begin
process (a,b,carry)
begin
if (a ='0' and b='0'and carry='0') then
sum <= '0';
carry<='0';
elsif(a ='0' and b='1'and carry='0') then
sum <= '1';
carry<='0';
elsif( a='1' and b='0'and carry = '0')then
sum <= '1';
carry <='0';
elsif( a='1' and b='1'and carry= '0')then
sum <= '0';
carry <='1';
elsif( a='0' and b='0'and carry= '1')then
sum <= '1';
carry <='0';
elsif( a='0' and b='1'and carry= '1')then
sum <= '0';
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carry <='1';
elsif( a='1' and b='0'and carry= '1')then
sum <= '0';
carry <='1';
elsif( a='1' and b='1'and carry= '1')then
sum <= '1';
carry <='1';
end if;
end process;
end architecture;
--vhdl code for full-adder using structural style model.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fa is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c: in std_logic;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end fa;
architecture fa_stru of fa is
component xor2
port( l,m:in std_logic;n: out std_logic);
end component;
component and2
port( x,y:in std_logic; z:out std_logic);
end component;
component or2
port (e,f: in std_logic; g: out std_logic);
end component;
for x1 : xor2 use entity work.xor2(xor2);
for x3: and2 use entity work.and2(and2);
for x5: or2 use entity work.or2(or2);
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borrow<= '1';
elsif(a="011") then
diff <= '0';
borrow<= '1';
elsif(a="100") then
diff <= '1';
borrow<= '0';
elsif(a="101") then
diff <= '0';
borrow<= '0';
elsif(a="110") then
diff <= '0';
borrow<= '0';
elsif(a="111") then
diff <= '1';
borrow<= '1';
end if;
end process;
end fs_beh;
--vhdl code for full-Created by bsaitmbtractor using structural style model.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity fsub is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c: in std_logic;
diff : out STD_LOGIC;
borrow : out STD_LOGIC
);
end fsub;
architecture fs_str of fsub is
component xor2
port(l,m: in std_logic;n: out std_logic);
end component;
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component and2
port(x,y: in std_logic; z: out std_logic);
end component;
component inv
port (u: in std_logic; v: out std_logic);
end component;
component or2
port(e,f: in std_logic; g: out std_logic);
end component;
for b1: xor2 use entity work.xor2(xor2);
for b3: inv use entity work.inv(inv);
for b5: and2 use entity work.and2(and2);
for b7: or2 use
entity work.or2(or2);
signal q1,q2,q3,q4,q5: std_logic;
begin
b1:xor2 port map ( a,b,q3);
b2:xor2 port map ( q3,c,diff);
b3:inv port map ( a,q1);
b4:inv port map ( q3,q4);
b5:and2 port map ( q1,b,q2);
b6:and2 port map ( q4,c,q5);
b7: or2 port map (q5,q2,borrow);
end fs_str;
--vhdl code for B2G code converter using data-flow model.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity b2g is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
w : out STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC
);
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end b2g;
architecture b2g_data of b2g is
begin
w<= a;
x<= a xor b;
y<= b xor c;
z<= c xor d;
end b2g_data;
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end b2g_stru;
--vhdl code for G2B code converter using data-flow model.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity g2b is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
w : out STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC
);
end g2b;
architecture g2b_data of g2b is
begin
w <= a;
x <= a xor b;
y <= a xor b xor c;
z <= a xor b xor c xor d;
end g2b_data;
--vhdl code for G2B code converter using behavioral model.
entity g2b is
port(
g : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end g2b;
architecture g2b_beh of g2b is
begin
process (g)
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begin
case b is
when "0000"=> b<="0000";
when "0001"=> b<="0001";
when "0011"=> b<="0010";
when "0010"=> b<="0011";
when "0110"=> b<="0100";
when "0111"=> b<="0101";
when "0101"=> b<="0110";
when "0100"=> b<="0111";
when "1100"=> b<="1000";
when "1101"=> b<="1001";
when "1111"=> b<="1010";
when "1110"=> b<="1011";
when "1010"=> b<="1100";
when "1011"=> b<="1101";
when "1001"=> b<="1110";
when "1000"=> b<="1111";
when others=> null;
end case;
end process;
end g2b_beh;
--vhdl code for G2B code converter using structural style model.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity g2b is
port(
w : in STD_LOGIC;
x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
a : out STD_LOGIC;
b : out STD_LOGIC;
c : out STD_LOGIC;
d : out STD_LOGIC
);
end g2b;
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begin
process (b)
begin
case b is
when "0000"=>excess3<="0011";
when "0001"=>excess3<="0100";
when "0010"=>excess3<="0101";
when "0011"=>excess3<="0101";
when "0100"=>excess3<="0111";
when "0101"=>excess3<="1000";
when "0110"=>excess3<="1001";
when "0111"=>excess3<="1010";
when "1000"=>excess3<="1011";
when "1001"=>excess3<="1100";
when "1010"=>excess3<="1110";
when others => null;
end case;
end process;
end bcd_excess_beh;
--vhdl code for Bcd-2-excess3 code converter using structural style model.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity bcd_excess is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
w : out STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC
);
end bcd_excess;
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en : in STD_LOGIC;
z : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder2_4;
architecture decoder_data of decoder2_4 is
signal s0bar,s1bar:std_logic;
begin
s0bar<= not s0;
s1bar<= not s1;
z(3)<= s0bar and s1bar and en;
z(2)<= s0bar and s1 and en;
z(1)<= s0 and s1bar and en;
z(0)<= s0 and s1 and en;
end decoder_data;
--VHDL Code for decoder 2X4 using behavioral model.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder is
port(
en : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
z : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder;
architecture decoder_beh of decoder is
begin
process(s0,s1,en)
variable s0bar,s1bar: std_logic;
begin
s0bar:= not s0;
s1bar:= not s1;
if (en='1')then
z(3)<= s0bar and s1bar;
z(2)<=s0bar and s1;
z(1)<= s0 and s1bar;
z(0)<= s0 and s1;
else
z<="0000";
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end if;
end process;
end decoder_beh;
--VHDL Code for decoder 2X4 using structural style model
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder is
port(
en : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
z : out STD_LOGIC_VECTOR(0 to 3)
);
end decoder;
architecture decoder_stru of decoder is
component and3
port(l,m,o:in std_logic; n: out std_logic);
end component;
component inv_1
port(e: in std_logic; f: out std_logic);
end component;
for x1: and3 use entity work.and3(and3);
for x5: inv_1 use entity work.inv_1(inv_1);
signal s0bar,s1bar: std_logic;
begin
x1: and3 port map (s0bar,s1bar,en,z(0));
x2: and3 port map (s0bar,s1,en,z(1));
x3: and3 port map (s0,s1bar,en,z(2));
x4: and3 port map (s0,s1,en,z(3));
x5: inv_1 port map (s0,s0bar);
x6: inv_1 port map (s1,s1bar);
end decoder_stru;
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end parity_gen_data;
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