Simulation & Synthesis

Tools in VLSI

By
B.SIDDHARTHA
M.Tech (VLSI Design)
814206100003

Contents
Brief Introduction on simulation & synthesis
Simulation Tools
Synthesis Tools

Brief Intro on Simulation & Synthesis

Simulation:-Simulation is used to verify the functionality of the circuit. a)Functional
Simulation: study of circuits operation independent of timing parameters and gate delays.
b) Timing Simulation: study including estimated delays, verify setup, hold and other
timing requirements of devices like flip flops are met.
1. Today, Simulators are available from many vendors, at all price points. For
desktop/personal use, Aldec, Mentor, LogicSim, SynaptiCAD,TarangEDA and others
offer <$5000 USD tool-suites for the Windows 2000/XP platform and recent versions
and also on linux platforms.
2. The three major signoff-grade simulators include Cadence Incisive Enterprise
Simulator, Mentor ModelSim/SE, and Synopsys VCS. Pricing is not published publicly,
but all three vendors charge $25,000-$100,000 USD per seat, 1-year time-based license.
Mainly on linux platforms.
Synthesis:-One of the foremost in back end steps where by synthesizing is nothing but
converting VHDL or VERILOG description to a set of primitives(equations as in CPLD)
or components(as in FPGA'S)to fit into the target technology. Basically the synthesis tools
convert the design description into equations or components.