Mid Range Family Peripheral Configuration and Assembly Programming

201ASP
Mid-Range Family Peripheral

Configuration and Assembly
Programming
2006 Microchip Technology Incorporated. All Rights Reserved.
201ASP
v8.0
JanuarySlide
20071
Objectives
z
At the end of this class you will:
Understand the basic PICmicro peripherals

and their associated registers
Have HANDS ON experience initializing

Mid-Range peripherals
Be able to implement peripherals not

covered here
Understand interrupts and polling
Write your own application code from

scratch
201ASP
Slide 2
To get the most from this Class

z
Ideally you should be familiar with the

following:
Assembler programming
Basic Mid-Range family Instruction set
Data and Program memory organization
MPLAB Integrated Development Environment
Microchip ICD2 debugger
201ASP
Slide 3
201ASP Agenda
z
Brief review of Mid-Range Architecture,

Instruction Set and Tools
Interrupts on the Mid-Range PICmicro
Interrupts Lab
Peripheral discussion:
Input/Output Ports
Timers
z Timer0
z Timer1
Timer1 Lab
z Timer2
Timer2 Lab
201ASP
Slide 4
201ASP Agenda (cont.)

z
Capture / Compare / PWM Module (CCP)
PWM and Output Compare Labs
Analog Comparator
Analog to Digital Converters (ADC)
ADC Lab
Addressable Universal Asynchronous &

Synchronous Receiver & Transmitter (AUSART)
z I 2C
with the Master Synchronous Serial Port
I2C Based Temp Sensor Lab
Wrap-Up and additional questions
201ASP
Slide 5
Mid-Range Family Basic

Architecture and
Development Tools
201ASP
v8.0
JanuarySlide
20076
Mid-Range PIC Block Diagram

Pages of
Program
Memory
STATUS
PROGRAM COUNTER
REGISTER
8-bit value from instruction
MUX
Banks of Data Memory
ADC
ALU
TIMER0
14-bits
INSTRUCTION REGISTER
WORKING
REGISTER
AUSART
MSSP
PERIPHERALS
201ASP
Slide 7
Program Memory
z
Maximum 8K words
(8K x 14 bits/word)/1 byte

= 14Kbytes of memory
Reset Vector at 0000h
Reset Vector
Program Counter (PC) will

go to this address on
reset
Interrupt Vector at 0004h
Program Counter (PC) will

go to this address upon
any Interrupt
201ASP
0000h
Interrupt Vector 0004h

Page 0
0005h
07FFh
Page 1
0800h
0FFFh
Page 2
1000h
17FFh
Page 3
1800h
1FFFh
Slide 8
Program Counter (PC) and Stack

PCLATH
13-bit PC
PCL ALU result (8-bits) or PCH<12:8>

OPCODE(11-bits)
CALL, RETURN,
RETFIE, RETLW
PCH Paging bits
z
z
Updated from PCLATH

Specifies page in program
memory
PCL
PC<12:0>
Stack Level 1
8 Level Deep Stack
Stores the contents of the PC

z
PUSHES
Stack Level 8
CALL/Interrupt
Program Memory
POPS
RETURN, RETFIE,RETLW
201ASP
Slide 9
Data Memory Map

000h
Special
Function
Registers 01Fh
Special
Function
Registers
020h
128
Bytes
General
Purpose
Registers
080h
SFR
09Fh
0A0h
General
Purpose
Registers
General
Purpose
Registers
0EFh
07Fh
Bank 0
Shared
Shared
0FFh
Bank1
100h
10Fh
110h
General
Purpose
Registers
1EFh
16Fh
Shared
Shared
Bank2
201ASP
SFR
180h
18Fh
190h
17Fh
Shared
Shared
1FFh
Bank3
Slide 10
Special Function Registers (SFRs)

z
z
z
Register File Concept

Accessed like any
other register
Some registers carry
across all banks
(PCLATH, INTCON, etc.)
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
Bank0
201ASP
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
Bank1
Slide 11
Status Register
IRP
RP1 RP0
TO
PD
Contains:
Arithmetic status of the

ALU
The RESET status
Bank select bits for data
memory
RP1
RP1
0
0
1
1
DC
RP0
RP0
0
1
0
1
BANK0
BANK1
BANK2
BANK3
Indirect Register Bank Select bit:

(used for indirect addressing)
1 = Bank 2,3
0 = Bank 0,1
201ASP
Slide 12
PIC16 Instruction Set

z
z
addwf
addwf
andwf
andwf
clrf
clrf
clrw
clrw
comf
comf
decf
decf
decfsz
decfsz
incf
incf
incfsz
incfsz
iorwf
iorwf
movf
movf
movwf
movwf
nop
nop
rlf
rlf
rrf
rrf
subwf
subwf
swapf
swapf
xorwf
xorwf
35 single word instructions

All are single cycle except for program branches
Byte
Byte Oriented
Oriented Operations
Operations
f,d
f,d Add
Add W
W and
and ff
f,d
f,d AND
AND W
W with
with ff
ff
Clear
Clear ff
-Clear
Clear W
W
f,d
f,d Complement
Complement ff
f,d
f,d Decrement
Decrement ff
f,d
f,d Decrement
Decrement f,f, Skip
Skip ifif 00
f,d
f,d Increment
Increment ff
f,d
f,d Increment
Increment f,f, Skip
Skip ifif 00
f,d
f,d Inclusive
Inclusive OR
OR W
W with
with ff
f,d
f,d Move
Move ff
ff
Move
Move W
W to
to ff
-No
No Operation
Operation
f,d
f,d Rotate
Rotate Left
Left ff through
through Carry
Carry
f,d
f,d Rotate
Rotate Right
Right ff through
through Carry
Carry
f,d
f,d Subtract
Subtract W
W from
from ff
f,d
f,d Swap
Swap nibbles
nibbles in
in ff
f,d
f,d Exclusive
Exclusive OR
OR W
W with
with ff
bcf
bcf
bsf
bsf
btfsc
btfsc
btfss
btfss
addlw
addlw
andlw
andlw
call
call
clrwdt
clrwdt
goto
goto
iorlw
iorlw
movlw
movlw
retfie
retfie
retlw
retlw
return
return
sleep
sleep
sublw
sublw
xorlw
xorlw
201ASP
Bit
Bit Oriented
Oriented Operations
Operations
f,b
Bit Clear
Clear ff
f,b Bit
f,b
f,b Bit
Bit Set
Set ff
f,b
f,b Bit
Bit Test
Test f,f, Skip
Skip ifif Clear
Clear
f,b
f,b Bit
Bit Test
Test f,f, Skip
Skip ifif Set
Set
Literal
Literal and
and Control
Control Operations
Operations
kk
Add
Add literal
literal and
and W
W
kk
AND
AND literal
literal with
with W
W
kk
Call
Call subroutine
subroutine
-Clear
Clear Watchdog
Watchdog Timer
Timer
kk
Go
Go to
to address
address
kk
Inclusive
Inclusive OR
OR literal
literal with
with W
W
kk
Move
Move literal
literal to
to W
W
-Return
Return from
from interrupt
interrupt
kk
Return
Return with
with literal
literal in
in W
W
-Return
Return from
from Subroutine
Subroutine
-Go
Go into
into standby
standby mode
mode
Subtract
kk
Subtract W
W from
from literal
literal
kk
Exclusive
Exclusive OR
OR literal
literal with
with W
W
Slide 13
PICmicro Development
Tools
201ASP
v8.0
January
Slide
2007
14
MPLAB IDE
MPLAB IDE (Integrated Development
Environment)
z Integrates different Microchip and third
party tools
z
Code Editor
Cross Compilers
Assemblers
Simulators, In-Circuit Debuggers, Emulators
Programmers
201ASP
Slide 15
MPLAB IDE
MPLAB IDE (Integrated Development
Environment)
z Integrates different Microchip and third
party tools
z
Code Editor
Cross Compilers
Assemblers
Simulators, In-Circuit Debuggers, Emulators
Programmers
201ASP
Slide 16
ICD 2 (In Circuit Debugger)

z
MPLAB ICD 2 is a low cost, real-time

debugger and programmer.
Reading/Writing memory space and

EEDATA areas of the PIC
Programs configuration bits
Real time debugging
Erase of program memory
space with verification
201ASP
Slide 17
PICDEM 2 Plus Board

9V to 5V
regulator
LEDs
16 x 2 LCD
Module
RS232
Connector
Analog Pot
18, 28 and 40pin DIP sockets

ICD
Connecto
r
Piezo
Buzzer
Push button
Switches
I2C Based
Temp Sensor
201ASP
Slide 18
Interrupts
201ASP
v8.0
January
Slide
2007
19
Polling and Interrupts

z
Often we would like the processor to

perform a task if a specific event occurs
Two methods to check if this event has

occurred:
Polling:
z
Continuously check for event at various points in

the code
Interrupts:
z
INTERRUPTS the Main program and starts an

Interrupt Service Routine when an event occurs
201ASP
Slide 20
Polling
bsf
PORTA,1
;Set bit 1 of
;PORTA
btfss INTCON,TMR0IF ;Check Timer0

;interrupt flag
;in INTCON
;register and
;skip the next
;instruction if
;it is set
goto
$-1
;Go to
;previous
;instruction
bcf
PORTA,1
;Clear bit 0 of
;PORTA
201ASP
RA<1>
RA<1>==11
NO
TMR0IF
TMR0IF==11
??
??
YES
RA<1>
RA<1>==00
Slide 21
Interrupts
Reset
code
goto
;=========================
int_vector code 004h
Interrupt Service
Routine (ISR)
retfie
;return from
;interrupt
;=========================
main_prog
no interrupt
000h
Start
Main
Main
program
program
execution
execution
retfie
instruction
interrupt flag
set
Execute
ExecuteISR
ISRat
at
address
address004h
004h
code
Start ;start label for main

code
Main program
code
end
201ASP
Slide 22
Enabling Interrupts
z
Processor must be told that interrupts

will be used
A number of registers with interrupt enable

bits do this:
z
z
z
Interrupt Control (INTCON)

Peripheral Interrupt Enable 1 (PIE1)
201ASP
Slide 23
Interrupt Logic
TMR0IE
TMR0IF
Interrupt
INTE
INTF
RBIE
RBIF
TMR2IE
TMR2IF
GIE
ADIE
ADIF
PEIE
Other peripherals
201ASP
Slide 24
INTCON Register
(Core Interrupts)
Enable Bits
Description
GIE
Global Interrupt Enable
PEIE
Peripheral Interrupt Enable
TMRIE
Must be set to use

any Interrupts
Timer0 Interrupt Enable
INTE
External Interrupt Enable
RBIE
PORTB change Interrupt Enable
GIE
Must be set to use

any Peripheral
Interrupts
PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF

Flag Bits
Flags will set

even if interrupts
arent enabled!
Description
TMR0IF
Timer0 Overflow Interrupt Flag
INTF
RB0/INT External Interrupt Flag
RBIF
PORTB Change Interrupt Flag
201ASP
Slide 25
Enabling a Core Interrupt

Int_vect CODE
004h
;clear external interrupt
;flag to enable
;further interrupts
bcf
INTCON,INTF
<ISR code>
retfie
Main
Start
goto $ address
Program Counter
goto $ address
Stack
INTCON
0 0 0
1
CODE
<code to set up PORTB >
GIE
; initialize INTCON
clrf
INTCON
0
1
INTE
0
1
INTF
Interrupt detected
on RB0/INT Pin!!
;enable an external
;interrupt on the INT pin
bsf
INTCON,INTE
;enable global interrupts
bsf
INTCON,GIE
; sit here and loop forever
goto
$
201ASP
Slide 26
Peripheral Interrupts
z
Two registers ENABLE interrupts for

peripherals

Two registers display peripheral

REQUESTS for an interrupt (Flags)
Peripheral Interrupt Request 1 (PIR1)

Peripheral Interrupt Request 2 (PIR2)
*Flags will set even if

interrupts are not enabled!!
201ASP
Slide 27
PIE1 and PIR1 Registers*

PIE1 Register (Peripheral Interrupt Enables)
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE
PIR1 Register (Peripheral Interrupt Requests)

ADIF
Enable
RCIF
TXIF
SSPIF
Flag
CCP1IF TMR2IF TMR1IF
Condition
ADIE
ADIF
ADC conversion complete
RCIE
RCIF
AUSART receive buffer is full
TXIE
TXIF
AUSART transmit buffer is full
SSPIE
SSPIF
I2C or SPI Interrupt
CCP1IE
CCP1IF
Timer1 register capture or compare match
TMR2IE TMR2IF
Timer2 value and PR2 period value match
TMR1IE TMR1IF
Timer1 register has overflowed
*Check individual datasheets for bit locations

201ASP
Slide 28
PIE2 and PIR2 Registers*

PIE2 Register (Interrupt Enables)
OSCFIE
C2IE
C1IE
EEIE
BCLIE ULPWUIE
CCP2IE
PIR2 Register (Interrupt Flags)

OSCFIF
Enable
C2IF
C1IF
EEIF
Flag
BCLIF ULPWUIF
CCP2IF
Condition
OSCFIE
OSCFIF
System Oscillator Failed
C2IE
C2IF
Comparator2 output changed
C1IE
C1IF
Comparator1 output changed
EEIE
EEIF
Write operation completed
BCLIE
BCLIF
Bus collision occurred in MSSP I2C mode
ULPWUIE
ULPWUIF
Wake-up condition occurred
CCP2IE
CCP2IF
Timer1 Capture or Compare match occurred
*Check individual datasheets for bit locations

201ASP
Slide 29
Int_vect CODE
Main
Start
Enabling a Peripheral (Timer 1)

Interrupt
004h
banksel PIR1
bcf
PIR1, TMR1IF
goto $ address
<ISR code>
retfie
goto $ address
PIR1
PIR1,TMR1IF
PIE1
PIE,TMR1IE
bsf
bsf
INTCON,PEIE
INTCON,GIE
Stack
INTCON
1 1
0
CODE
banksel
bcf
banksel
bsf
Program Counter
GIE PEIE
PIE1
1
TMR1IE
PIR1
0
1
<code to set up Timer1>

; sit here and loop forever
goto
$
Timer1 Overflow!
201ASP
TMR1IF
Slide 30
Interrupt Latency
z
Interrupt Latency:
Time from interrupt event to execution of

instruction at address 0004h
Synchronous interrupts (typically internal)
z
latency is 3 instruction cycles (Tcy)
Asynchronous interrupts (typically external)

z
latency is 3 3.75 instruction cycles
201ASP
Slide 31
Context Saving
z
During an interrupt:
Only the PC value is saved (on the stack)

Registers changed in the Interrupt Service
Routine (ISR) are permanently changed
Key registers you may want saved:
Working register
Status
PCLATH (Program Counter Latch High)
User defined registers
201ASP
Slide 32
Interrupt Priority
z
Mid-Range PIC microcontrollers treat all

Interrupts with the same priority
The user must do the following:
Determine source of interrupt

Determine the order in which the interrupts
are serviced.
201ASP
Slide 33
Interrupt Priority Example

INT_VECTOR CODE
0x004
;interrupt vector location
;Save context
movwf temp_w
swapf STATUS,w
;save WREG
;movf affects Z bit,
;use swapf instead
;save STATUS register
movwf
temp_status
;Check
btfsc
call
btfsc
call
btfsc
call
flags in order of priority

INTCON,RBIF ;PORTB change?
PORTB_ISR
PIR1,TMR2IF ;Timer2 interrupt?
Timer2_ISR
PIR2,TMR1IF ;Timer1 interrupt?
Timer1_ISR
Restore_context:
swapf temp_status,w
movwf STATUS
;restore STATUS reg
movf
temp_w,w
;restore WREG
retfie
;return from interrupt
201ASP
Slide 34
Interrupt
Hands on Lab
201ASP
v8.0
January
Slide
2007
35
Interrupt
z
The objective of this is to:
Learn how to set up and enable an

interrupt on the Mid-Range PIC
Become more familiar with the MPLAB IDE,

the PICdem2 Plus and the ICD2
z
z
Building a Project
Using the ICD to set a break point
201ASP
Slide 36
Interrupt Lab Overview

Interrupt Vector
Main Program
Call
debounce
delay function
Clear Variables
Initialize PORTB
(RB0) for S3 input
Increment
Count variable
Enable Interrupts
Clear IF
No Operation
NOP
Return to Main
201ASP
Slide 37
Lab Specifics
z
Code is located in C:\RTC\201_ASP\Lab1-INT
The S3 switch is connected to the RBO/INT

pin on PORTB
The push_count register will display the #

of times S3 has been pushed.
Use MPLAB and the ICD to set a breakpoint

in the code to view the changing value of the
register named push_count
201ASP
Slide 38
What you need to know

z
The function of the INTCON register bits
Jumper J6 must be removed in order for

the INTE pin to work
A subroutine called debounce is given
masks the mechanical bouncing of S3
How to setup break points and a Watch

Window in MPLAB
201ASP
Slide 39
Interrupt Lab Solution
bsf
bsf
bsf
bsf
bcf
STATUS,RP0
TRISB,0
INTCON,INTE
INTCON,GIE
STATUS,RP0
;
;
;
;
;
point to BANK1
### initialize PORTB<0> as input
### enable INTE interrupts
### Enable global interrupts
return to BANK0
201ASP
Slide 40
Peripherals
201ASP
v8.0
January
Slide
2007
41
Mid-Range Family Peripherals

z
z
z
z
z
z
z
I/O Ports
Timers (0, 1, 2)
Capture/Compare/PWM
Comparators
Analog-to-Digital
Converter
AUSART
I2C and SPI Serial
Interface
201ASP
Slide 42
I/O Overview
z
Up to 35 bi-directional Input/Output pins
some multiplexed with peripheral functions
High drive capability
25mA source or sink
Direct, single cycle bit manipulation
Most I/Os have ESD protection
After Reset:
Analog capable pins come up as Analog

Digital I/O pins come up as Input
201ASP
Slide 43
PORTx and TRISx Registers

z
Every PORT (A, B, C, D, E) will have a

corresponding direction register TRISx
PORTB Register
RB7
RB7
RB6
RB6
RB5
RB5
RB4
RB4
RB3
RB3
RB2
RB2
RB1
RB1
RB0
RB0
Data
Configures Data Direction
PORTB Tri-State Register (TRISB)
TRISB7
TRISB6TRISB5
TRISB5TRISB4
TRISB4TRISB3
TRISB3TRISB2
TRISB2TRISB1
TRISB1TRISB0
TRISB0
TRISB7TRISB6
1 = corresponding PORTB pin is an INPUT

0 = corresponding PORTB pin is an OUTPUT
201ASP
Slide 44
Configuring Analog Inputs for Digital

z
I/Os with digital and analog capabilities

default to analog on reset
201ASP
Slide 45

z
Two ways to configure Analog inputs as Digital:

1) Analog Select Registers (ANSEL and ANSELH)
z
For devices with > 8 analog pins
OR
2) ADC Control register 1 (ADCON1)
z
For devices with 8 or less analog pins
Analog Select Register (ANSEL)

ANS7
ANS6 ANS5
ANS5 ANS4
ANS4 ANS3
ANS3 ANS2
ANS2 ANS1
ANS1 ANS0
ANS0
ANS7 ANS6
Analog Select High Register (ANSELH)

ANS13
ANS12 ANS11
ANS11 ANS10
ANS10 ANS9
ANS9 ANS8
ANS8
ANS13 ANS12
1 = Pin assigned as Analog Input

0 = Digital I/O
ADC Control Register 1 (ADCON1)
PCFG3
PCFG2 PCFG1
PCFG1 PCFG0
PCFG0
PCFG3 PCFG2
ADFM
ADCS2
ADFM ADCS2
Port Configuration Bits
201ASP
Slide 46

PCFG AN7
AN6 AN5 AN4 AN3
<3:0>
AN1
VddAN0
PCFG3
PCFG2 PCFG1
PCFG1 PCFG0
PCFG0
PCFG3 PCFG2
ADFM
ADCS2
ADFM ADCS2
AN2
201ASP
Slide 47
Initializing Digital I/O

z
Initialize PORTB
RB4 through RB7 as Digital Inputs

RB0 through RB3 as Digital Outputs
;------------configure PORTB for digital ---------------------banksel

PORTB
;Go to bank containing PORTB register
clrf
PORTB
;Initialize PORTB data
banksel
ANSELH
;Go to bank containing ANSELH register
clrf
ANSELH
;Set as all digital
;-----------Set up direction of each PORTB pin----------------banksel
TRISB
;Go to bank containing TRISB register
movlw
b11110000
;Move value to set TRISB<7:4> high and
;TRISB<3:0> low into W register
movwf
TRISB
;Move value in W into TRISB
201ASP
Slide 48
PORTB Interrupt & Weak Pull-Up Options

z
All PORTB pins have Interrupt-on-Change

and Weak Pull-Up options
Weak Pull-Up PORTB Register (WPUB)
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
1 = Pull-up enabled
0 = Pull-up disabled
Devices without WPUB register

use RBPU bit in OPTION register
Interrupt-On-Change PORTB Register (IOCB)
RB3
IOCB7 IOCB6 IOCB5 IOCB4

1 ICOB3 IOCB2 IOCB1 IOCB0
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
HIGH
LOW
Devices without IOCB rely

on RBIE bit in INTCON
RB4
Interrupt Control Register (INTCON)

GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
RBIF
*PORTB must first be read/written and then RBIF can be cleared in software
201ASP
Slide 49
Timers
201ASP
v8.0
January
Slide
2007
50
Timers
z
Timers are used for many functions:
timing reference to generate an event

count the number of events
waveform generation etc...
PIC16F877 has 3 timers
Timer0
Timer1
Timer2
201ASP
Slide 51
Timer Comparison
TIMER0
TIMER1
TIMER2
SIZE OF
REGISTER
8-bits (TMR0)
16-bits
(TMR1H:TMR1L)
8-bits (TMR2)
CLOCK SOURCE
(Internal)
Fosc/4
Fosc/4
Fosc/4
CLOCK SOURCE
(External )
T0CKI pin
T1CKI pin or
Timer 1 oscillator
(T1OSC)
None
CLOCK SCALING
AVAILABLE
(Resolution)
Prescaler 8-bits
(1:21:256)
Prescaler 3-bits
(1,2,4,8)
Prescaler
(1:1,1:4,1:8)
Postscaler
(1:11:16)
INTERRUPT
EVENT and FLAG
LOCATION
On overflow
FFh00h
(TMR0IF in INTCON)
On overflow
FFFFh0000h
(TMR1IF in PIR1)
TMR2 matches
PR2
(TMR2IF in PIR2)
CAN WAKE PIC

FROM SLEEP?
NO
YES
NO
201ASP
Slide 52
Timer 0 Block Diagram

DATA BUS
Fosc/4
8
synchronize
T0CKI
pin
scaled clock
TMR0
PS2
PS1
PS0
TMR0
RATE
1:2
1:4
1:8
1:16
1:32
1:64
1= prescaler assigned to WDT 1

0= prescaler assigned to Timer 0
1:128
1:256
prescaler
Watchdog Timer
WDT out
OPTION register
RBPU INTEDG TOCS TOSE
PSA
PS2
PS1
PS0
Prescaler Rate Select Bits

Prescaler Assignment
TMR0 Clock
Source Select
1 = TOCK1, 0 = Fosc/4
Source Edge Select
1 = increment TMR0 on high-to-low transition

0 = increment TMR0 on low-to-high transition
201ASP
Slide 53
Timer 0 Block Diagram

DATA BUS
Fosc/4
8
synchronize
T0CKI
pin
scaled clock
Watchdog Timer
prescaler
TMR0
INTCON register
TMR0IF
If the external clock source (TOCKI) is used it will be

synchronized to the internal clock
Timer 0 is readable or writeable
Timer 0 interrupt flag is set on TMR0 roll-over (FF to 00)
201ASP
Slide 54
Timer0 Initialization
;Make sure the Timer0 count
;register (TMR0) is clear
banksel
TMR0
clrf
TMR0
Timer0
incrementing
TMR0
0
0 0
1 0
1 0
1 0
1 0
1 0
1 1
1
INTCON
0
1
;Clear Timer0 interrupt flag

bcf
INTCON,TMR0IF
This interrupt flag will set on

Timer0 overflow even if
interrupts are disabled
OPTION_REG
;The TMR0 interrupt is disabled, do

;polling on the flag bit (TMR0IF)
btfss
INTCON,TMR0IF
goto
$-1
<continue>
TMR0IF
Flag on overflow
;Setup the Option register to

;increment Timer0 from internal
;clock with a prescaler of 1:16
banksel
OPTION_REG
movlw
b00000011
movwf
OPTION_REG
0 0 0 0 0 0 1 1
TOCS
PSA
PS<2:0>
Prescaler
Selects Timer 0
Prescaler
Assignment
Clock Source
value = 1:16
(External or Internal) (WDT or TMR0)
201ASP
Slide 55
Timer1 Block Diagram

T1OSI
T1
OSC
T1OS0
prescaler
synchronize
Fosc/4
T1CKI
pin
TMR1H
TMR1L
Enable
Timer1 Control Register (T1CON)

T1GINV
TMR1ON
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T1CKPS1
T1CKPS0
scale
1:8
1:4
1:2
1:1
LP Oscillator Enable
1 = T1OSC selected
0 = T1CKI can be used
201ASP
Timer1 On
1 = Enable Timer1
Clock Source Select

1 = External (T1CKI)
0 = Internal (FOSC/4)
Slide 56

T1OSI
T1OS0
T1
OSC
prescaler
synchronize
Fosc/4
T1CKI
pin
TMR1H
TMR1L
Enable
TMR1ON

T1GINV
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer1 Gate Enable and

Timer1 Gate Invert are
available on some devices
Timer1 External Clock Input Synchronization

1 = do not synchronize external clock input
0 = synchronize external clock input with
internal clock (Fosc/4)
201ASP
Slide 57
Timer1 Interrupt Setup

TMR1L
TMR1H
Main Code
1 0
0
1 0
1 0
1 0
1 0
1 0
1 0
1
1 0
0
1 0
1 0
1 0
1
Start
;Start by clearing the Timer1 interrupt flag
banksel
PIR1
PIR1
bcf
PIR1, TMR1IF
0
1
0 0
1
1
1
0
;Enable Timer1 interrupt
banksel
PIE1
bsf
PIE1, TMR1IE
TMR1IF
PIE1
1
;Enable Global and Peripheral Interrupts

bsf
INTCON, PEIE
INTCON
bsf
INTCON, GIE
TMR1IE
1 1
GIE PEIE
201ASP
Slide 58
TMR1H
;Make sure the TMR1 registers are clear
banksel
TMR1H
clrf
TMR1H
clrf
TMR1L
;Make sure the TMR1IF flag in PIR1
;is cleared
banksel
PIR1
bcf
PIR1,TMR1IF
TMR1H:TMR1L
0 0OVERFLOW!!
0 0 INCREMENTING
0 0 0 0
0 0 0 0 0 0 0 01
TMR1IF
T1CON (Timer1 Control)
0 0 1 1 0 0 0 1
0
;Start Timer1 incrementing

bsf
T1CON, TMR1ON
TMR1L
PIR1 (Peripheral Interrupt Request)
;Setup T1CON register for internal clock

;with 1:8 prescaler, Timer1 is stopped
;and T1 osc is disabled
movlw
b00110000
movwf
T1CON
;The TMR1 interrupt is disabled, do

;polling on the Timer1 flag bit
btfss
PIR1, TMR1IF
goto
$-1
0 0 0 0 0 0 0 0
Input clock
prescale bits
(T1CKPS<1:0>)
201ASP
Timer1
oscillator
enable bit
(T1OSCEN)
TMR1ON
Clock source
select bit
(TMR1CS)
Slide 59
Timer1 Lab
201ASP
v8.0
January
Slide
2007
60
Timer1 Lab
z
Objective of this lab is to become familiar with

the operation of Timer1
AND
To gain experience enabling Peripheral

Interrupts
201ASP
Slide 61
Lab Overview
Interrupt Vector
Main Program
Save Context
Initialize PORTB
Clear IF
Initialize Timer1 clock

source and pre-scaler:
Timer1 interrupts
every 100,000 Instruction cycles
Reload Timer1
Toggle LED 0
5th
Int. ?
Enable Timer1, Global

and Peripheral Interrupts
NO
YES
Toggle LED 3
NOP
Main Loop
Restore Context
Retfie
201ASP
Slide 62
Lab Specifics
z
The code for the lab is in

C:\RTC\201_ASP\Lab2-TMR1
Within lab2.asm complete the following
Set Timer1 clock source to Fosc/4

Set Timer1 pre-scaler to 2
Load Timer1 with 0x3CB0 (65,536 50,000)
Start Timer1
Enable Timer1, Global and Peripheral Interrupts
201ASP
Slide 63

z
Register Operations of INTCON, T1CON,

TMR1H, TMR1L and PIE1
With a value of 0x3CB0 and a pre-scaler of 2,

Timer1 will overflow every 100,000 cycles
The interrupt vector code to toggle the LEDs

has been provided
201ASP
Slide 64
Timer1 LAB Solution

;*******************************************************************
;Set code to Select clock source, Set pre-scaler to 2, load hex 3CB0
;into Timer1 and turn on Timer1
;*******************************************************************
movlw 0x3C
; ### initialize TMR1L and TMR1H
movwf TMR1H
; ###
movlw 0xB0
; ###
movwf TMR1L
; ###
bsf
T1CON,T1CKPS0 ; ### configure prescaler to 1:2
bsf
T1CON,T1CKPS1 ; ###
bcf
T1CON,TMR1CS
; ### set clock source to Fosc/4
bsf
T1CON,TMR1ON
; ### turn TMR1 on
;
;*******************************************************************
;Enable Timer1 interrupts, Peripheral Interrupts and Global
Interrupts
;*******************************************************************
bsf
STATUS,RP0
; ### point to BANK1
bsf
PIE1,TMR1IE
; ### enable TMR1 interrupts
bsf
INTCON,GIE
; ### enable Peripheral interrupts
bsf
INTCON,PEIE
; ### enable Global interrupts
bcf
STATUS,RP0
; ### return to bank0
201ASP
Slide 65
Lab Questions
Question:
Was Timer 1 still running during the time it
took to service the Interrupt?
Answer:
Yes
Question:
What effect did this have on the value to be
placed to reload TMR1L and TMR1H?
Answer:
Everything to be precise the latency of
reloading Timer1 should be considered.
201ASP
Slide 66
Fosc/4
TMR2
OUTPUT
TMR2
Prescaler
1:1, 1:4, 1:16
COMPARATOR
Postscaler
1:1 1:16
PR2

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
T2CKPS1
T2CKPS2
Scale
1:1
1:4
1:16
Timer2 ON
1 = Timer2 enabled
201ASP
Slide 67
TOUTPS3

TOUTPS2
TOUTPS1
TOUTPS0
SCALE
1:1
1:2
1:3
1:4
1
Prescaler
0
1:1, 1:4,1 1:16
1:6
1:7
1:8
1:9
1:14
1:15
1:16
Fosc/4
TMR2
OUTPUT
TMR21:5
1:10
COMPARATOR
1:11
Postscaler
1:1 1:16
1:12
PR2 1:13

T2CKPS1
T2CKPS2
Scale
1:1
1:4
1:16
Timer2 ON
1 = Timer2 enabled
201ASP
Slide 68

Start Timer2
Counting
Fosc/4
Prescaler
1:1, 1:4, 1:16
TMR2
1 1 1 1 0
1 1
0 0
1 1
0
Postscaler
1:1 1:16
COMPARATOR
Load Period
Register
PR2
1 1 1 1 1 0 0 0
TMR2
OUTPUT
PIR1
1
TMR2IF

Flag set on first

match with
postscaler = 1:1
201ASP
Slide 69
Timer2
Incrementing
TMR2 (Timer2 Counter)

;Disable the Timer2 interrupts in the PIE1
;register. Make sure the Timer2 interrupt
;flag in PIR1 is cleared.
PR2 (Period Register Timer2)
banksel
PIE1
bcf
PIE1,TMR2IE
banksel
PIR1
bcf
PIR1,TMR2IF
PIE1 (Peripheral Interrupt Enable)
;Setup T2CON register for Postscaler = 1:15,
;Prescaler = 1:16, Timer2 off
movlw
b01110010
TMR2IE
movwf
T2CON
PIR1 (Peripheral Interrupt Request)
;Make sure the TMR2 register is clear
banksel
TMR2
clrf
TMR2
TMR2IF
;Load the Period register
Flag is set
banksel
PR2
movlw
b10000000
movwf
PR2
banksel
T2CON
bsf
T2CON,TMR2ON
;The Timer2 interrupt is disabled, do
TMR2ON
Postscaler = 1:15
;polling on the Timer2 interrupt flag
(TOUTPS<3:0>)
btfss
PIR1,TMR2IF
Prescaler = 1:16
goto
$-1
1 0
1
0
1 0
1 0
1 0
1 0
1 0
1 0
1 0 0 0 0 0 0 0
0
0
1
0 1 1 1 0 0
1 1 0
(T2CKPS<1:0>)
201ASP
Slide 70
Timer2 Lab
201ASP
v8.0
January
Slide
2007
71
Timer2 Lab
z
The Goal of Lab 3 is to become familiar with

the following:
Timer2 Clock Source

Setting the Prescaler
Setting the Postscaler
Turning on Timer2
Setting the Interrupt Enable bits needed for
Timer2 to successfully generate an interrupt.
201ASP
Slide 72
Lab Overview
Interrupt Vector
Main Program
Save Context
Initialize PORT B
Increment counter the

number of times
Timer2 has interrupted
Set up Timer2
Period,
Prescaler,
Postscaler
Output 3 LSBs of count

to LEDs
Enable interrupts
NOP
Restore context
retfie
201ASP
Slide 73
Lab Specifics
z
Code for this lab is in

C:\RTC\201_ASP\Lab3-TMR2
Complete the following sections of code
Set Timer2 prescaler to a value of 4

Set Timer2 postscaler to a value of 13
Turn Timer2 on
Configure the GIE and PEIE bits in the Interrupt
Control register (INTCON)
Configure the Timer2 Interrupt Enable bit in the
Timer2 Configuration register (T2CON)
201ASP
Slide 74

z
Special Function Registers (SFRs) needed

for this lab are:
INTCON(Interrupt Control)
PIE1..(Peripheral Interrupt Enable 1)
PR2...(Timer2 Period Register)
T2CON..(Timer2 Control)
With the Period register (PR2) set to 250,

the prescaler at 4, and the postscaler at
13, Timer2 will interrupt every 13 ms
(about 1/80 second) with a 4Mhz oscillator
(Fosc/4 = 1Mhz).
201ASP
Slide 75
Timer2 Lab Solution

;*****************************************************************
; configure Timer2 prescaler of 4, PR2 of 250 and a postscaler
; of 13 and turn timer2 on.
;*****************************************************************
;
BANKSEL
T2CON
; point to bank containing T2CON
movlw
0x60
; ### set TMR2 postscaler = 1:13
movwf
T2CON
; ###
bsf
T2CON,T2CKPS0 ; ### set TMR2 prescaler = 1:4
bsf
T2CON,TMR2ON
; ### turn on TMR2
;*****************************************************************
;Enable Timer2 interrupts, Peripheral and Global Interrupts
;*****************************************************************
bsf
bsf
bsf
bsf
bcf
STATUS,RP0
PIE1,TMR2IE
INTCON,PEIE
INTCON,GIE
STATUS,RP0
;
;
;
;
;
point to BANK1
### enable TMR2 interrupts
### enable peripheral interrupts
### enable global interrupts
return to BANK0
201ASP
Slide 76
Lab Questions
Question:
Like Timer1, does Timer2 keep running
during Interrupt latency?
Answer:
Yes it does!
Question:
Does the user have to account for the free
running Timer2 in order to ensure a precise
interrupt period?
Answer:
No, Interrupt occurs on match not overflow
201ASP
Slide 77
Capture/Compare/PWM
Module
201ASP
v8.0
January
Slide
2007
78
Capture/Compare/PWM
(CCP) Overview
Capture
Compare
Times the duration of an external event using an

input pin
Changes an output pin or generates an interrupt
when a specific amount of time has passed
Pulse Width Modulation (PWM)
Creates a reconfigurable, steady duty-cycle, square

wave output at a defined frequency
Provides enhanced features for various bridge
connectivity
* Module interfaces with Timers 1 and 2

201ASP
Slide 79
Capture/Compare/PWM
(CCP) Overview
Capture
Compare
Capture
Times the duration of an external event using an

Timer Resource
inputCCP
pin MODE
Timer 1
Changes an output pin or generates an interrupt

Compare
Timer 1
when a specific amount of time has passed
PWM
Pulse Width
Modulation (PWM) Timer 2
Creates a reconfigurable, steady duty-cycle, square

wave output at a defined frequency
Provides enhanced features for various bridge
connectivity
* Module interfaces with Timers 1 and 2

201ASP
Slide 80
CCP Control Registers

CCP1 Control Register (CCP1CON)
P1M1
P1M0 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
BIT
FUNCTION
CCP1M<3:0>
CCP Mode Select Bits configure the module as Input Capture,

Output Compare, or PWM
CCP1<X:Y>
PWM duty cycle 2 LSBs (8 MSBs located in CCPR1L)
P1M<1:0>
These PWM output configuration bits are available for Enhanced

CCP (ECCP) modules only. They provide half-bridge or full-bridge
output steering control.
201ASP
Slide 81
CCP Control Register

CCP1 Control Register (CCP1CON)
P1M1
P1M0 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPxM
CCPxM2
BIT
3
0
0
CCP1M<3:0>
0
0CCP1<X:Y>
0
0
0
0
0
1
P1M<1:0>
CCPxM1
CCPxM0
CCP Mode Selected

FUNCTION
CCP Mode
Select0 Bits configure
the module asoffInput
0
Capture/Compare/PWM
(resetsCapture,
CCP module)
Output
0 Compare,1 or PWM
Unused (reserved)
Compare
mode,in
toggle
output on match
PWM1duty cycle 20 LSBs (8 MSBs
located
CCPR1L)
1
Unused (reserved)
Capture mode, every 4th rising edge
These PWM output configuration bits are available for Enhanced

0
0
Capture mode, every falling edge
CCP (ECCP) modules only. They provide half-bridge or full-bridge
0
1
Capture mode, every rising edge
output
steering control.
Capture mode, every 16th rising edge
Compare mode, set output on match
Compare mode, clear output on match
Compare mode, generate software interrupt on match
Compare mode, trigger special event
PWM mode
201ASP
Slide 82
Capture Mode
Prescaler
1, 4, 16
CCPx
CCPxIF in PIRx
TMR1H
Edge Detect
and
TMR1L
Single Buffered
System Clock (Fosc)
CCPRxH CCPRxL
P1M1
P1M0
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPxCON
201ASP
Slide 83
Capture Mode
Prescaler
1, 4, 16
CCPx
CCPxIF in PIRx
TMR1H
CCPxM3
CCPxM2
CCPxM1
CCPxM0
TMR1L
MODE
Edge Detect
0 and
0
Capture every falling

edgeBuffered
Single
Capture every rising edge
0
1
1
System Clock (Fosc)
0
1
1
Capture every 4th rising edge
Capture every 16th rising edge
P1M1
P1M0
CCPRxH CCPRxL
CCPxCON
201ASP
Slide 84
Capture Initialization
TMR1H
;Turn off CCP module
CCP1
0
0
0 0
0 0
0
0
banksel
CCP1CON
Pin
clrf
CCP1CON
TMR1L
0
1
;Make sure Timer1 is off
0 Current
0 0 INCREMENTING!!
0
0 0Value
0
0
TIMER1
Timer1
rd
bcf
T1CON,TMR1ON
nd
st
4
3
21th
;Clear Timer1 registers Rising Edge CCPR1H
clrf
TMR1H
Detected!!
clrf
TMR1L
;Disable all interrupts for CCP
CCPR1L
bcf
PIR1,CCP1IF
Captured!
banksel
PIE1
bcf
PIE1,CCP1IE
PIR1
;Set CCP1 pin for input
0
1
bsf
TRISC,2
CCP1IF
;Set Capture for every 4th rising edge
CCP1CON
banksel
CCP1CON
movlw
b00000110
0
0 0
0 0 10 0
1 0
movwf
CCP1CON
T1CON
bsf
T1CON,TMR1ON
;Test the interrupt flag for capture
1
0
btfss
PIR1,CCP1IF
TMR1ON
goto
$-1
201ASP
Slide 85
Compare Mode
TMR1H
TMR1L
COMPARATOR
COMPARATOR
Does
DoesTMR1H:TMR1L
TMR1H:TMR1L
==CCPRxH:CCPRxL
CCPRxH:CCPRxL
??
??
CCPRxH
CCPxIF in PIRx
NO
YES
OUTPUT
OUTPUT
LOGIC
LOGIC
CCPx
CCPRxL
Special Event Trigger
CCP1CON
P1M1
P1M0
201ASP
Slide 86
Compare Mode
TMR1H
TMR1L
COMPARATOR
CCPxM3 COMPARATOR
CCPxM2 CCPxM1
Does
DoesTMR1H:TMR1L
TMR1H:TMR1L
==CCPRxH:CCPRxL
0
0
CCPRxH:CCPRxL
1
1
??
??
CCPRxH
P1M1
P1M0
CCPxIF in PIRx
NO
CCPxM0
MODE
Set output onOUTPUT

match (CCPxIF is set)
OUTPUT
YES
LOGIC
LOGIC
CCPx
Clear output on match (CCPxIF is set)
Generate software interrupt on match

(CCPxIF is set CCP1 pin unaffected)
Trigger special event

(CCPxIF is set, CCP1 resets TMR1 or
TMR2 and starts an A/D conversion if
enabled)
Special Event Trigger
CCPRxL
201ASP
Slide 87
Compare Initialization
TMR1H
;Turn off the CCP module

banksel
CCP1CON
clrf
CCP1CON
;Turn off Timer1
bcf
T1CON,TMR1ON
;Clear Timer1 result registers
clrf
TMR1H
clrf
TMR1L
;Disable CCP1 interrupt and make sure
;its flag is clear
banksel
PIE1
bcf
PIE1,CCP1IE
banksel
PIR1
bcf
PIR1,CCP1IF
;Make CCP1 pin output
banksel
TRISC
bcf
TRISC,2
;Initialize Compare to set output on match
banksel
CCP1CON
movlw
b00001000
movwf
CCP1CON
;Load Compare value into CCPR1H:CCPR1L
banksel
CCPR1H
movlw
b10000000
movwf
CCPR1H
clrf
CCPR1L
bsf
T1CON,TMR1ON
;Test CCP1IF for Timer1 match with CCPR1x
btfss
PIR1,CCP1IF
goto
$-1
201ASP
TMR1L
TMR1H:TMR1L = 1000 0000 0000 0000
0
0 0 INCREMENTING!!
0
0 0
0
0
TIMER1
(CCPR1H:CCPR1L Value)
CCPR1H
CCPR1L
T1CON
0
1
TMR1ON
CCP1CON
10
PIR1
1
0
CCP1IF
Slide 88
PWM Mode
z
Generates a Pulse-Width Modulated

(PWM) signal on the CCP1 and CCP2 pins
Duty cycle, period and resolution

determined by the following registers
Register
Description
PR2
Period Register
T2CON
Timer2 Control
CCPRxL
CCPxCON
2 Duty Cycle Registers

2 CCP Control Registers
201ASP
Slide 89
PWM Block Diagram

Period 1
Period 2
CCP1<X:Y>
DUTY CYCLE VALUE
CCPR1L
DOUBLE
BUFFER
10
CCPR1H
LATCH
10
Period
Start
TMR2
= CCPR1H
COMPARATOR
10
TMR2incrementing
TMR2
Reset to 0s
CCP1 Output Pin
R
Latch
(1)
0
1
CCP1
pin
COMPARATOR
TMR2 = PR2
8
PR2
Note (1): TMR2 is concatenated with the

2-bit FOSC, or 2-bits from Prescaler
to create 10-bit time base
201ASP
Slide 90
PWM Initialization
TMR2
;Turn off CCP1 pin by setting TRISC bit HIGH
banksel
TRISC
bsf
TRISC, 2
;configure pin as input
0 0 0 0
PR2
0 1 1 1 1 1 1 1
;Clear Timer2
banksel
TMR2
clrf
TMR2
;Set up Period and Duty
movlw
b01111111
movwf
PR2
movlw
b00011111
movwf
CCPR1L
0 0 0 0
CCPR1L
Cycle
;
;Load a Period Value
;
;Load Duty Cycle Value
;Configure CCP module for PWM

;and LSBs of Duty Cycle = b10
movlw
b00101100
movwf
CCP1CON
CCP1CON
0 0 1 0 1 1 0 0
T2CON
duty cycle
LSBs
CCP1<X:Y>
0 0 0
;Turn CCP1 pin back on (make it an output)

banksel
TRISC
bcf
TRISC,2
PWM Mode
CCP1M <3:0>
0 0 1 0 0
Prescaler bits
TOUTPS<3:0>
;Start the PWM by turning on Timer2

;Configure Prescaler and Postscaler to 1:1)
movlw
b00000100
movwf
T2CON
0 0 0 1 1 1 1 1
Prescaler bits
T2CKPS<1:0>
TMR2ON
201ASP
Slide 91
Pulse Width Modulation

(PWM) Lab
201ASP
v8.0
January
Slide
2007
92
PWM Lab Objectives

z
Become familiar with the CCP module

configuration and operation in PWM mode
Gain additional exposure to Timer2

configuration
201ASP
Slide 93
PWM Lab Overview

z
The PWM waveform is output on the

CCP1 pin (RC2) that will emit a tone on
the PICdem2 plus onboard buzzer.
When the lab is completed, a 50% duty

cycle at a period of 256/(Fosc/4) will
drive the buzzer.
201ASP
Slide 94
PWM Lab Overview

Main Code
Load PR2 value
Set up RC2 as output pin
Load CCPR1L for 50% duty cycle
Configure CCP as 8-bit PWM

Turn on Timer2 w/ 1:1 pre scaler
NOP
201ASP
Slide 95
PWM Lab Specifics

z
Code for the lab is in

C:\RTC\201_ASP\Lab4-PWM
Complete the following sections
Configure PORTC pin 2 ( CCP1) as an output

Set CCP in PWM mode
Clear CCP1X and CCP1Y (8-bit PWM)
Configure Timer2 with 1:1 pre-scaler
201ASP
Slide 96

z
The code to load PR2 (Timer2) and to set a

50% duty cycle has been provided. These
values can be seen in the code
The CCP1 pin is RC2 (Pin 2 of PORTC) on

the PIC16F877
Registers needed to complete this lab are:
TRISC
T2CON
CCP1CON
201ASP
Slide 97
PWM Lab Solution

;*****************************************************************
;
Set CCP1 as an output
;*****************************************************************
bcf
TRISC,2
; ### config CCP1 pin PORTC<2> as output
bcf
movlw
movwf
STATUS,RP0
0x80
CCPR1L
; point to BANK0
; establish duty cycle @ 50%
;*****************************************************************
;
Put CCP1 module in PWM mode.
;*****************************************************************
movlw
movwf
0x0C
CCP1CON
; ### configure CCP for PWM

; ###
;*****************************************************************
; Configure Timer2 pre and post scale of 1:1 and turn Timer2 on
;*****************************************************************
bsf
T2CON,TMR2ON
; ### turn on TMR2
201ASP
Slide 98
PWM Lab Questions

Question:
Why didnt we have to enable the interrupts
for the PWM to work?
Answer:
PWM will run concurrently with the PICmicro
MCU without slowing the processor down
201ASP
Slide 99
Output Compare
Lab
201ASP
v8.0
January
Slide
2007
100
Output Compare Lab

z
Goals of the lab are to gain experience with

the following:
Setting up the CCP for Output Compare

Configure the Special Event Flag to reset Timer1
Configure the CCP to generate an Interrupt on
Timer1 overflow
Using an Interrupt Vector to modify the interval
between Interrupts
201ASP
Slide 101
Compare Lab Overview

z
This lab configures the CCP into output compare

mode driven by Timer1
An Interrupt is used to change the sound of the

buzzer
During the Interrupt Service Routine (ISR):
The RC2/CCP1 pin (connected to buzzer) is toggled
The ISR period is reduced:

z
z
The Compare Register (CCPR1L) is decremented

The Timer1 count registers are reset
The combination of a reduced period and the

CCPR1L roll-over will cause the buzzer to emit a
chirping sound
201ASP
Slide 102
Compare Lab Overview

Interrupt Vector
Main Program
Save Context
Configure CCP as
Output Compare
Clear IF
Initialize Timer1
Toggle CCP
Output Pin
Drives
Buzzer
Initialize PORT C
Decrement
CCPR1L
Turn on timer1
Reset
Timer1
NOP
RETFIE
201ASP
Slide 103
Compare Lab Specifics

z
The code for this lab is in

C:\RTC\201_ASP\Lab5-CCP
Complete the following sections:
Configure the CCP as an Output Compare

that sets the Special Event Flag and CCP1IF
Configure Timer1 with a clock source of
Fosc/4 and a pre-scaler of 1:8
Configure Special Function Registers to
allow the CCP interrupt to occur
201ASP
Slide 104

z
The registers needed to complete this lab are:
INTCON (Interrupt Control)

CCP1CON (CCP1 Control)
PIE1 (Peripheral Interrupt Enable)
The Interrupt Vector has been provided
The Value of CCPR1L will rollover from 0 to

0xFF and continue to decrement
201ASP
Slide 105
Compare Lab Solution

;
; Set CCP1CON to Output Compare mode with Special Event Trigger
; to clear the Timer 1 register pair on a match
;****************************************************************
movlw 0x0B
; ### value for CCP1CON
movwf CCP1CON
; move to CCP1CON
;
; Configure Timer 1 for Fosc/4 operation. 8:1 Prescaler
;
;****************************************************************
movlw 0x30
; ### value for TMR1
movwf T1CON
; ### move to TMR1 control register
;
; Enable Timer 1 interrupts, Peripheral Interrupts and
; Global Interrupts
;****************************************************************
bsf
PIE1,CCP1IE
; ### enable CCP1 interrupt
bsf
INTCON,PEIE
; ### enable peripheral interrupts
bsf
INTCON,GIE
; ### enable global interrupts
201ASP
Slide 106
Lab Question
Question:
The PWM did not require an interrupt in order
to work. Do we need an interrupt to operate in
output compare mode?
Answer:
Not necessarily
Peripherals always set their associated interrupt

flag, so you have the choice of polling or
directly responding to the interrupt.
The choice is based on the need of your
application.
201ASP
Slide 107
Comparators
201ASP
v8.0
January
Slide
2007
108
Comparator Overview
z
Comparator Module:
Compares analog input voltage to a reference

and outputs a digital result
Vref
Analog Input
(Vin)
Reference Voltage
(Vref)
Vin
+
Output
(Vout)
Comp
Vout
201ASP
Slide 109
Comparator Reference Voltage

z
Voltage Reference can be either:
External from a device pin

Internally generated with the Voltage Reference
Module
z
Provides 16 selectable voltages from 0 to 75% of VDD
Some devices also have a fixed reference (0.6V)
VREF+
VRSS = 1
Some devices can also scale VREF+ and VREFIndependent of VDD

8R
VRR
VRSS = 0
V
CVREFDD
To Comparators
and ADC Module
8R
15
VREF0
VRSS = 1
4 VR<3:0>
CVREF
VROE
VRSS = 0
VREN
201ASP
Slide 110
Comparator Interrupts
z
An Interrupt occurs when the comparator

output changes
Some devices share one flag for both

comparators
Some devices have independent flags
Must read the comparator output before

clearing interrupt flags
Outputs found in the comparator control

register (CMCON or CMxCON0)
Resets the output mismatch condition
201ASP
Slide 111
Comparators and Sleep Mode

z
Comparators remain active in Sleep
A Comparator output change will wake-up

core
After wake-up, the instruction following

the SLEEP instruction or an Interrupt
Service Routine (ISR) is executed
201ASP
Slide 112
Analog-to-Digital
Converter (ADC)
201ASP
v8.0
January
Slide
2007
113
ADC Overview
z
Analog-to-Digital Converter Module
Converts analog input signal into an 8 or 10-bit

binary value
Selectable internal or external reference voltage
Interrupt can be generated after conversion is
completed
z
The interrupt can wake the PICmicro from SLEEP
ADC
Analog
Input
Digital
Output
201ASP
Slide 114
ADC Control Registers

z
The ADC implements two control registers

ADCON0 and ADCON1
Devices with > 8 analog inputs do not have same bits
shown below

ADCS1
ADCS0
CHS2
BIT
CHS1
CHS0 GO/DONE
ADON
FUNCTION
ADCS<1:0> A/D Conversion Clock Select bits

Use with ADCS2 in ADCON1
CHSx bits
GO/DONE
ADON
Analog Channel Select bits

1 = A/D Conversion in progress
0 = A/D Conversion is completed
Enables the ADC module
201ASP
Slide 115
ADC Control Registers

z
The ADC implements two control registers

ADCON0 and ADCON1
Devices with > 8 analog inputs do not have same bits
shown below

ADFM
ADCS2
PCFG3
BIT
PCFG2
PCFG1
FUNCTION
ADFM
ADC Result Registers Format bit

1 = Right Justified,
0 = Left Justified
ADCS2
A/D Conversion Clock Select bit

Use with ADCS<1:0> in ADCON0
PCFG<3:0>
PCFG0

Configures I/O as analog or digital
201ASP
Slide 116
ADC Result Registers

z
10 bit ADC result in is placed in two registers
ADRESH and ADRESL

Left or Right Justified
z
Determined by Format Select bit (ADFM) in ADCON1 register
ADRESH
ADRESL
LSB
MSB
Left Justified (ADFM = 0)

ADRESH
ADRESL
LSB
MSB
Right Justified (ADFM = 1)

201ASP
Slide 117
ADC Module Diagram

Fosc
Conversion
clock scaler
VREF+
pin
AN0
AN1
AN2
AN3
ADC
AN4
AN5
AN6
AN7
Holding
Capacitor
Start Conversion
Conversion Complete
00000011 11111111
ADRESH
ADRESL
Left Justified Right Justified
VREFpin
ADCON0
ADCS1 ADCS0 CHS2
CHS1
CHS0
GO/DONE
ADON
Vss
ADCON1
ADFM ADCS2
PCFG3 PCFG2 PCFG1 PCFG0

201ASP
Slide 118
ADC Module Diagram

PCFG AN7
AN6 AN5 AN4 AN3
<3:0>
Conversion
clock scaler
Fosc
Port Config Bits
AN2
AN1
VddAN0
VREF+
pin
AN0
AN1
AN2
AN3
ADC
AN4
AN5
AN6
AN7
Holding
Capacitor
Start Conversion
Conversion Complete
00000011 11111111
ADRESH
ADRESL
Left Justified Right Justified
VREFpin
ADCON0
ADCS1 ADCS0 CHS2
0
0
CHS1
CHS0
0
GO/DONE
0
1
ADON
Vss
ADCON1
0
ADFM
ADCS2
1
PCFG3 PCFG2 PCFG1 PCFG0

201ASP
Slide 119
Timing Considerations for ADC

z
When an A-to-D channel is selected

time must be taken for the holding
capacitor to charge
All 10 bit conversions take 11 cycles to

complete
User must select the appropriate ADC

clocking based on the system clock
frequency
201ASP
Slide 120
Analog-to-Digital
Conversion LAB
201ASP
v8.0
January
Slide
2007
121
ADC Lab
z
This Lab will familiarize you with:
Setting up the ADC module
Operating a peripheral from the Main

program, not an interrupt vector
Using the value read from one peripheral

(ADC) to drive another peripheral (CCP in
PWM mode)
201ASP
Slide 122
ADC Lab Overview

Main Program
Configure Timer 2
Configure PORT C
Configure CCP for
PWM
Configure and
Turn on ADC
Enable interrupts
Continued on
next page
201ASP
Slide 123
ADC Lab Overview (cont.)

Continued from
Previous Page
Main Loop
TMR2IF=1
NO
YES
Start ADC
NO
ADC done?
YES
Put ADC value in
CCPR1L
Output 4 LSBs of
ADC value to LEDs
201ASP
Slide 124
ADC Lab Specifics

z

in the project C:\RTC\201_ASP\Lab6-ADC
Configure the ADC to return a left justified

value
Set ADC Conversion Clock to FOSC/32
Turn on ADC unit
Complete the code to start an ADC and wait

for the conversion to finish in the main
control loop
201ASP
Slide 125

z
This lab does not do the ADC conversion in

an interrupt routine. We will use a polling
method.
Writing the value of the ADC conversion into

CCPR1L will change the duty cycle of the
buzzer
ADCON1 and ADCON0 special function

registers are used to complete this lab
201ASP
Slide 126
ADC Solution
;*************************************************************************
; Configure ADC: Channel 0, left justified, Tad = 8 * Tosc, turn on ADC
;*************************************************************************
clrf
ADCON0
; ### ensure default channel is set to channel 0
bsf
ADCON0,ADCS1
; ### set Tad = Fosc/4
bsf
ADCON0,ADON
; ### turn on ADC
bsf
STATUS,RP0
; ### point to BANK1
movlw
0x0E
; ### left justify, configure AN0 analog
movwf
ADCON1
;
; Enable Timer 2 interrupts, Peripheral Interrupts and Global Interrupts
;
bsf
PIE1,TMR2IE
bsf
INTCON,GIE
bsf
INTCON,PEIE
bcf
STATUS,RP0
; return to BANK0
;
;*************************************************************************
; add three lines of code to start the ADC conversion and wait for the
; conversion to complete
;*************************************************************************
bsf
ADCON0,GO
; ### start ADC conversion
btfsc
ADCON0,GO
; ### Is the conversion done?
goto
$-1
; ### no: loop until done
201ASP
Slide 127
ADC Lab Question

Question:
Instead of waiting for TMR2IF to be set in
the main program, could we start the ADC
from within an interrupt routine?
Answer:
YES
201ASP
Slide 128
ADDRESSABLE Universal
Synchronous Asynchronous
Receiver Transmitter
(AUSART)
201ASP
v8.0
January
Slide
2007
129
AUSART Overview
z
Serial I/O communications peripheral
Sometimes called Serial Communications

Interface (SCI)
Main Functions:
Can be synchronous or asynchronous

Can receive and transmit
z
z
Most common use
RS-232 communications to a PC serial port

z
Full-duplex asynchronous transmit and receive

Half-duplex synchronous master and slave
Needs driver for RS-232 level shifter
Enhanced (EUSART) features allow interface

with a Local Interconnect Network (LIN) bus
system
201ASP
Slide 130
AUSART Registers
z
Baud rate generator registers
Transmit status and control
RCSTA
Transmit data register
TXSTA
Receive status and control
SPBRG (8 bit for AUSART)

SPBRG and SPBRGH (16 bit for EUSART)
TXREG
Receive data register
RCREG
201ASP
Slide 131
TXSTA Register
CSRC
TX9
TXEN
SYNC
SENB
Bit
CSRC
TX9
BRGH
TRMT
TX9D
Function
Clock Source Select
1 = Master Mode (clock generated internally from BRG)
0 = Slave Mode (clock from external source)
Ninth bit transmission enable
TXEN
Transmit Enable bit, 1 = Tx enabled, 0 = Tx disabled
SYNC
AUSART Mode , 1 = Synchronous Mode, 0 = Asynchronous Mode
SENB
For EUSART only

1 = Send sync break character bit
0 = Sync break transmission is completed
BRGH
Baud Rate Select, 1 = High Speed, 0 = Low Speed
TRMT
Transmit Shift Register (TSR) status

1 = TSR empty, 0 = TSR is full
TX9D
Ninth bit of transmit data
201ASP
Slide 132
RCSTA Register
SPEN
RX9
SREN
CREN
ADDEN
Bit
SPEN
FERR
OERR
RX9D
Function
Serial Port Enable
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
RX9
1 = Enable 9-bit data reception, 0 = 8-bit data
SREN
Synchronous mode (Master), 1 = enable single Rx, 0 = disable single Rx
CREN
Continuous Receive Enable, 1 = enable, 0 = disable
ADDEN
Address Detect Enable bit

1 = enable (enable interrupt and load the Rx buffer when RSR<9> is set)
0 = disable and use 9th bit for parity
FERR
1 = framing error occurred (Stop bit not detected)
OERR
1 = Overrun error occurred (FIFO was still full when other data was
loaded)
RX9D
Ninth bit of received data
201ASP
Slide 133
Transmit Block Diagram

DATA BUS
TXIE
TXREG
Interrupt
TXIF
Set TXIF
TXEN
MSB
LSB
Transmit Shift
Register (TSR)
Baud Rate
Generator
TRMT
TX9D TX9
Ninth data bit
Clear TXIF
Pin Buffer
and Control
TX/DT
pin
SPEN
Enables Serial
Port
Set TRMT bit

Indicates shift register is empty
Clear TMRT bit
TSR has data in it
201ASP
Slide 134
Receive Block Diagram

Enable Serial Port
SPEN
RX/DT
pin
Receive Shift Register (RSR)

Pin Buffer
and Control
Data
Recovery
STOP
START
RX9
Baud Rate
Generator
FIFO
Set RCIF flag

Clear RCIF flag
RCIE
RCREG
RCIF
Interrupt
201ASP
RX9D
Data Bus
Slide 135
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
201ASP
v8.0
January
Slide
2007
136
MSSP Overview
z
The MSSP module can operate in one of two modes:
SPI (Serial Peripheral Interface)

z
3 pins are used
I2C (Inter-Integrated Circuit)

z
z
z
Full Master mode

Slave mode (with general address call)
2 pins are used
Serial Data Out (SDO)

Serial Data In (SDI)
Serial Clock (SCK)
Serial Clock (SCL)

Serial Data (SDA)
The MSSP Control Register (SSPCON) determines

which mode you are in.
We will cover I2C mode only

201ASP
Slide 137
I2C Conditions
z
Conditions :
START (S)
STOP (P)
SDA
SCL
SDA pulled
released
LOW
while SCL is
still HIGH
Recipient
Stop
SDA
condition
goes
doesLOW
quickly
not drive
during
followed
SDA
th clock
pulse of SCL
by a9Start
LOW
condition
ACKNOWLEDGE (A)
RESTART (R)
NEGATIVE or NOT-ACKNOWLEDGE (N)
201ASP
Slide 138
External IC EEPROM Read
+5V
SCL
MASTER
SDA
READ
WRITE
STOP
GOTO
DATA
MODE
ADDRESS
BUSY
PIC
LISTEN
EEPROM
SLAVE
START
RESTART
MEMORY
STOP
ACK
NACK
ADDRESS
ADDRESS
BUSY
LISTEN
SLAVES
201ASP
LISTEN
EEPROM
DATA
ACK
Slide 139
MSSP Control
Registers
2
(I C mode)
1 of 3: MSSP Status Register (SSPSTAT)

SMP
CKE
D/A
CONTROL BITS
BIT
SMP
CKE
D/A
P
S
R/W
UA
BF
R/W
UA
BF
DETECTION BITS (FLAGS)
FUNCTION
Slew Rate Control bit
Not used in I2C mode
Last byte Rx/Tx was data or address
Stop Condition Detected
Start Condition Detected
Slave :READ/WRITE or Master = transmit in progress
Address needs to be updated
The SSPBUF register is full
201ASP
Slide 140
MSSP Control
Registers
2
(I C mode)
1 of 3: MSSP Status Register (SSPSTAT)

SMP
CKE
D/A
CONTROL BITS
BIT
SMP
CKE
D/A
P
S
R/W
UA
BF
R/W
UA
BF
FUNCTION
Slew Rate Control bit
Not used in I2C mode
Last byte Rx/Tx was data or address
Stop Condition Detected
Start Condition Detected
Slave :READ/WRITE or Master = transmit in progress
Address needs to be updated
The SSPBUF register is full
201ASP
Slide 141
MSSP Control
Registers
2
(I C mode)
2 of 3: MSSP Control Register 1 (SSPCON)

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
CONTROL BITS
BIT
FUNCTION
WCOL
Write Collision Detected
SSPOV
A write to the SSPBUF before previous value processed
SSPEN
Enables MSSP module
CKP
Enables clock
SSPM3
Mode Select Bit
SSPM2
Mode Select bits
SSPM1
SSPM0
201ASP
Slide 142
MSSP Control
Registers
2
(I C mode)
SSPM3
SSPM2
SSPM1
SSPM0
Mode
SPI Master mode, clock = FOSC/4
2 of 3:
MSSP
Control
Register
1 (SSPCON)
0
1
0
WCOL1 SSPOV
CKP mode,
SSPM3
SSPM1 SSPM0
1 SSPEN
SPI Master
clockSSPM2
= TMR2 output/2
SPI Slave mode, clock = SCK pin, SS pin control disabled,

FUNCTION
SS can be used as
I/O pin
I2C Slave
mode,Collision
7-bit address
Write
Detected
BIT
1
WCOL
1
SSPOV
0
clock = SCK pin, SS pin control enabled
CONTROL
BITSSPI Slave mode, DETECTION
BITS (FLAGS)
mode, 10-bit address

A 1write to I2C
theSlave
SSPBUF
before previous value processed
0
I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
Reserved
CKP
0
Reserved
0
SSPM3
I2C firmware controlled

MasterBit
mode (Slave idle)
Mode Select
SSPM2
Reserved
Reserved
I2C Slave mode, 7-bit address with Start and Stop bit
interrupts enabled
I2C Slave mode, 10-bit address with Start and Stop bit
interrupts enabled
1
1
SSPEN
SSPM1
1
SSPM0
Enables MSSP module

Enables clock
Mode Select bits

201ASP
Slide 143
MSSP Control
Registers
2
(I C mode)
3 of 3: MSSP Control Register 2 (SSPCON2)

GCEN ACKSTAT ACKDT
ACKEN
CONTROL BITS
RCEN
PEN
RSEN
SEN
BIT
FUNCTION
GCEN
Generates an interrupt when a call is received (slave mode)
ACKSTAT
0 = Acknowledge received from slave (transmit mode)
ACKDT
0 = ACK 1 = NACK (receive mode)
ACKEN
Initiate ACK/NACK condition (Transmits ACKDT bit)
RCEN
Enables receive mode
PEN
Initiates a STOP condition
RSEN
Initiates a RESTART condition
SEN
Initates aa START
Initiates
START condition
condition
201ASP
Slide 144
MSSP Control
Registers
2
(I C mode)
3 of 3: MSSP Control Register 2 (SSPCON2)

GCEN ACKSTAT ACKDT
ACKEN
CONTROL BITS
RCEN
PEN
RSEN
SEN
BIT
FUNCTION
GCEN
Generates an interrupt when a call is received (slave mode)
ACKSTAT
0 = Acknowledge received from slave (transmit mode)
ACKDT
0 = ACK 1 = NACK (receive mode)
ACKEN
Initiate ACK/NACK condition (Transmits ACKDT bit)
RCEN
Enables receive mode
PEN
Initiates a STOP condition
RSEN
Initiates a RESTART condition
SEN
Initates aa START
Initiates
START condition
condition
201ASP
Slide 145
Tx/Rx Buffer (SSPBUF)

Buffer register containing Tx and Rx data
SSPBUF interfaces to a shift register (SSPSR) for

shifting data in or out
When full, the Buffer Full (BF) bit in the

SSPSTAT register is set
Any write to the SSPBUF register during

Tx/Rx of data will be ignored, and the write
collision detect bit (WCOL) of the SSPCON
register will be set
201ASP
Slide 146
I2C Address Register

(SSPADD)
Slave mode:
Contains the slave address of the PIC

Compared against the received value
Master mode:
Used to calculate the clock speed

(BAUD rate) of the I2C system.
Fosc
BAUD RATE =
4 ( SPADD + 1)
*NOTE: FOSC is the frequency of the oscillator
not the Instruction Clock TCY
201ASP
Slide 147
MSSP Interrupts
z
The MSSP interrupt flag (SSPIF) is set in

the PIR1 register with the following events:
START condition
STOP condition
Tx or Rx complete
Acknowledge transmit
RESTART condition
201ASP
Slide 148
I2C Based Temp Sensor

Lab
201ASP
v8.0
January
Slide
2007
149
I2C Based Temp Sensor

Lab Objective
z
Configure some MSSP control registers to

enable I2C communication to the I2C based
Temp sensor on the PICDEM 2 Plus board.
Temperature reading (lowest 4 bits) will be

displayed on the LEDs.
201ASP
Slide 150
I2C Lab Overview

z
This lab configures the MSSP as an I2C

Master
The TC74 Temperature Sensor is then

read by the MSSP module
The temperature reading is then sent to

PORTB to be displayed on the 4 LEDs
201ASP
Slide 151
I2C Lab Overview

Main Code
Configure I/0s
Configure MSSP
Initiate I2C start condition
Send Temp Sensor Address
Loop
Read Temperature
Display Temp LSB

on PORTB LEDs
201ASP
Slide 152
I2C Lab Specifics

z
Code for the lab is in

C:\RTC\201_ASP\Lab7-I2C
Complete the following sections:
Disable the slew rate control

z
Well be using I2C standard rate (100KHz)
Configure the MSSP to operate as an I2C

master and enable the data (SDA) and
clock (SCL) pins
Start the data transfer and check for

when it has completed
201ASP
Slide 153

z
Slew rate control is found in the

SSPSTAT register
Registers needed to complete this

lab are:
SSPSTAT
SSPCON
SSPCON2
201ASP
Slide 154
I2C Lab Solution

;-------------------------------------------------------------; set the slew rate and baud rate for 100 MHZ operation
BANKSEL SSPSTAT
bsf
SSPSTAT,SMP
; ### point to correct BANK for SSPSTAT

; ### Set for standard speed slew rate
;-------------------------------------------------------------; Configure as I2C master with Fosc/4 Clock source

BANKSEL SSPCON
bsf
SSPCON,SSPM3
bsf
SSPCON,SSPEN
; ### set to I2C master mode with

;
Fosc/4 clock source
; ### Enable SDA and SCL pins to
;
operate in I2C mode
;-------------------------------------------------------------BANKSEL
bsf
btfsc
goto
SSPCON2
SSPCON2,SEN
SSPCON2,SEN
$-1
;
;
;
;
Initiate a START condition

### set the SEN bit
### is it finished?
no: test again
201ASP
Slide 155
Multiple Interrupt
Lab
201ASP
v8.0
January
Slide
2007
156
Multiple Interrupts Lab

z
This Lab involves:
Dealing with 2 (or more) concurrent interrupts
Determining the source of an interrupt
Deciding which interrupt request will be

serviced first
201ASP
Slide 157
Lab Overview
Main Program
Set up CCP as Output
Compare just as in Lab 6
Enable Timer1 and
PORTC as In Lab 6
Setup PORTB and enable
External Interrupts on
S3as in Lab 1
NOP
Continued on next slide
201ASP
Slide 158
Lab Overview
Interrupt Service Routines
INT_ISR
CCP_ISR
Call debounce
Delay routine
Clear IF
Put -1 in WREG
Toggle variable
Called
push_flag
push_flag
Set ?
Clear IF
Put 0 in WREG
Return to Main
Add WREG to
CCPR1L
Return to Main
201ASP
Slide 159
Lab Overview (cont.)

Save
context
Interrupt Handler
NO
Did CCP generate

the interrupt?
YES
Did INT generate

the interrupt?
YES
Go to CCP
service routine
NO
Service External
Interrupt
Return to Main
201ASP
Slide 160
Lab Specifics
z
Lab is found in:
The two Interrupt Service Routines (ISRs)

are provided:
C:\RTC\201_ASP\Lab8-MXINT
INT_ISR
CCP_ISR
When an interrupt occurs, determine the cause

and transfer control to the appropriate ISR
Set the Special Function Registers (SFRs) to
enable INT and CCP1 Interrupts to occur
201ASP
Slide 161
What you need to know for Lab

z
INTCON, and PIR Special Function

Registers are used in this lab
201ASP
Slide 162
Lab Solution
Int_Service_Routine
call
save_regs;
btfsc
goto
btfsc
goto
Finish_Int
call
INTCON,INTF
INTE_ISR
PIR1,CCP1IF
CCP_ISR
; save W, STATUS, & PCLATH

; ### test for INTE interrupt request
; ### test for CCP interrupt request
; restore W, STATUS & PCLATH
Restore_Regs
retfie
201ASP
Slide 163
Lab Solution ( cont.)
bsf
PIE1,CCP1IE
;### enable CCP1 interrupt
bsf
bsf
bsf
bcf
INTCON,INTE
INTCON,GIE
INTCON,PEIE
STATUS,RP0
;### enable
;### enable
;### enable
; return to
INTE interrupt
global interrupts
peripheral interrupts
BANK0
201ASP
Slide 164
Lab Questions
Question:
Why is there a noticeable silence when S3 is
pushed?
Answer:
Since debounce is called during an interrupt
and the GIE bit is cleared, the CCP1 interrupt
that toggles the buzzer is not allowed to
operate. Therefore, the buzzer goes quiet.
201ASP
Slide 165
Lab Questions (cont.)

Question:
How can this silence be eliminated and the
buzzer continue to run?
Answer:
1. Capture S3 in Main and call debounce
while GIE is set
2. Use a timer to accomplish the delay
3. Re-enable interrupts during the INT ISR
201ASP
Slide 166
201ASP Wrap-Up
201ASP
v8.0
January
Slide
2007
167
Peripherals Class Wrap-up

z
Today we covered the following

peripherals on the Mid-Range family
I/O ports
Interrupt structure and processing
Timers (timer0, timer1, timer2)
CCP Module ( Output Compare, Input Capture,
PWM)
Comparators and Analog-to-Digital Converters
z
Voltage Reference
AUSART Serial Port

I2C using the MSSP module
201ASP
Slide 168
Final Word
z
This discussion has followed the standard

Microchip datasheet flow:
Overview of Peripheral
Register Description
and Configuration
Enhanced or
Special Features
Use these sections to:

Develop logical flow charts or
pseudo-code (Avoid Spaghetti
Programming!!)
Other Tips:
Comment your code thoroughly
Choose descriptive names
for user defined registers
*Packaging and Electrical Specifications are at the end

of the datasheet
201ASP
Slide 169
Resources
z
Visit www.microchip.com for:

24/7 technical support
Application Notes
Web Seminars
Code examples
Datasheets
and Much More!
201ASP
Slide 170
Thank You!!
201ASP
v8.0
January
Slide
2007
171

Mid Range Family Peripheral Configuration and Assembly Programming

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201ASP

Mid-Range Family Peripheral

2006 Microchip Technology Incorporated. All Rights Reserved.

At the end of this class you will:

Understand the basic PICmicro peripherals

Have HANDS ON experience initializing

Be able to implement peripherals not

Understand interrupts and polling

Write your own application code from

2007 Microchip Technology Incorporated. All Rights Reserved.

To get the most from this Class

Ideally you should be familiar with the

2007 Microchip Technology Incorporated. All Rights Reserved.

Brief review of Mid-Range Architecture,

Interrupts on the Mid-Range PICmicro

2007 Microchip Technology Incorporated. All Rights Reserved.

201ASP Agenda (cont.)

Capture / Compare / PWM Module (CCP)

PWM and Output Compare Labs

Analog to Digital Converters (ADC)

Addressable Universal Asynchronous &

with the Master Synchronous Serial Port

I2C Based Temp Sensor Lab

Wrap-Up and additional questions

2007 Microchip Technology Incorporated. All Rights Reserved.

Mid-Range Family Basic

2006 Microchip Technology Incorporated. All Rights Reserved.

Mid-Range PIC Block Diagram

8-bit value from instruction

Banks of Data Memory

(8K x 14 bits/word)/1 byte

Reset Vector at 0000h

Program Counter (PC) will

Interrupt Vector at 0004h

Program Counter (PC) will

2007 Microchip Technology Incorporated. All Rights Reserved.

Interrupt Vector 0004h

Program Counter (PC) and Stack

PCL ALU result (8-bits) or PCH<12:8>

Updated from PCLATH

8 Level Deep Stack

Stores the contents of the PC

2007 Microchip Technology Incorporated. All Rights Reserved.

Data Memory Map

2007 Microchip Technology Incorporated. All Rights Reserved.

Special Function Registers (SFRs)

Register File Concept

2007 Microchip Technology Incorporated. All Rights Reserved.

Arithmetic status of the

Indirect Register Bank Select bit:

2007 Microchip Technology Incorporated. All Rights Reserved.

PIC16 Instruction Set

35 single word instructions

2007 Microchip Technology Incorporated. All Rights Reserved.

2006 Microchip Technology Incorporated. All Rights Reserved.

2007 Microchip Technology Incorporated. All Rights Reserved.

2007 Microchip Technology Incorporated. All Rights Reserved.

ICD 2 (In Circuit Debugger)

MPLAB ICD 2 is a low cost, real-time

Reading/Writing memory space and

2007 Microchip Technology Incorporated. All Rights Reserved.

PICDEM 2 Plus Board

18, 28 and 40pin DIP sockets