Analog Integrated Circuit Design: A Video Course Under The NPTEL

Analog Integrated Circuit Design
A video course under the NPTEL

Nagendra Krishnapura
Department of Electrical Engineering
Indian Institute of Technology, Madras
Chennai, 600036, India
National Programme on Technology Enhanced Learning
Nagendra Krishnapura: Introduction
www: http://www.ee.iitm.ac.in/nagendra
e-mail: nagendra@iitm.ac.in
Website has reference material, problem sets from other

analog courses, and other resources
Modern signal processing systems
Sensor(s)
Digital Processing
Actuator(s)
...
...
DSP
...0100011011...
...
Continuous-time
Continuous-amplitude
Discrete -time
Discrete -amplitude
Continuous-time
Continuous-amplitude
Interface Electronics
(Signal Conditioning)
(A-D and D-A Conversion)
Picture source: Prof. Shanthi Pavan
Analog circuits in modern systems on VLSI chips
Analog to digital conversion

Digital to analog conversion
Amplification
Signal processing circuits at high frequencies
Power management-voltage references, voltage regulators
Oscillators, Phase locked loops
The last two are found even on many digital ICs
Analog circuits in modern systems on VLSI chips
Analog to digital conversion

Digital to analog conversion
Amplification
Signal processing circuits at high frequencies
Power management-voltage references, voltage
regulators
Oscillators, Phase locked loops
The last two are found even on many digital ICs
Image sensor
Chip Micrograph
Voltage
Regulator
Column
CDS circuits
703 x 499 pixels

(VGA format)
Timing Generator
10b pipelined
ADC
I/O circuit
Chip size: 4.74mm x 6.34mm
H. Takahashi et al., A 3.9 m pixel pitch VGA format 10b digital image sensor with 1.5-transistor/pixel, IEEE
International Solid-State Circuits Conference, vol. XVII, pp. 108 - 109, February 2004.
Wireless LAN transceiver
M. Zargari et al., A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN, IEEE
International Solid-State Circuits Conference, vol. XVII, pp. 96 - 97, February 2004.
DRAM
64 I/Os
ADDRESSES
AND CONTROL
64 I/Os
BANK 3
ROW
DECODERS
BANK 2
DATA LINES
BANK 1
COLUMN
DECODERS
1088
SENSE AMPS
512K
ARRAY
BANK 0
VPP PUMP
K. Hardee et al. A 0.6V 205MHz 19.5ns tRC 16Mb embedded DRAM, IEEE International Solid-State Circuits
Conference, vol. XVII, pp. 200 - 201, February 2004.
Analog IC design in India
Many companies starting analog centers

Multinationals and Indian start ups
Big demand for skilled designers
Interesting and profitable activity
Course goals
Learn to design negative feedback circuits on CMOS ICs

Negative feedback for controlling the output
Amplifiers, voltage references, voltage regulators, biasing
Phase locked loops
Filters
Course prerequisites
Circuit analysis-small and large signal

Laplace transforms, frequency response, Bode plots,
Differential equations
Ideal opamp circuits; Opamp nonidealities
Single transistor amplifiers, differential pairs
Course contents
Course contents-Negative feedback amplifiers
Amplifiers using negative feedback

Stability, Frequency compensation
Negative feedback circuits using opamps
Opamp models
Course contents-Opamps on CMOS ICs
Components available on a CMOS integrated circuit

Device models-dc small signal, dc large signal, ac small
signal, mismatch, noise
Single stage opamp
Cascode opamps
Two stage opamp with miller compensation
Course contents-Fully differential circuits
Differential and common mode half circuits, common mode

feedback
Fully differential miller compensated opamp
Fully differential feedforward compensated opamp
Course contents-Phase locked loop
Frequency multiplication using negative feedback

Type I, type II loops
Oscillators
Phase noise basics
PLL noise transfer functions
Course contents-Design of opamps
Single stage opamp

Folded, telescopic cascode opamps
Two stage opamp
Fully differential opamps and common mode feedback
Applications: Bandgap reference, constant gm bias
generation
Course contents-Applications
Bandgap reference
Constant current and constant gm bias generators
Continuous-time filters
Switched capacitor filters
What is design and how do I learn it?
Design versus Analysis
Design: Create something that doesnt yet exist

Analysis: Analyze something that exists
To be able to design
Knowing analysis is necessary, not sufficient

Multiple ways of looking at building blocks
Trial and error approaches
Approximations
Intuitive thinking/understanding
Curiosity
Open mind
Thoroughness
Intuition
Intuitive thinking is not sloppy thinking!

Relate problems to other problems already solved
Use boundary conditions, dimension checks etc.
Build your intuition
Solve many problems
Think about why the answer is what it is
Come up with the form of the solution before applying full
blown analysis
Using these lectures
Using these lectures
Take notes as you watch

Work out all the steps in solving a problemDont just
watch it being solved
Expect to spend about three hours to understand an hour
long lecture
Brief overview of prerequisites
Circuit analysis
Nodal analysis-Kirchoffs Current Law (KCL) at each node

Solve N simultaneous equations for an N node circuit
Mesh analysis-Kirchoffs Voltage Law (KVL) around each
loop
Solve M simultaneous equations for a circuit with M
independent loops
Nodal analysis
i11 (v ) + i12 (v ) + . . . + i1N (v ) = i1

i21 (v ) + i22 (v ) + . . . + i2N (v ) = i2
..
.
iN1 (v ) + iN2 (v ) + . . . + iNN (v ) = iN
ikl : Current in the branch between nodes k and l

ikk : Current in the branch between node k and ground
vk : Voltage at node k ; v = [v1 v2 . . . vN ]T
ik : Current source into node k
ikl can be a nonlinear function of v
Nodal analysisLinear circuits
g11 v1 + g12 v2 + . . . + g1N vN
= i1
g21 v1 + g22 v2 + . . . + g2N vN
= i2
..
.
gN1 v1 + gN2 v2 + . . . + gNN vN
= iN
gkl : Conductance between nodes k and l

gkk : Conductance between node k and ground
vk : Voltage at node k
Nodal analysisIndependent voltage source
..
.
gk 1 v1 + gk 2 v2 + . . . + gkN vN
vk
= ik
..
.
node k
= Vo
node k
Ideal voltage source Vo connected to node k
Nodal analysisVoltage controlled voltage source
..
.
gk 1 v1 + gk 2 v2 + . . . + gkN vN
= ik
..
.
node k
vk kvl
= 0
node k
Voltage controlled voltage source vk = kvl driving node k
Nodal analysisControlled voltage source
gk 1 v1 + gk 2 v2 + . . . + gkl vl + . . . + gkN vN
vk
gk 1 v1 + gk 2 v2 + . . . +
+ . . . + gkN vN
Rm
gl1 v1 + gl2 v2 + . . . + glk vk + . . . + glN vN
v
gl1 v1 + gl2 v2 + . . . k + . . . + glN vN
Rm
= ik
node k
= ik
node k
= il
node l
= il
node l
Current controlled voltage source vk = Rm ikl driving node k
Nodal analysisControlled current source
gk 1 v1 + gk 2 v2 + . . . + gkl vl + . . . + gkN vN
gk 1 v1 + gk 2 v2 + . . . + gkl vl gm vl + . . . + gkN vN
= ik + gm vl
= ik
Voltage controlled current source i0 = gm vl driving node k
Nodal analysisIdeal opamp
..
.
gm1 v1 + gm2 v2 + . . . + gmN vN
= im
..
.
vk vl
= 0
node m
node m
Ideal opamp with input terminals at nodes k , l and output

at node m
Nodal analysissolution

i1
v1
i2
v2

.. = ..
.
.
iN
vN
gN1 gN2 . . . gNN
g11 g12 . . . g1N

g21 g22 . . . g2N
..
Gv
v
= i
= G1 i
gkl : Conductance between nodes k and l

gkk : Conductance between node k and ground
vk : Voltage at node k
Modified terms for voltage sources or controlled sources
Matrix inversion yields the solution
Nodal analysissolution
vk

g11 g12 . . . i1 . . . g1N

g21 g22 . . . i2 . . . g2N

..

.

gN1 gN2 . . . iN . . . gNN

g11 g12 . . . g1k . . . g1N

g21 g22 . . . g2k . . . g2N

..

.

gN1 gN2 . . . gNk . . . gNN
Cramers rule can be used for matrix inversion
Circuits with capacitors and inductors
I1 (s)
V1 (s)
Y11 (s)Y12 (s) . . . Y1N (s)
I2 (s)
Y21 (s)Y22 (s) . . . Y2N (s) V2 (s)
=
..
..
..
.
.
.
IN (s)
VN (s)
YN1 (s)YN2 (s) . . . YNN (s)
Y(s)V (s) = I(s)

V (s) = Y1 I(s)
Conductances gkl replaced by admittances Ykl (s)

Roots of the determinant of Y(s) are system poles
Laplace transform analysis for linear systems
Input
Output
X (s)
H(s)X (s)
st
X (j)
e
jt
cos(t)
H(s)est
H(j)X (j)
H(j)ejt
|H(j)| cos (t + H(j))
(Steady state solution)
Linear time invariant system described by its transfer

function H(s)
H(s) is the laplace transform of the impulse response
s = j implies a sinusoid of frequency
Laplace transform analysis for linear systems

Transfer function H(s) (no poles at the origin)
1 + b1 s + b2 s 2 + . . . + b M s M
1 + b1 s + b2 s 2 + . . . + b N s N
QM
1 + s/zk
= Adc QNk =1
k =1 1 + s/pk
H(s) = Adc
Single pole at the origin

H(s) =
Q
u M
k =1 1 + s/zk
Q
s N
k =2 1 + s/pk
All poles pk must be in the left half plane for stability
Frequency and time domain analyses
Frequency domain
Algebraic equations-easier solutions
Only for linear systems
Time domain
Differential equations-more difficult to solve
Can be used for nonlinear systems as well
Piecewise linear systems occur quite frequently (e.g.
saturation)
Bode plots
Sinusoidal steady state response characterized by |H(j)|,

H(j)
Bode plot: Plot of 20 log |H(j)|, H(j) versus log
approximated by straight line segments
Good approximation for real poles and zeros
Simulators
Very powerful tools, indispensable for complex calculations, but

GIGO!
Matlab/Octave: System level analysis (Frequency
response, pole-zero, transfer functions)
Spice: Circuit analysis
Maxima: Symbolic analysis
References
Recorded lectures:
http://www.ee.iitm.ac.in/nagendra/videolectures
Behzad Razavi, Design of Analog CMOS Integrated Circuits,
McGraw-Hill, August 2000.
Hayt and Kemmerly, Engineering Circuit Analysis, McGraw Hill,
6/e.
B. P. Lathi, Linear Systems and Signals, Oxford University Press,
2 edition, 2004.
Sergio Franco, Design with operational amplifiers and analog
ICs, Tata McGraw Hill.

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Analog Integrated Circuit Design

A video course under the NPTEL

National Programme on Technology Enhanced Learning