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1. General description
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2)
to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs
(E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines)
decoder with just four 138 ICs and one inverter. The 138 can be used as an eight output
demultiplexer by using one of the active LOW enable inputs as the data input and the
remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
3. Ordering information
Table 1.
Ordering information
Type number
74HC138N
Package
Temperature range
Name
Description
Version
40 C to +125 C
DIP16
SOT38-4
40 C to +125 C
SO16
SOT109-1
40 C to +125 C
SSOP16
SOT338-1
74HCT138N
74HC138D
74 HCT138D
74HC138DB
74HCT138DB
74HC138; 74HCT138
NXP Semiconductors
Table 1.
Type number
Package
74HC138PW
Temperature range
Name
Description
Version
40 C to +125 C
TSSOP16
SOT403-1
40 C to +125 C
74HCT138PW
74HC138BQ
74HCT138BQ
4. Functional diagram
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Logic symbol
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Fig 2.
Functional diagram
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Fig 3.
Logic diagram
74HC_HCT138
2 of 19
74HC138; 74HCT138
NXP Semiconductors
5. Pinning information
5.1 Pinning
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Fig 4.
Fig 5.
Pin description
Symbol
Pin
Description
A0, A1, A2
1, 2, 3
E1, E2
4, 5
E3
output Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 (active LOW)
GND
ground (0 V)
VCC
16
74HC_HCT138
3 of 19
74HC138; 74HCT138
NXP Semiconductors
6. Functional description
Function table[1]
Table 3.
Control
Input
Output
E1
E2
E3
A2
A1
A0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
[1]
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
0.5
+7
IIK
20
mA
IOK
20
mA
IO
output current
25
mA
ICC
50
mA
IGND
ground current
50
mA
Tstg
storage temperature
65
+150
Ptot
[1]
750
mW
SO16 package
[2]
500
mW
SSOP16 package
[3]
500
mW
TSSOP16 package
[3]
500
mW
DHVQFN16 package
[4]
500
mW
[1]
[2]
[3]
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[4]
For DHVQFN16 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT138
4 of 19
74HC138; 74HCT138
NXP Semiconductors
Conditions
74HC138
Min
Typ
74HCT138
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
VI
input voltage
VCC
VCC
VO
output voltage
VCC
VCC
Tamb
ambient temperature
40
+25
+125
40
+25
+125
t/V
VCC = 2.0 V
625
ns/V
VCC = 4.5 V
1.67
139
1.67
139
ns/V
VCC = 6.0 V
83
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to
+85 C
Tamb = 40 C to Unit
+125 C
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
1.2
1.5
1.5
VCC = 4.5 V
3.15
2.4
3.15
3.15
VCC = 6.0 V
4.2
3.2
4.2
4.2
VCC = 2.0 V
0.8
0.5
0.5
0.5
VCC = 4.5 V
2.1
1.35
1.35
1.35
VCC = 6.0 V
2.8
1.8
1.8
1.8
IO = 20 A; VCC = 2.0 V
1.9
2.0
1.9
1.9
IO = 20 A; VCC = 4.5 V
4.4
4.5
4.4
4.4
74HC138
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VI = VIH or VIL
IO = 20 A; VCC = 6.0 V
5.9
6.0
5.9
5.9
3.98
4.32
3.84
3.7
5.48
5.81
5.34
5.2
IO = 20 A; VCC = 2.0 V
0.1
0.1
0.1
IO = 20 A; VCC = 4.5 V
0.1
0.1
0.1
IO = 20 A; VCC = 6.0 V
0.1
0.1
0.1
0.15
0.26
0.33
0.4
VI = VIH or VIL
0.16
0.26
0.33
0.4
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
0.1
1.0
1.0
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
8.0
80
160
74HC_HCT138
5 of 19
74HC138; 74HCT138
NXP Semiconductors
Table 6.
Static characteristics continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
CI
Tamb = 25 C
Conditions
input
capacitance
Tamb = 40 C to
+85 C
Min
Typ
Max
3.5
Min
Max
Tamb = 40 C to Unit
+125 C
Min
Max
pF
74HCT138
VIH
HIGH-level
input voltage
2.0
1.6
2.0
2.0
VIL
LOW-level
input voltage
1.2
0.8
0.8
0.8
VOH
HIGH-level
output voltage
4.4
4.5
4.4
4.4
IO = 4 mA
3.98
4.32
3.84
3.7
IO = 20 A
0.1
0.1
0.1
LOW-level
output voltage
0.15
0.26
0.33
0.4
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
0.1
1.0
1.0
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
8.0
80
160
ICC
additional
supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; An inputs
150
540
675
735
125
450
562.5
612.5
100
360
450
490
3.5
VOL
CI
input
capacitance
74HC_HCT138
pF
6 of 19
74HC138; 74HCT138
NXP Semiconductors
Tamb = 25 C
Conditions
Tamb = 40 C
to +85 C
Tamb = 40 C
to +125 C
Unit
Min
Typ
Max
Min
Max
Min
Max
41
150
190
225
ns
74HC138
tpd
propagation
delay
[1]
VCC = 2.0 V
VCC = 4.5 V
15
30
38
45
ns
VCC = 5 V; CL = 15 pF
12
ns
12
26
33
38
ns
VCC = 6.0 V
E3 to Yn; see Figure 6
[1]
VCC = 2.0 V
47
150
190
225
ns
VCC = 4.5 V
17
20
38
45
ns
VCC = 5 V; CL = 15 pF
14
ns
14
26
33
38
ns
VCC = 2.0 V
47
150
190
225
ns
VCC = 4.5 V
17
20
38
45
ns
VCC = 5 V; CL = 15 pF
14
ns
14
26
33
38
ns
VCC = 2.0 V
19
75
95
110
ns
VCC = 4.5 V
15
19
22
ns
VCC = 6.0 V
13
16
19
ns
67
pF
VCC = 6.0 V
En to Yn; see Figure 7
[1]
VCC = 6.0 V
tt
CPD
transition
time
power
dissipation
capacitance
74HC_HCT138
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
[2]
[3]
7 of 19
74HC138; 74HCT138
NXP Semiconductors
Table 7.
Dynamic characteristics continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C
to +85 C
Tamb = 40 C
to +125 C
Unit
Min
Typ
Max
Min
Max
Min
Max
20
35
44
53
ns
17
ns
18
40
50
60
ns
19
ns
74HCT138
propagation
delay
tpd
[1]
[1]
[1]
19
40
50
60
ns
VCC = 5 V; CL = 15 pF
19
ns
15
19
22
ns
67
pF
tt
transition
time
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC 1.5 V
[2]
VCC = 4.5 V
[1]
[3]
[2]
[3]
74HC_HCT138
8 of 19
74HC138; 74HCT138
NXP Semiconductors
11. Waveforms
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Propagation delay input (An) and enable input (E3) to output (Yn) and transition time output (Yn)
9&&
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Fig 7.
Propagation delay enable input (En) to output (Yn) and transition time output (Yn)
Table 8.
Measurement points
Type
Input
Output
VM
VM
74HC138
0.5VCC
0.5VCC
74HCT138
1.3 V
1.3 V
74HC_HCT138
9 of 19
74HC138; 74HCT138
NXP Semiconductors
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9
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WU
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Table 9.
Test data
Type
Input
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74HC138
VCC
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HCT138
3V
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HC_HCT138
Load
S1 position
10 of 19
74HC138; 74HCT138
NXP Semiconductors
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NXP Semiconductors
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NXP Semiconductors
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NXP Semiconductors
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NXP Semiconductors
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74HC138; 74HCT138
NXP Semiconductors
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
DUT
ESD
ElectroStatic Discharge
HBM
TTL
Transistor-Transistor Logic
MM
Machine Model
Revision history
Document ID
Release date
Change notice
Supersedes
74HC_HCT138 v.5
20150126
74HC_HCT138 v.4
Modifications:
74HC_HCT138 v.4
Modifications:
74HC_HCT138 v.3
Modifications:
Table 6: OFF-state output current removed because device has no 3-state outputs.
Table 7: Power dissipation capacitance condition for 74HCT138 is corrected.
20120627
74HC_HCT138 v.3
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
SOT38-1 changed to SOT38-4.
20051223
74HC_HCT138_CNV v.2
The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
74HC_HCT138
Product specification
16 of 19
74HC138; 74HCT138
NXP Semiconductors
Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT138
17 of 19
74HC138; 74HCT138
NXP Semiconductors
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
74HC_HCT138
18 of 19
NXP Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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