NITIN MATHUR

Date of
Birth:
E-mail ID:
Address:

9-Mar-89

Contact No: 8792539438,

nitinmathur1989@gmail.com
Tajmahal PG, Room no:202, No. 88,
Jakksandra, Koramangala,
Bangalore-506034

9652656725

Career Objective
To work in an organization that will utilize and enhance my skill sets in the field of, CMOS IC Circuit
design, Layout and ASIC / FPGA design and applications.

Academic Qualification
Exam / Degree
Year

Name of Institute

University / Board

Percentage

M. Tech.
(VLSI System Design)

2014

National Institute Of
Technology, Warangal

National Institute Of
Technology, Warangal

8.45
CGPA

B. Tech.
(E.C.E)

2011

Rajasthan Technical
University, Kota

73.30%

Class XII

2006

CBSE

71.40%

Class X

2004

Arya College of
Engineering and I.T, Jaipur
The Aditya Birla Public
School, Chittaurgarh (Raj.)
Delhi Public School,
Chittaurgarh (Raj.)

CBSE

81.80%

Projects
M. Tech.

1. Design and Implementation of Digital Up Converter for Multi-Standard Software Radio.

2. Design of Two Stage CMOS OpAmp in 180nm Technology using Cadence Tools.
3. Design and Implementation of 32 bit MIPS Processor.
4. Design and Implementation of 64 bit MAC unit with Guard bits for DSP applications.

B. Tech.

1. Infrared based Digital Object Counter using 8052 microcontroller.

Skill Set

EDA Tools: Synopsys VCS & Design Compiler, Cadence Virtuoso, Xilinx ISE, Tanner Tools
Hardware Description Languages: Verilog, VHDL.
Programming and Scripting Languages: C++, TCL
Platforms: Linux, Windows.

Area of Interest
ASIC Design, RTL Design
Physical Design
FPGA Design

Awards and Achievements

Passed M. Tech examination in First Division with Distinction.

Secured 286th rank in GATE-2012 with 99.99 percentile.
Awarded Marker cup for excellent performance in Computer Sc. in 12th standard.
Awarded Certificate of Merit for Science in 10th standard.

Extra - Curricular Activities

Participated in "Autonomous Robotic Workshop" in MNIT, Jaipur
Participated in Volleyball & Table Tennis competitions at College and School level
Participated in various Arts and Crafts competitions at School level

References
1) Mr. Sree Hari Rao Patri
Associate Professor, Chip Design Centre,
ECE Dept., NIT Warangal
Mob: +91 9441342324
2) Mrs B. Lakshmi
Associate Professor, Chip Design Centre,
ECE Dept., NIT Warangal
Mob: +91 9493436845

Declaration
I, the undersigned, hereby declare that the information furnished above is true, complete and correct to the
best of my knowledge.

Date: 12/08/2014

Nitin Mathur