Professional Documents
Culture Documents
Layout of Analog Cmos Integrated Circuit: F. Maloberti
Layout of Analog Cmos Integrated Circuit: F. Maloberti
Maloberti
Layout of Analog
CMOS
Integrated Circuit
Part 2
Outline
Introduction
Process and Overview Topics
Transistors and Basic Cells Layout
Passive components: Resistors, Capacitors
System level Mixed-signal Layout
Polysilicon gate
diffusion
Parallel elements
silicon is unisotropic
Shadowed region
Source and drain are not equivalent
F. Maloberti - Layout of Analog CMOS IC
Parasitics in Transistors
Analog transistors often have a large W/L ratio
W
LD
10
S
C ' SB ; C ' DB
D
W/2
W/3
S
CSB
1
'
= C DB ; C DB = C DB
2
11
2
CSB = C ' SB
3
2
C DB = C ' DB
3
12
Interdigitated Devices
Two matched transistors with one node in common
spilt them in an equal part of fingers (for example 4)
interdigitate the 8 elements: AABBAABB or ABBAABBA
1
1
A
13
B
3
Axis of Symmetries
Common axis
of symmetry
Axis of symmetry
of device B
Axis of symmetry
of device A
(A)
(B)
14
Common axis of
symmetry
(C)
Interdigitiation Patterns
A
AA
AAA
AAAA
AB*
ABBA
ABBAAB*
ABABBABA
ABC*
ABCCBA
ABCBACBCA*
ABCABCCBACBA
ABCD*
ABCDDCBA
ABCBCADBCDA*
ABCDDCBAABCDDCBA
ABA
ABAABA
ABAABAABA
ABAABAABAABA
ABABA
ABABAABABA
ABABAABABAABABA ABABAABABAABABAABABA
AABA*
AABAABAA
AABAAABAAABA*
AABAA
AABAAAABAA
AABAAAABAAAABAA AABAAAABAAAABAAAABAA
AABAABAAAABAABAA
15
16
Common Centroid
DA
DB
DA
DB
DB
DA
DB
DA
17
Cross coupling
18
ABBAABBA
BAABBAAB
ABBAABBA
BAABBAAB
ABBAABBA
ABBAABBA
BAABBAAB
BAABBAAB
ABBAABBA
ABA
BAB
ABAABA
BABBAB
ABAABA
BABBAB
ABAABA
ABAABAABA
BABBABBAB
BABBABBAB
ABAABAABA
ABCCBA
CBAABC
ABCCBAABC
CBAABCCBA
ABCCBAABC
CBAABCCBA
ABCCBAABC
ABCCBAABC
CBAABCCBA
CBAABCCBA
ABCCBAABC
AAB
BAA
AABBAA
BAAAAB
AABBAA
BAAAAB
AABBAA
AABBAA
BAAAAB
BAAAAB
AABBAA
19
s
Dummies are shorted transistors
Remember their parasitic contribution!
F. Maloberti - Layout of Analog CMOS IC
20
Matched interconnections
V = Z int I
21
22
Waffle Transistor
S
Minimum capacitance
drain-substrate and
source-substrate
W not accurate
L not well defined
23
24
Stacked Layout
Systematic use of stack or transistors (multi-finger
arrangement)
Same width of the fingers in the same stack, possibly
different length
Design procedure
Examine the size of transistors in the cell
Split transistors size in a number of layout oriented fingers
Identify the transistors that can be placed on the same stack
Possibly change the size of non-critical transistors
Use (almost) the same number of finger per stack
place stacks and interconnect
F. Maloberti - Layout of Analog CMOS IC
25
EVEN
d s d
ODD
d
Ending drain
s d
d s
Ending source
F. Maloberti - Layout of Analog CMOS IC
26
s d
S/D ending
d s d
D/S ending
M2
3
M3
4
2 1 2 3 4
1 2 3 4
Same width
M1 double
2
1 2 1 2 3 2 3 4 3 4
M1
M2
3 4 3 2 1 2 3 4 3
M3 M2 M1 M2 M3
F. Maloberti - Layout of Analog CMOS IC
27
M3
3 4 3 2 1 2 1 2 3 4 3
M3 M2
M1
M2 M3
M3
M4
30
108
M6
M1
M2
60
60
M5
40
72
M7
28
M3
M4
30
108
M6
M1
M2
60
60
72
M5
M7
40
M3, M4, M6
M1, M2
M5, M7
F. Maloberti - Layout of Analog CMOS IC
29
M4
M6
M3
D3
M4
M1
M2
O1
6
CS
M5
M2
M1
VDD
O1
M6
M6
OUT
M7
First attempt of
interconnections
(not completed)
M7
M5
M7
30
GND
M4
O1
CS
M2
M1
M5
M5
GND
31
M3
D3
M4
M1
M2
M6
OUT
CS
M5
OUT
O1
M7
GND
32
Input-Output
Well and its bias
Substrate bias
Compensation
Bias voltage
Bias current
VDD
Rectangular shape
System oriented cell layout
Related cells with same height
Vdd and GND crossing the cell
In and Out properly placed
F. Maloberti - Layout of Analog CMOS IC
33
GND
30
30
MP
M4
M3
60
M6
60
M5
M1
M2
80
80
M11
MN
16
16
34
38
38
M7
M8
M9
M10
25
25
Split of Transistors
20
30
MP 2
30
3
M3
M4
M5
M6
6
60
60
M1
M2
40
M7
80
80
M8
40
38
MN
M11
16 2
16
35
M9
25
24
M10
24
Stack Design
MP 2
M3
555555344PP334666666
M4
M6
10x2
M1
M5 6
5
M2
M11
2
M8
M7
MN
11221122112211221122
22112211221122112211
777779xxoo99nno88888
M10
M9
3
X=11; o=10
36
Interconnection: Exercise
Sketch the source-drain interconnections of the folded-cascode
37
38