FD-SOI

TRANSISTOR & CHIP

FABRICATION PROCESS

Presented By:
Abhishek Anand
Aman Agrawal
EC VIIth SEM
OIST

INTRODUCTION

FD-SOI stands for Fully Depleted Silicon On

Insulator.
In FD-SOI source and drain are placed on the top
of substrate.
It incorporates a BOX layer just below channel.

Bulk & FD-SOI

Transistors

CHIP FABRICATION PROCESS

Earlier reduction in size of transistors helped in producing

faster chips which dissipated less heat.

P4 had 125m transistors made with 90nm while sandy

bridge made of 32nm tech have 1b+ transistors.

But further reduction in size became inefficient.

So a change of architecture was demanded.

BULK TRANSISTORS & CURRENT

LEAKAGE

Smaller fab process brings source, drain and

substrate closer & they influence each other.

The electrons flow through channel even with no

voltage at gate. This is current leakage.

Further in 32nm transistor gate is 1nm thick.

Silicon atom has dia of 0.3nm.

CURRENT LEAKAGE

SOLUTION IS FD-SOI

Isolating the channel from rest of substrate is a

solution to the leakage of electrons flowing
inadvertently from gate to channel.

An insulating layer called Buried Oxide is used as

an insulator between substrate and channel.

ADVANTAGES

Lower fab process up to 14nm became possible.

Lower production cost.
Less power consumption in mobile devices.
Only 0.6V power consumption in idle devices.
Higher clock speed for mobile chips.

PERFORMANCE GRAPH

DISADVANTAGES

BOX wafers are more costly than bulk transistors

wafers.
Tri-gate technology from Intel proves to be more
efficient.

It is still not popular among leading chip

manufacturers.

USES

STMicroelectronics has already started producing

FD-SOI transistors for ST-Ericsson mobile
processors.

Sony has used these FD-SOI made processors in

its Xperia P and U smartphones.

FD-SOI is making its way to AMD and IBM

processors.

FUTURE EXPECTATIONS
FD-SOI 3D : (around 2016)
To bring chip sizes down to 11nm , both
FD-SOI and tri-gate technologies need
to be combined.

THANK YOU