UNIT-II

3. a) For the following circuit

i) Find the set of all tests that detect the fault a s a o
ii) Find the set of all tests that detect the multiple fault

a s a o, b s a o
b) Explain critical path tracing with an example

OR

4. a) Explain Single stuck Fault model with an example

b) Explain concurrent fault simulation

6
6

UNIT-III
5. a) Explain Fanout-Free circuits using. Justify and propagate
pseudo code
b) Explain critical path TG algorithm

6
6

OR

6. a) Explain the procedure to generate the self initializing test

sequence for sequential circuits with an example
b) Explain Functional Fault models for microprocessors

6
6

UNIT-IV
7. a) Explain generic scan-based designs
b) Explain the level sensitive scan design rules

6
6

OR
8. a) Discuss about storage cells for scan design
b) Explain ones-count compression

6
6

UNIT-V
9. a) Write a short notes on generic off line BIST Architectures
b) Explain LOCST Architecture

6
6

OR
10. a) Write a short notes on any two TPG techniques
b) Write a short notes on CATS and CSTP

6
6
[12/II S/210]

[EPRVD 204A]
M.Tech. DEGREE EXAMINATION
VLSI DESIGN
II SEMESTER
DIGITAL SYSTEMS TESTING & TESTABILITY
(Effective from the admitted batch 200910)
Time: 3 Hours
Max.Marks: 60
--------------------------------------------------------------------------------- ------------------Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
--------------------------------------------------------------------------------------- -------------

UNIT-I
1. a) Explain structural model representations
b) Use 3-valued complied simulation to simulate the following
circuit, starting with Q = u for the input vectors 01 and 11

2. a) Derive a binary decision diagram for the function f

b) Explain Hazard Detection Procedures

a b c ac