ANNA UNIVERSITY: CHENNAI-600025

B.E DEGREE EXAMINATION, APRIL 2014

Regulations-R-2008
SIXTH SEMESTER
B.E ELECTRONICS AND COMMUNICATION ENGINEERING
EC 2357 - VLSI DESIGN LAB
Time:3 Hours

Maximum marks : 100

1. Write a Verilog HDL program to add two 8- bit numbers using behavioural
model and implement the same in FPGA and also draw the hardware circuit
and RTL schematic of the same.(100)

2. (i) Design and simulate 2-bit multiplier Using Verilog HDL.(50)

(ii) Develop a verilog HDL program for 3 to 8 decoder using dataflow
model. (50)

3. (i) Design and simulate a digital circuit to add two 8-bit numbers with help
of two four bit adders using Verilog HDL code.(50)
(ii) Design a half subtractor using Verilog HDL. (50)

4. Develop a verilog HDL program to select only one output from eight inputs.
Implement the same in FPGA. Use data flow model, behavioural model and
structural model. (100)

5. (i) Design a 4 to 2 encoder using Verilog HDL .(use structural model)(50)

(ii)Write a verilog HDL program for 4-bit multipliers using structural
model. (50)

6. Develop a verilog HDL program to design 1-8 DEMUX and implement the
same in FPGA. Use data flow model, behavioural model and structural
model.
(100)

7. (i) Design and simulate a 4- bit counter using Verilog HDL program (use
Structural model .(50)
(ii) Develop a Verilog program for D Flip flop by using behavioural
model.(50)

8. (i) Design a digital circuit which can generate 5-bit code randomly using
Verilog HDL. (50)
(ii) Write a test bench program for 8 to 1 MUX and draw the simulation
waveforms. (50)
9. (i) Write a Verilog program for 4-bit accumulator using behavioural
style.(50)
(ii) Write a test bench program for 1 to 8 DE MUX and draw the simulation
waveforms.(50)
10. Develop and simulate Verilog HDL programs for D FF, JK FF and TFF by
using data flow model, behavioural model and structural model. (100)

11. Write a Verilog HDL program for JKFF by using behavioural style and also
implement the same in FPGA. (100)

12.(i)Design a digital circuit which can count the given 16 clock pulses using
Verilog HDL.(50)
(ii) Write a test bench program for D-FF (50)

13.(i)Design a 4 bit ripple counter using Toggle flip flop using Verilog
HDL.(50)
(ii)Design a digital circuit which can store a given 4 bit data and accumulate
the intermediate results using Verilog HDL.(50)

14. Generate the schematic entry of MOS Differential Amplifier using

LTSPICE and plot the AC characteristics to obtain gain, bandwidth, output
impedance and CMRR.(100)

15. Generate the DC characteristics of CMOS inverter using CADENCE tool.

Extract parasitic elements.(100)

16. Design and implement NMOS and CMOS inverters. Find their Switching
time and electrical characteristics. Use + 5 logic level to choose the MOS
devices and construct the inverter. (100)

17. Develop the source code for binary to gray converter by using VERILOG
and obtained the simulation, synthesis, place and route and implement into
FPGA.(100)

18. Develop the source code for full adder using three modeling styles by using
VERILOG and obtained the simulation, synthesis, place and route and
implement into FPGA.(100)

19. Implement a CMOS inverter using transistors sizes PMOS: W=35m,

NMOS:W=1.55m, lengths L=600nm. Calculate the rise time and fall time.
And then, (1)keep the size of NMOS and change the width of the PMOS to
45m, and calculate the rise time and fall time. Also, (2) keep the size of
PMOS and change the width of the NMOS to 35m, and calculate the rise
time and fall time again. Finally state the general rule of sizing and
timing.(100)

20. Develop the source code for logic gates by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.(100)

21. Write a test bench Verilog HDL program for 3 to 8 decoder and BCD
encoder .(100)

22. Draw a combinational circuit for full adder using only NAND gates.
Develop a Verilog HDL program for the same by using structural level
modeling and also write a test bench program.
Mark allotment pattern
Aim/procedure/Algorithm

-25

Circuit diagram/program

-25

Connections/execution

-15

Results

-25

Viva

-10

Total

-100