Mixed Signal Verification:

Model Development
Tristan Simetkosky
Packet Digital
April 17, 2015

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Packet Digital Background

Packet Digital is a provider of power management solutions, including the PowerSage® family of ICs.
Packet Digital also provides engineering services, including hardware, software, and ASIC design.
Key Statistics
Corporate Headquarters Fargo, North Dakota

Company Footprint Offices in Fargo, ND and Austin, TX; Channel partners in Asia

Founded 2003

Re-Invented 2008

Key Partners SMART, Intel, Cisco

Patents Awarded 12 patents with additional patents pending

Product Accolades Gartner Cool Vendor 2014, Forbes, Wall Street Journal, Fox National
Business News, Inc. 500, Department of Defense, Aviation Week and others

Industry Experience Our senior management team has more than 50 years of collective experience
in hardware and software delivery

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Overview

• Verification challenges at Packet Digital

• Addressing verification challenges
• Options for developing models
• Model development procedures
• DAC model example
• Benefits of SystemVerilog real number models

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Verification Challenges at Packet Digital

• Timeline
• Meet customer design schedules
• Fabrication schedules
• Need high quality first silicon
• Impress customers
• Long fabrication times
• Simulation time / License constraints
• Full chip sims in parallel with block level extracted and/or Monte Carlo
simulations

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Sample Design

25% Digital
75% Analog

~15 Analog blocks:

DAC, LDO, VREF, IREF, Oscillators,
timers, amplifiers, charge pumps, ...

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Verification Flow Strategies

Models of analog circuits enable:

• Reduced simulation time
• Better license utilization
• Accurate full chip simulations
• Verification of system level operation
• Higher quality silicon

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Modeling Options

Verilog
+ Faster than Spice
+ Digital solver only
- No real ports ($bitstoreal / $realtobits)

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Modeling Options

Verilog
+ Faster than Spice
+ Digital solver only
- No real ports ($bitstoreal / $realtobits)

Verilog-AMS Analog
+ Faster than Spice
+ Electrical signals (voltage, current)
- Requires analog solver
- Convergence errors

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Modeling Options

Verilog Verilog-AMS wreal

+ Faster than Spice + Faster than Spice
+ Digital solver only + Digital solver only
- No real ports ($bitstoreal / $realtobits) + Real ports
- Single-value nets (voltage or current)
- No SystemVerilog constructs

Verilog-AMS Analog
+ Faster than Spice
+ Electrical signals (voltage, current)
- Requires analog solver
- Convergence errors

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Modeling Options

Verilog Verilog-AMS wreal

+ Faster than Spice + Faster than Spice
+ Digital solver only + Digital solver only
- No real ports ($bitstoreal / $realtobits) + Real ports
- Single-value nets (voltage or current)
- No SystemVerilog constructs

Verilog-AMS Analog SystemVerilog real

+ Faster than Spice + Faster than Spice
+ Electrical signals (voltage, current) + Digital solver only
- Requires analog solver + Multi-value nets (UDT/UDR)*
- Convergence errors + SV constructs and verification
techniques

*SV IEEE 1800-2012

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Verilog-AMS wreal and SystemVerilog real

Verilog-AMS wreal (Verilog-AMS Language Reference Manual 2.4.0)

• wreal nets can can only be driven by a single driver
• Undriven nets have a value of 0.0 (instead of X/Z)

SystemVerilog IEEE 1800-2009 real

• Real ports
• Single drivers (i.e. no resolution functions)

SystemVerilog IEEE 1800-2012 real

• Multiple drivers
• User Defined Types (UDT) and User Defined Resolution (UDR)
functions

*Vendor implementations may offer enhancements

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Modeling Options

Source: Cadence white paper “Solutions for Mixed-Signal SoC Verification Using Real Number Models”

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Model Development

Procedure:
• Construct Verilog-AMS analog model
• Leverage spice netlist if available
• Build a testbench
• Verify
• Basic functionality
• Port polarity
• Trimming
• Slew rates
• Propagation delays
• Construct Real Number Model (RNM)
• Focus on sim performance
• Compare model against spice circuit as available or as changes are
made

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DAC Example

Statistics:
2000 Transistors
8-bit R2R DAC 300 Resistors
50 Capacitors
4 Diodes

Inputs: Outputs: Supplies:

VREF_1V2 VDAC VDDA_3V3
EN OA1_TEST VDDA_1V8
TRIM_EN OA2_TEST VSSA
VREF_TRIM[7:0] AN_TEST
OA1_TRIM[7:0]
OA2_TRIM[7:0]
SETPOINT[7:0]

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DAC Example

R2 R1

VREF_1V2 VOUT
R2R Ladder OA R2R Ladder OA

VREF_TRIM[7:0] OA1_TRIM[7:0] SETPOINT[7:0] OA2_TRIM[7:0]

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DAC Example

R2 R1

VREF_1V2 VOUT
R2R Ladder OA R2R Ladder OA

VREF_TRIM[7:0] OA1_TRIM[7:0] SETPOINT[7:0] OA2_TRIM[7:0]

Sources of variation:
● VREF_1V2 accuracy
● Resistor mismatch
● OA offset

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Modeling Process Variation

Obtain the range variation from spice simulations (corners or Monte Carlo)
Use compiler directives to choose an offset:

`ifdef CORNER_SS
t_slew = 500n;
op1_offset = 0.07 + 0.02 * ($urandom_range(0,200)/100.0 - 1.0); //-1.00:1.00
`elsif CORNER_FF
t_slew = 300n;
op1_offset = 0.05 + 0.02 * ($urandom_range(0,200)/100.0 - 1.0);
`elsif CORNER_RAND
t_slew = (400 + 100.0 * ($urandom_range(0,200)/100.0 - 1.0)) * 1e-9;
op1_offset = 0.06 + 0.03 * ($urandom_range(0,200)/100.0 - 1.0);
`else
t_slew = 400n;
op1_offset = 0.06;
`endif

//calculate expected trim

calc_trim_op1_offset = op1_offset / trim_step;
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DAC Example - Verilog-AMS Analog Model

VREF RS
VDAC_int
SETPOINT[7:0] DAC VDAC

always @( SETPOINT, absdelta(V(VREF), 0.005) ) begin

v_dac = V(VREF) * SETPOINT/255.0;
end

analog begin
V(VDAC_int,VSSA) <+ transition(v_dac, t_d, t_r, t_f); //model slew rates
I(VDAC_int,VDAC) <+ (V(VDAC_int,VDAC)) / r_ser; //model drive
strength
end

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DAC Example - Verilog-AMS Analog Model

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DAC Example - Verilog-AMS Analog Model Sim Time

Simulation time
● Spice simulation: 139 s
● Verilog-AMS Analog: 220 ms

Very nice, but what about a pure real number model?

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DAC Example - Verilog-AMS wreal / SV RNM Single Value Net

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SystemVerilog RNM

SystemVerilog RNM hurdles:

• Single valued nets
• How to model drive strength?
• Real number ports can only have a single driver
• How to model multiple loads on a signal?

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SystemVerilog RNM

SystemVerilog RNM hurdles:

• Single valued nets
• How to model drive strength?
• Real number ports can only have a single driver
• How to model multiple loads on a signal?

Solution:
• SystemVerilog IEEE 1800-2012
• User Defined Types (UDT)
• User Defined Resolution (UDR) functions

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DAC Example - Drive Strength - UDT/UDR

//user-defined resolution (UDR) function

RS function automatic elec_type elec_sum (input elec_type driver[]);
//[variable declarations]

foreach (driver[i]) begin

if(driver[i].voltage > max_v) begin
max_v = driver[i].voltage;
max_index = i;
src_res = driver[i].resistance;
end
else begin
load_res_inv += 1.0 / driver[i].resistance;
//user-defined type (UDT) end
typedef struct { end
real voltage;
real current; load_res = 1.0 / load_res_inv;
real resistance; elec_sum.voltage = (driver[max_index].voltage * (load_res)
} elec_type; / (load_res + src_res));
elec_sum.current = driver[max_index].voltage
/ (load_res + src_res);

endfunction

nettype elec_type elec_net with elec_sum;

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DAC Example - Drive Strength - UDT/UDR
module DAC
...
RS output VDAC;
elec_net VDAC;

//elec_type’{voltage, current, resistance}

assign VDAC = elec_type'{v_dac, 0, 900.0}; //900 ohm Rs
...
endmodule

module resistive_load
...
input RES_VAL;
input VIN;
real RES_VAL;
elec_net VIN;

real resistance = 10000.0;

assign VIN = elec_type'{0.0, 0.0, resistance};

always @(RES_VAL) begin

resistance = RES_VAL;
end
...
endmodule
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DAC Example - SV RNM Multi-Value Net

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DAC Example - Slew Rate

//VDAC slew rate control, 10ns/10mV

always @( v_dac_target ) begin
while( v_dac != v_dac_target ) begin
if( v_dac_target < v_dac ) begin
v_dac = (v_dac - 0.01) > v_dac_target ? v_dac - 0.01 :
v_dac_target;
end else begin
v_dac = (v_dac + 0.01) < v_dac_target ? v_dac + 0.01 :
v_dac_target;
end
#10;
end
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DAC Example - Sim Times

Simulation time
● Spice simulation: 139 s
● Verilog-AMS Analog: 220 ms
● Verilog-AMS wreal: <100 ms
● SystemVerilog real: <100 ms
● SystemVerilog real MVN: <100 ms

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DAC Example - SV RNM Multi-Value Net - Power Analysis

Stimulus:
elec_net VDDA_3V3, VDDA_1V8, VSSA;

// elec_type’{voltage, current, resistance}

assign VDDA_3V3 = elec_type’{3.3, 0.0, 0.0};
assign VDDA_1V8 = elec_type’{1.8, 0.0, 0.0};
assign VSSA = elec_type’{0.0, 0.0, 0.0};

Circuit Model:
assign VDDA_1V8 = elec_type'{0.0, 0, 900.0};
assign VDDA_3V3 = elec_type'{0.0, 0, 3300.0};
or
assign VDDA_1V8 = elec_type'{0.0, 0, EN_I == 1'b1 ? 900.0 : 1e6};
assign VDDA_3V3 = elec_type'{0.0, 0, EN_I == 1'b1 ? 3300.0 : 1e6};

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DAC Example - SV RNM Multi-Value Net - Power Analysis

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DAC Example - SV RNM - Assertions

always @(negedge EN_I) begin

#1000; //1us to discharge
assert_dac_en:
assert (VDAC.voltage < 0.010) else
$display("ERROR: VDAC output should be 0V");
end

always @(VDAC.voltage) begin

assert_dac_vmax:
assert (VDAC.voltage < 2.2) else
$display("ERROR: VDAC output is too high:%0.2fV", VDAC.voltage);
end

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DAC Example - SV RNM - Assertions

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Summary

• Model development procedure

• Language options and tradeoffs for mixed-signal verification
• Key functionality that can be included in a model
• A DAC model example
• How to use SystemVerilog RNM to more accurately model analog circuits

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Thank You

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