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Concept to Silicon
Victor P. Nelson
ASIC Design Flow
Behavioral
Verify
Model
Function
VHDL/Verilog
Synthesis
DFT/BIST Gate-Level Verify
& ATPG Netlist Function
Physical
DRC & LVS Verify
Layout
Verification Timing
Map/Place/Route
VHDL VHDL-AMS
Verilog Create Behavioral/RTL
HDL Model(s) Verilog-A
SystemC
Leonardo
Spectrum, Synthesize
Xilinx ISE Circuit
(digital)
Technology Libraries
Post-Layout Simulation,
Technology-Specific Netlist
to Back-End Tools
ADVance MS Simulation System
ADVance MS “kernel” supports:
– VHDL & Verilog: digital (via ModelSim)
– VHDL-AMS & Verilog-A: analog/mixed signal
– Eldo/SPICE: analog (via Eldo)
– Eldo RF/SPICE: analog RF (via Eldo RF)
– Mach TA/SPICE: high-speed analog/timing
Invoke stand-alone or from Design
Architect-IC
ADVance MS
Digital, Analog, Mixed-Signal Simulation
VHDL,Verilog,
VHDL-AMS, Verilog-A,
SPICE Netlists SPICE Xilinx
VITAL
models simprims
Working Design_1
Library Design_2 IEEE 1164 Resource
Libraries
Simulation Input
ADVance MS
Setup Stimuli
Mixed Signal
Eldo, EZwave (VHDL-AMS,
Eldo RF or Xelga ModelSim Verilog-A)
Analog Mach TA View Results
(SPICE) Mach PA Digital
(VHDL,Verilog)
Example: 4-bit binary counter
VHDL model (count4.vhd)
– Create working library: vlib work
vmap work work
– Compile: vcom count4.vhd
– Simulate: vsim count4(rtl)
ModelSim simulation-control inputs
– ModelSim “Macro” (count4_rtl.do)
– OR, VHDL testbench
ModelSim results
– listing or waveform
-- count4.vhd 4-bit parallel-load synchronous counter
LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; --synthesis libraries
ENTITY count4 IS
PORT (clock,clear,enable,load_count : IN STD_LOGIC;
D: IN unsigned(3 downto 0);
Q: OUT unsigned(3 downto 0));
END count4;
Clear
Counting
Parallel
Load
ADVance MS : mixed-signal simulation
A/D converter
digital
analog
VHDL-AMS
ADVance MS: mixed Verilog-SPICE
Verilog top
(test bench)
SPICE
subcircuit
Automated Synthesis with
Leonardo Spectrum
VHDL/Verilog
Technology Behavioral/RTL Models
Synthesis
Libraries
wire nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187,
nx189;
wire [3:0] \$dummy ;
dffr Q_0__rename_rename (.Q (Q[0]), .QB (\$dummy [0]), .D (nx126), .CLK (clock), .R (clear)) ;
mux21_ni ix127 (.Y (nx126), .A0 (Q[0]), .A1 (nx8), .S0 (enable)) ;
oai21 ix9 (.Y (nx8), .A0 (load_count), .A1 (Q[0]), .B0 (nx169)) ;
nand02 ix170 (.Y (nx169), .A0 (D[0]), .A1 (load_count)) ;
dffr Q_1__rename_rename (.Q (Q[1]), .QB (\$dummy [1]), .D (nx136), .CLK (clock), .R (clear)) ;
mux21_ni ix137 (.Y (nx136), .A0 (Q[1]), .A1 (nx28), .S0 (enable)) ;
ao22 ix29 (.Y (nx28), .A0 (D[1]), .A1 (load_count), .B0 (nx14), .B1 (nx22) ) ;
or02 ix15 (.Y (nx14), .A0 (Q[0]), .A1 (Q[1])) ;
aoi21 ix23 (.Y (nx22), .A0 (Q[1]), .A1 (Q[0]), .B0 (load_count)) ;
dffr Q_2__rename_rename (.Q (Q[2]), .QB (\$dummy [2]), .D (nx146), .CLK (clock), .R (clear)) ;
mux21_ni ix147 (.Y (nx146), .A0 (Q[2]), .A1 (nx48), .S0 (enable)) ;
oai21 ix49 (.Y (nx48), .A0 (nx181), .A1 (nx183), .B0 (nx189)) ;
aoi21 ix182 (.Y (nx181), .A0 (Q[1]), .A1 (Q[0]), .B0 (Q[2])) ;
nand02 ix184 (.Y (nx183), .A0 (nx185), .A1 (nx187)) ;
inv01 ix186 (.Y (nx185), .A (load_count)) ;
nand03 ix188 (.Y (nx187), .A0 (Q[2]), .A1 (Q[1]), .A2 (Q[0])) ;
nand02 ix190 (.Y (nx189), .A0 (D[2]), .A1 (load_count)) ;
dffr Q_3__rename_rename (.Q (Q[3]), .QB (\$dummy [3]), .D (nx156), .CLK (clock), .R (clear)) ;
mux21_ni ix157 (.Y (nx156), .A0 (Q[3]), .A1 (nx62), .S0 (enable)) ;
mux21_ni ix63 (.Y (nx62), .A0 (nx54), .A1 (D[3]), .S0 (load_count)) ;
xnor2 ix55 (.Y (nx54), .A0 (Q[3]), .A1 (nx187)) ;
endmodule
Post-synthesis simulation
(Leonardo-generated netlist)
Verify synthesized netlist matches behavioral
model
Create simulation primitives library for std cells:
>vlib adk VITAL
>vcom $ADK/technology/adk.vhd
>vcom $ADK/technology/adk_comp.vhd models of all
ADK std cells
Insert library/package declaration into netlist
library adk;
use adk.adk_components.all;
Memory
& Logic
BIST Boundary
Scan
Internal
Scan Design
ATPG
DFTadvisor/FastScan Design Flow
count4.vhd
count4_0.vhd
count4.v
DFT/ATPG count4_scan.v
Library:
adk.atpg
ATPG Library
DFT Advisor Insert Internal
Scan Circuitry
adk.atpg
VHDL/Verilog
Netlist With
Scan Elements
Fastscan/ Generate/Verify
Flextest Test Vectors
Layout vs.
Generate Design Rule Backannotate
Schematic
Mask Data Check Schematic
Check
Calibre Calibre Calibre
IC Mask Data Mach TA/Eldo Simulation Model
Cell-Based IC
Cell-Based Block
Basic standard
Cell layout
-Netlist
-Simulation cmds
-Stimulus
SPICE “circuit” file generated by DA-IC SPICE netlist for modulo7 counter
From ADK
library
v1
td tr tw tf
Force functions (3)
Pattern wave (for logic 0 & 1 values)
Vname B 0 pattern 5 0 5n 0.1n 0.1n 10n 011010 R
Bit pattern
Rise & Fall
Between circuit Logic 1 & 0 Time between
Nodes B & GND voltages Delay tochanges Duration of
(node 0) waveform bit value Repeat
begin the pattern
(optional)
1 1 1
0 0 0
delay pattern
Eldo simulation of modulo7 counter
(transient analysis)
Create a std-cell based logic block
in IC Station
Invoke: adk_ic
In IC Station palette, select: Create Cell
– Cell name: count4
– Attach library: $ADK/technology/ic/process/tsmc035
– Process: $ADK/technology/ic/process/tsmc035
– Rules file: $ADK/technology/ic/process/tsmc035.rules
– Angle mode: 45
– Cell type: block
– Select With connectivity
– EDDM schematic viewpoint: count4/layout
– Logic loading options: flat
Create Cell dialog box
Auto-”floorplan” the block
place & route > autofp
Auto-place the std cells
Autoplc > StdCel
Auto-place “ports” (Autoplc > Ports) Signal
connections on cell boundaries
AutoRoute all nets
(hand-route any unrouted “overflows”)
Then: Add > Port Text to copy port names from schematic – for Calibre
Layout design rule check (DRC)
Technology-specific design rules specify
minimum sizes, spacing, etc. of features
to ensure reliable fabrication
– Design rules file specified at startup
Ex. tsmc035.rules
From main palette, select ICrules
– Click Check and then OK in prompt box
(can optionally select a specific area to check)
– Rules checked in numeric order
Common errors detected by DRC
To fix, click on First in palette to highlight first
error
– Error is highlighted in the layout
– Click View to zoom in to the error (see next)
– Example: DRC9_2: Metal2 spacing = 3L
– Fix by drawing a rectangle of metal2 to fill in the gap
between contacts that should be connected
Click Next to go to next error, until all are fixed
Draw
rectangle
of metal2
to fill gap
Layout vs schematic check
Calibre Interactive LVS
From ICstation menu: Calibre > Run LVS
– In popup, Calibre location: $MGC_HOME/../Calibre
– Rules: $ADK/technology/ic/process/tsmc035.calibre.rules
– Input: count4.src.net (previously created in DA-IC)
– H-cells: $ADK/technology/adk.hcell (hierarchical cells)
– Extracted file: count4.lay.net
Compares extracted transistor-level netlist vs.
netlist saved in DA-IC
Post-layout parameter extraction
Calibre Interactive PEX
Extract Spice netlist, including parasitic RC
– Simulate in Eldo or MachTA
ICstation menu: Calibre>Run PEX
– Options similar to Calibre LVS
– Extraction options:
lumped C + coupling cap’s
distributed RC
distributed RC + coupling cap’s
– Output file: count4.pex.netlist
Post-layout simulation with MachTA
MachTA is an accelerated Spice simulator
– Digital & mixed-signal circuits
– Analyze timing effects pre- and post-layout
SPICE netlists with parasitic R/C
– Execute test vector file to verify functionality
Algorithms support large designs
– Partition design, simulate only partitions with changes
– Combine time-driven & event-driven operation
– Solves linearized models using a proprietary high-
performance, graph-theory based, matrix solution
algorithm
Mach TA flow diagram
SPICE
netlist
$ADK/technology/mta/tsmc035
Prepare Calibre-extracted netlist for
Mach TA (file.pex.netlist)
In file.pex.netlist, insert model definitions and VDD/GND
voltage source functions after comment header:
* File: m7.pex.netlist
* Created: Thu Nov 15 15:25:56 2007
* Program "Calibre xRC"
* Version "v2005.2_9.14"
.model n nmos
.model p pmos
Vvdd VDD 0 5
Vgnd GND 0 0
Delete (or comment out with * in 1st column) .subcircuit
statement and any continuation lines (for long statement):
*.subckt modulo7 CLK Q[1] CLEARBAR I[1] Q[0] I[0] Q[2]
*+ L_CBAR I[2] GND VDD
Change .ends to .END near end of file
Post-layout simulation with Mach TA
Invoke Mach TA:
ana - command file to initialize Anacad SW
mta –ezw –t $ADK/technology/mta/tsmc035 count4.sp
Transistor calibration files for this technology
Generate waveform database & display in EZwave
Netlist, modified as
on previous slide
Other options:
-do file (execute commands from file.do – instead of design.spdo
-donot (run without simulating – compile only)
-b (run in batch mode – no GUI – output to console)
Sample Mach TA “dofile”
(transient analysis)
Signals to observe in EZwave
plot v(clk) v(q[2]) v(q[1]) v(q[0])
measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v
l load
l reset
h count
Measure time from rising edge of clk (TRIGger)
l clk to 1st rising edge of q[0] (TARGet) - voltages
run 5 ns
h reset
h clk Drive signals low/high (Lsim format)
run 5 ns
l clk
run 5 ns Simulate for 5 ns
h clk
run 5 ns
Double-click
signal name
to display.
Alternative Mach TA “dofile”
(same result as previous example)
plot v(clk) v(q[2]) v(q[1]) v(q[0])
measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0])
VAL=2.5v
vpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n 20n)
v-levels delay rise fall width period
l load
l reset Nodes to which
h count source connected
Periodic pulses
run 5 ns
Voltage source name
h reset
run 200 ns
Mach TA – test vector file
Verify design functionality/behavior
– apply test vectors
– capture outputs
– compare outputs to expected result
– vectors/outputs from behavioral simulation
Command to execute a test vector file:
run –tvend tvfile.tv
Xilinx “ISE”
Altera “Max Plus 2” Map to FPGA
LUTs, FFs, IOBs
FPGA/PLD
User-Specified Technology
Place & Route Files
Constraints
Generate
Generate
Programming
Timing Model
Data
Memory
PowerPC
Peripherals