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8086 Microprocessor Architecture
8086 Microprocessor Architecture
MICROPROCESSOR
By
A. Sanyasi Rao
Assoc. Prof
BIES, NSPT
1
Features
It is a 16-bit p.
8086 has a 20 bit address bus can access up to 220
memory locations (1 MB).
It can support up to 64K I/O ports.
It provides 14, 16 -bit registers.
Word size is 16 bits and double word size is 4 bytes.
It has multiplexed address and data bus AD0- AD15
and A16 A19.
It requires single phase clock with 33% duty cycle to
provide internal timing.
2
EXECUTION UNIT
Decodes instructions fetched by the BIU
Generate control signals,
Executes instructions.
The main parts are:
Control Circuitry
Instruction decoder
ALU
7
8 bits
AH
AL
BH
BL
CH
CL
DH
DL
AX
BX
CX
DX
SP
Pointer
BP
SI
Index
DI
Accumulator
Base
Count
Data
Stack Pointer
Base Pointer
Source Index
Destination Index
8
Register
Purpose
AX
AL
AH
BX
CX
CL
DX
10
Over flow
OF DF IF
Direction
U - Unused
TF SF ZF U
Interrupt Trap
Sign
AF U
PF U
Auxiliary
Zero
Parity
CF
Carry
12
Purpose
Carry (CF)
Parity (PF)
Auxiliary (AF) Holds the carry (half carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF)
Sign (SF)
Flag
Purpose
Trap (TF)
A control flag.
Enables the trapping through an on-chip debugging
feature.
Interrupt (IF)
A control flag.
Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
Direction (DF)
A control flag.
It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow (OF)
16
Data
Opcode
Opcode queue
Is it
Single
byte?
No
Take 2nd byte from Q as
opcode, decode 2nd byte
opcode
Execute it with data bytes
decoded by the decoder
19
Segmented Memory
The memory in an 8086/88
based system is organized as
segmented memory.
Physical Memory
00000
1 MB
FFFFF
20
Segment registers
In 8086/88 the processors have 4 segments
registers
Code Segment register (CS), Data Segment
register (DS), Extra Segment register (ES) and
Stack Segment (SS) register.
All are 16 bit registers.
Each of the Segment registers store the upper 16
bit address of the starting address of the
corresponding segments.
23
24
MEMORY
00000
BIU
Segment Registers
CSR
ESR
SSR
44EB
54EB
695E
44B9F
44EB0
54EAF
54EB0
CODE (64k)
DATA (64K)
1 MB
DSR
34BA
34BA0
EXTRA (64K)
64EAF
695E0
STACK (64K)
795D
F
25
27
34BA
IP
8AB4
Code segment
34BA0
8AB4 (offset)
3D645
34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F
28
Required Address
0001
0000
BIU
AX
AH
AL
BX
BH
BL
CX
CH
CL
DX
DH
DL
SP
BP
SI
IP
D
E
C
O
D
E
R
Fetch &
store code
bytes in
C
O PIPELINE C
D PIPELINE
(or)
E
O QUEUE
U
T
O
D
E
I
N
CS
DS
ES
SS
IP
BX
DI
DI
SP
BP
SI
DI
FLAGS
ALU
Timing
control
Default Assignment
31