Professional Documents
Culture Documents
Advanced MOS and Bipolar Logic Circuits: Microelectronic Circuits, Sixth Edition
Advanced MOS and Bipolar Logic Circuits: Microelectronic Circuits, Sixth Edition
Sedra/Smith
Figure 15.1 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load (or saturated-load) NMOS inverter.
(c) The depletion-load NMOS inverter.
Sedra/Smith
These 2 parameters
approach zero for
conventional CMOS
inverter.
Figure 15.2 Graphical construction to determine the VTC of the inverter in Fig. 15.1(a).
Since kp is r times smaller than kn, tPLH will be r times larger than
tPHL. Thus the circuit exhibits an asymmetrical delay performance.
10
Figure 15.7 A basic design requirement of PTL circuits is that every node have, at all times, a low resistance
path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in
(b) through switch S2.
11
The high output voltage (VOH) will not be equal to VDD; rather, it will be
lower by Vt, and to make matters worse, the value of Vt can be as high
as 1.5 to 2 times Vto (due to body effect).
For static consideration, the low value of VOH can cause the Qp of the
next CMOS inverter stage to conduct and thus has a finite static current
and static power dissipation.
Figure 15.8
12
13
14
Figure 15.11 The CMOS transmission gate and its circuit symbol.
Sedra/Smith
14.12 Operation of the transmission gate as a switch in PTL circuits with (a) vI high and (b) vI low.
Figure 15.12
Sedra/Smith
18
Sedra/Smith
Figure 15.14 (a) A transmission gate connects the output of a CMOS inverter to the input of another. (b) Equivalent circuit for the purpose
of analyzing the
Microelectronic Circuits, Sixth Edition
Sedra/Smith
2 to 1 Multiplexer Using
Pass-Transistor Logic (1)
A multiplexer (MUX) is a digital switches which connects data from
one of n sources to the output. A number of select inputs determine
which data source is connected to the output.
22
2 to 1 Multiplexer Using
Pass-Transistor Logic (2)
The symbol and truth table for the 2-to-1 MUX is shown below. The
circuit realizes it through pass-transistor logic is also presented.
23
12 transistors
24
Figure 15.18 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is
therefore known as complementary pass-transistor logic, or CPL. Note that both the output function and its complement are generated.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
27
Figure 15.19 (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit.
28
Sedra/Smith
reversed-biased junction
leakage current
30
Increased static
power dissipation
Increased circuit
complexity
Figure 15.21 (a) Charge sharing. (b) Adding a permanently turned-on transistor QL solves the charge sharing problem at the
expense of static power dissipation.
31
32
Figure E 15.10
Sedra/Smith
Figure 15.23 The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the
output. During evaluation, Y either will remain low (at 0 V) or will make one 0-to-1 transition (to VDD).
34
35
Figure 15.25 The basic element of ECL is the differential pair. Here, VR is a reference voltage.
36
37
38
Figure E15.12
Sedra/Smith
40
Sedra/Smith
42
Figure 15.27 The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the
two gates eliminates the ringing that would otherwise corrupt the logic signals. (See Section 15.4.6.)
43
Figure 15.28 Simplified version of the ECL gate for the purpose of finding transfer characteristics.
Sedra/Smith
45
15.28
Figure 15.31
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Figure 15.31
47
Figure 15.32
48
50
Figure 15.33 Equivalent circuit for determining the temperature coefficient of the reference voltage VR.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Figure 15.34 Equivalent circuit for determining the temperature coefficient of VOL
Sedra/Smith
Figure 15.35 Equivalent circuit for determining the temperature coefficient of VOH.
Sedra/Smith
54
Figure 15.37 Development of the BiCMOS inverter circuit. (a) The basic concept is to use an additional bipolar transistor to increase the output
current drive of each of QN and QP of the CMOS inverter. (b) The circuit in (a) can be thought of as utilizing these composite devices.
(c) To reduce the turn-off times of Q1 and Q2, bleeder resistors R1 and R2 are added. (d) Implementation of the circuit in (c) using NMOS
transistors to realize the resistors. (e) An improved version of the circuit in (c) obtained by connecting the lower end of R1 to the output node.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Figure 15.38 Equivalent circuits for charging and discharging a load capacitance C. Note that C includes all the capacitances
present at the output node.
Sedra/Smith
Sedra/Smith