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ADC Input Noise The Good, The Bad, and The Ugly. Is No Noise Good Noise
ADC Input Noise The Good, The Bad, and The Ugly. Is No Noise Good Noise
NUMBER OF
OCCURRENCES
STANDARD DEVIATION
= RMS NOISE (LSBs)
Practical ADCs deviate from ideal ADCs in many ways. Inputreferred noise is certainly a departure from the ideal, and its
effect on the overall ADC transfer function is shown in Figure 1.
As the analog input voltage is increased, the ideal ADC (shown
in Figure 1a) maintains a constant output code until a transition
region is reached, at which point it instantly jumps to the next
value, remaining there until the next transition region is reached.
A theoretically perfect ADC has zero code-transition noise, and a
transition region width equal to zero. A practical ADC has a
certain amount of code transition noise, and therefore a finite
transition region width. Figure 1b shows a situation where
the width of the code transition noise is approximately one
least-significant bit (LSB) peak-to-peak.
(a) IDEAL ADC
DIGITAL
OUTPUT
ANALOG
INPUT
n4 n3 n2 n1
n
n+1 n+2 n+3 n+4
OUTPUT CODE
Figure 2. Effect of input-referred noise on ADC groundedinput histogram for an ADC with a small amount of DNL.
Although the inherent differential nonlinearity (DNL) of the ADC
will cause deviations from an ideal Gaussian distribution (for
instance, some DNL is evident in Figure 2), it should be at least
approximately Gaussian. If there is significant DNL, the value
of should be calculated for several different dc input voltages
and the results averaged. If the code distribution is significantly
non-Gaussian, as exemplified by large and distinct peaks and
valleys, for instancethis could indicate either a poorly designed
ADC ormore likelya bad PC board layout, poor grounding
techniques, or improper power supply decoupling (see Figure 3).
Another indication of trouble is when the width of the distribution
changes drastically as the dc input is swept over the ADC input
voltage range.
NUMBER OF
OCCURRENCES
ANALOG
INPUT
n5 n4 n3 n2 n1
OUTPUT CODE
http://www.analog.com/analogdialogue
3 dB
Frequency
1.97 Hz
3.95 Hz
5.92 Hz
7.9 Hz
15.8 Hz
SF
Word
2048
1024
683
512
256
Settling Time
Normal Mode
460 ms
230 ms
153 ms
115 ms
57.5 ms
Settling Time
Fast Mode
60 ms
30 ms
20 ms
15 ms
7.5 ms
Input Range
= 80 mV
230k (18)
170k (17.5)
130k (17)
120k (17)
80k (16.5)
Input Range
= 40 mV
175k (17.5)
125k (17)
100k (16.5)
90k (16.5)
55k (16)
Input Range
= 20 mV
120k (17)
90k (16.5)
70k (16)
65k (16)
40k (15.5)
Input Range
= 10 mV
80k (16.5)
55k (16)
45k (15.5)
40k (15.5)
30k (15)
*Power-On Default
Noise-free counts =
2N
peak -to-peak input noise ( LSBs ) (1)
2N
Noise-free code resolution = log 2
(2)
peak -to-peak input noise ( LSBs )
2N
Effective resolution = log 2
rms
input
noise
(
LSBs
)
(3)
(5)
ENOB =
SINAD 1.76 dB
6.02
(6)
NOISE
GENERATOR
OUT-OF-BAND
FILTER
OUT-OF-BAND NOISE
NEAR DC OR fS/2
DVCC
A1
TH1
TH2
A2
ADC1
2.4V
AD6645
TH3
TH4
DAC1
DAC2
5
INTERNAL
TIMING
GND
ADC3
TH5
ADC2
5
ENCODE
ADC
BPF
25 = 32 ADC1 TRANSITIONS
ENCODE
RANDOM
NUMBER
GENERATOR
VREF
ADDER
DAC
AIN
ADC
NOISE
GENERATOR
AIN
INPUT
+
ADC
AVCC
(b)
LARGE AMPLITUDE
DMID
OVR
DRY
D13
(MSB)
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
The first plot shown in Figure 9 shows the undithered DNL over
a small portion of the input signal range, including two of the
subranging points, which are spaced 68.75 mV (512 LSBs) apart.
The second plot shows the DNL after adding (and later filtering
out) 155 LSBs of rms dither. This amount of dither corresponds
to approximately 20.6 dBm. Note the dramatic improvement in
the DNL.
25 = 32 ADC1 TRANSITIONS
OUTPUT CODE
68.75mV
29 =
512 LSBs
ANALOG INPUT
UNDITHERED
1.5
1.5
512 LSBs
512 LSBs
1.0
DNL (LSBs)
DNL (LSBs)
1.0
0.5
0.5
0.5
0.5
OUTPUT CODE
OUTPUT CODE
0
10
20
20
30
40
40
SFDR =
92dBFS
SFDR =
108dBFS
50
dBFS
50
dBFS
10
30
60
70
80
60
DITHER SIGNAL
70
80
90
90
100
100
110
120
0
10
15
20
25
FREQUENCY (MHz)
30
35
40
130
110
120
130
WITH DITHER
1,048,576-POINT FFTs,
PROCESS GAIN = 60dB
10
15
20
25
FREQUENCY (MHz)
30
35
40
Figure 10. FFT plots showing AD6645 SFDR, without and with the use of dither.
NO DITHER
25
25
SFDR = 125dBFS
50
50
75
75
5
100
dBFS
dBFS
SFDR = 100dBFS
100
125
125
150
150
175
175
200
10
15
20
25
FREQUENCY (MHz)
30
35
40
200
10
15
20
25
FREQUENCY (MHz)
30
35
40
Figure 11. AD9444, a 14-bit, 80-MSPS ADC; fS = 80 MSPS, fIN = 30.5 MHz, signal amplitude = 40 dBFS.
and the AD9446 (16 bits at 80 MSPS/100 MSPS) 5. These
ADCs have very high SFDR (typically greater than 90 dBc
for a 70-MHz, full-scale input signal) and low DNL. Still, the
addition of an appropriate out-of-band dither signal can improve
the SFDR under certain input signal conditions.
ACKNOWLEDGEMENTS
SUMMARY
FURTHER READING