Dr.

NGP Institute of Technology

Coimbatore 48
QUESTION PAPER FOR MODEL TEST- I

DEPARTMENT OF CSE & IT

Semester & Branch: II & Common to CSE & IT

Date / Session: .04.15/AN

Subject: DPSD

Max. Marks: 100 Marks

Subject code: CS6201

Max. Time: 3 hrs

ANSWER ALL THE QUESTIONS
PART A

(10 x 2 = 20)

1. State and Prove Consensus Theorem.

2. Reduce A'B'C' + A'BC' + ABC.
3. Implement the function G=(0,3) using 2*4 decoder.
4. Write the Excitation table and equation of JK and T flip flop.
5. Write any four applications of shift register.
6. A shift register comprises of JK flip-flops. How will you complement the contents of the register?
7. Define race condition.
8. Define ASIC and List the types of Hazards.
9. What is memory decoding?
10. What is meant by static and dynamic memories?
PART B

(5 x 16 = 80)

11. (a) Simplify the following functions using K-map technique.

G=M (0, 1, 3, 7, 9, 11)

(8)

F(W,X,Y,Z)= m ( 0, 7, 8, 9, 10, 12) + d ( 2, 5, 13).

(8)

(OR)
(b) Minimize the expression using Quine Mc Cluskey method

(16)

F= m ( 0, 1, 9, 15, 24, 29, 30) + d ( 8, 11, 31).

12. (a) Design the circuit that converts 8421 BCD code to Excess -3 code.
(OR)
(b) Implement the following Boolean function using 8 to 1 Multiplexer
F(A,B,C,D) = ABD + ACD + BCD + ACD and also implement the function
Using 16 to 1 Multiplexer.

(16)

Dr.NGP Institute of Technology

Coimbatore 48
QUESTION PAPER FOR MODEL TEST- I
13. (a) Implement T flip flop using D flip flop and JK flip flop using D flip flop.

(16)

(OR)
(b) Design synchronous counter which counts in the sequence 000, 001, 010, 011, 100

(16)

101, 110, 111, 000 using D flip flop.

14. (a) Design an asynchronous sequential circuit with inputs xl and x2 and one

output z.

(16)

Initially and at any time if both the inputs are 0, output is equal to 0.
When xl or x2
becomes 1, z becomes 1. When second input also becomes 1, z = 0;
The output stays
at 0 until circuit goes back to initial state.
(OR)
(b) Implement the switching function F= m (1, 3, 5, 7, 8, 9, 14, 15) by a static hazard

(16)

free two level AND OR gate network.

15. (a) Implement the following function using PLA

(16)

A(x, y, z) = (1, 2, 4, 6)
B(x, y, z) = (0, 1, 6, 7)
C(x, y, z) = (2, 6).
(OR)
(b) The following messages have been coded in a even parity Hamming code and
transmitted through a noisy channel. Decode the messages, assuming that at most
a single error has occurred in each code word.
(i) 1001001
(ii) 0111001
(iii) 1110110
(iv) 0011011.

(16)

Dr.NGP Institute of Technology

Coimbatore 48
QUESTION PAPER FOR MODEL TEST- I

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