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Simulation Lab 3 Introduction To VHDL - Simple VHDL Project: Science Foundation (NSF)
Simulation Lab 3 Introduction To VHDL - Simple VHDL Project: Science Foundation (NSF)
National
Science
Foundation
Funded in part, by a grant from the
National Science Foundation
DUE 1003736 and 1068182
Acknowledgements
Developed by Craig Kief, Alonzo Vera, and Alexandria Haddad, at the Configurable Space Microsystems
Innovations & Applications Center (COSMIAC). Based on original tutorial developed by Bassam Matar,
Engineering Faculty at Chandler-Gilbert Community College, Chandler, Arizona. Funded by the National
Science Foundation (NSF).
Introduction
These labs will be using what is known as a Field Programmable Gate Array (FPGA). The FPGA will be on
a Digilent Nexys 3 board. FPGAs are different than traditional integrated circuits, because interconnects
between the gates are programmable, which means the hardware itself is configurable.
Lab Summary
This lab will be an introduction to design techniques for FPGAs using a hardware descriptive language
(VHDL) design. Xilinx ISE 14.x is the design tool provided by Xilinx for this purpose. Xilinx makes a free
version of this tool called Webpack which would be virtually identical for this purpose. The board is a
Digilent Nexys 3 board with a Xilinix Spartan 6 XC6LX16-CS324 chip. Please avoid putting your fingers
on the chips, as they are extremely electrostatic discharge sensitive.
Lab Goals
Using the Design process discussed in Lab 1, we will:
1. Learn about logic gates, symbols, and their respective truth tables.
2. Implement a small logic circuit using VHDL
Learning Objectives
Understand the basics of digital logic and design. We will accomplish this through the implementation of a
small circuit in an FPGA. The circuit will be designed in such a way that only specific combinations of
switches will turn on a light emitting diode (LED) on the board.
Grading Criteria
Your grade is determined by your instructor.
Time Required
4 - 5 hours
Special Safety Requirements
When working with electronic components, such as the Xilinx FPGA board, there is potential of
Electrostatic Discharge (ESD) hazards. Static electricity can damage the FPGA devices used in this lab.
Use appropriate ESD methods to protect the devices. No serious hazards are involved in this laboratory
experiment, but be careful to connect the components with the proper polarity to avoid damage.
Lab Preparation
Review Lab 1 Introduction to Xilinx previous lab.
Supplies
1. ISE Design Suite (or WebPACK ) software from the Xilinx website,
www.xilinx.com, if you dont already have it installed. Your classroom should have a
full working version of Xilinx ISE Design Suite.
In this lab, you download and install Digilent Adept which allows you to communicate with the Digilent
FPGA boards that we use in lab. If Adept is already installed on your system, you can skip this Lab
Procedure.
Step 1:
Navigate your browser to http://www.digilentinc.com/Products/Detail.cfm?Prod=ADEPT2.
Step 2:
Click the Download button for Adept 2.9.4 System, 32/64-bit Windows (or latest version) and click Save
file when prompted. The installation .exe file will download to your computer.
Step 3:
When the download is complete, run the .exe file and install Adept onto your computer.
User I/O
The Nexys-3 board includes several input and output devices, and data ports allowing many implementation
designs without the need for any other components. We will focus on the following inputs [slide switches,
push buttons, and reset button] and outputs [LEDs, and 7-segment display].
The five pushbuttons and eight slide switches are provided for circuit inputs. There is also a reset button.
Pushbuttons normally generate a low output when at rest, driven high when the pushbutton is pressed. Slide
switches generate constant high or low inputs depending on their position. Pushbutton and slide switch
inputs use a series resistor for protection against short circuits (a short circuit would occur if an FPGA pin
assigned to a pushbutton or slide switch was inadvertently defined as an output). Figure 4 shows the pin
assignments for each of the aforementioned inputs/outputs. Please refer the reference manual for any
additional information.
There are two design sections for this lab. The first is the VHDL program design, which involves writing the
code telling the hardware what we want it to do. We are implementing the circuit. The second step is the
testbench simulation. As its name implies, this is the testing of our code using a simulation program
provided with ISE Design Suite. We will driving the inputs and observe the outputs to verify the design
works as expected. We are using ISE Design Suite 14.x. ISE has the capability of implementing a variety
of different design methodologies including: Schematic Capture, Finite State Machines, and Hardware
Descriptive Language (VHDL or Verilog). ISE also provides its own simulation tool to test your designs
before programming them on the FPGA.
The AND gate is used to find if both input values are high (one). If the statement is true the gate will output
a one and if false (one input being low) it will output a low (zero). An OR gate is used to see if either of the
inputs are high and then will output a high if true and a low if false. The NOT gate is used to directly invert
the input. If the input is high then the output will be low and vice versa. In normal digital logic, a high is a
positive voltage and the low is ground.
NOTE:
The options specified are for the Spartan 6 LX FPGA. Your board might be different than
the board used for these instructions. Chip specifications are printed on the FPGA chip in the
middle of the board. The board information is also listed on the box it came in.
5. Verify the file type and name are correct
in the Project Summary then click
Finish to complete the New Project
creation process.
NOTE: You will add them to the project. Copy the source files into the LAB3 project folder that ISE
created. There are three files for this project: Tut1Source.vhd (the source file, tut1_tb.vhd (the
testbench) and tut1.ucf (the pin assignments). When naming testbenches, it is common practice to
add the _tb to the file name.
NOTE: For this project, we have already
created the source files for you. There
are three main files associated with this
tutorial. The project files are in the
lab3.zip file. If you dont have the zip
file you can download it from the
COSMIAC website
(http://cosmiac.org/Projects_FPGA.html
).
We will be adding the files from the
lab3.zip file to our new project.
1. Using Windows Explorer, extract or
move these three files to your project
folder.
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VHDL is portable.
g.
VHDL allows modeling and simulation of a system before expensive hardware is created.
h.
VHDL is NOT case sensitive, i.e. CLK is the same as clk, which is the same as Clk.
i.
Semicolons are used to end VHDL statements; very much like in C or C++.
j.
Comments, proceeded by two hyphens (--), are good, should be used often, and will be
helpful to your replacement in case you die.
k.
Assignment operators are different in VHDL than in other languages (Pedroni 47):
<= is used to assign a value to a signal
:=
assigns a value to a variable
=> assigns values to individual vector elements or OTHERS
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NOTE: The VHD file is used to describe the behavior of the hardware. The third file used in this project is
the tut1.ucf file. The UCF stands for user constraint file. The UCF file ties the VHDL code inputs
and outputs to the boards inputs and outputs, using pin assignments. There are many more things
that a UCF file can be used for but they are beyond the scope of this tutorial.
The first line ties input A to pin T10 on the FPGA board, which is the Pin assignment for switch 0 on
the FPGA board (see Figure 4). NET identifies a signal input or output. LOC identifies a pin
number on the FPGA and the green text is comments.
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NOTE: If you have errors or warnings you will need to find and fix the errors. You may or may not need
to fix warnings. Click the Errors (and/or Warnings) Panel tab to display a list of all errors (and/or
warnings) (1).
Clicking the hyperlink (2) of a particular Error (or Warning) will take you to the file and line (3) of
the Error (or Warning). Note in the example the semicolon is missing at the end of line 37.
Clicking the hyperlink word Error (4) (or Warning) will display context sensitive information about
the particular error/warning.
After fixing any errors, re-generate the programming file. To re-generate the programming file,
right-click on Generate Programming File and select Rerun All.
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are working with use a single USB cable for power and PC connection we need to use Digilent Adept to
transfer the .bit code to the board.
1
Open Digilent Adept by selecting Start All Programs Digilent Adept Adept.
NOTE: Your system might have slightly different Start Menu options.
17. Choose Nexys3 from the Connect Product drop down menu.
NOTE: If you do not see Nexys3 as an option, check the USB connection to ensure the board is connected
to the computer.
18. Click the Browse button. The Open dialog box displays.
19. Navigate to the folder of the Full_Adder project and select the full_adder.bit file.
20. Click the Open button. The file is displayed in the dropdown list next to the FPGA icon.
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21. Click the Program button. The bit file is programmed to the FPGA board. The green status bar at the
bottom of the Adept screen displays the status as the chip is programmed.
22. The program gets downloaded to the FPGA board.
23. Test the FPGA by sliding the programmed switches ON (up toward the middle of the board) and OFF
(down toward the edge of the board). The LED0 should light according to the truth table.
SW(0) (A)
T10
SW(1) (B)
T9
SW(2) (C)
V9
Off
Off
Off
On
On
On
On
On
Off
Off
Off
On
Off
Off
Off
On
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SW(3) (D)
M8
LD0 (Y)
U16
VHDL Code
-- VHDL files contain three parts: library declarations, entity and behavior.
-------------------------------------------------------------------------------- The library describes what each function will do.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------- Entity describes the inputs and outputs. This is the declaration of the
-- module's inputs and outputs for part 1 of tutorial 2
entity tut1 is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
D: in std_logic;
Y: out std_logic
);
end tut1;
-------------------------------------------------------------------------------- Behavior is the working portion of the project; defines the module's behavior
Architecture behavioral of tut1 is
begin
process (A,B,C,D) begin
Y <= (NOT(A) AND B) OR (C AND D);
end process;
end behavioral;
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VHDL Testbench
-- This is a VHDL testbench. It is used to stimulate the inputs to
-- file we are testing. A good design practice is to create a testbench
-- for each component you are developing. Test each component separately
-- before combining them.
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE testbench_arch OF testbench IS
COMPONENT tut1
PORT (
A
: in std_logic;
B
: in std_logic;
C
: in std_logic;
D
: in std_logic;
Y
: out std_logic
);
END COMPONENT;
-- develop signals to stimulate
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL C : std_logic := '0';
SIGNAL D : std_logic := '0';
SIGNAL Y : std_logic := '0';
-- UUT means unit under test
BEGIN
UUT : tut1
-- map signals on right to entitys on the left
PORT MAP (
A => A,
B => B,
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C => C,
D => D,
Y => Y
);
signal_A: process
begin
A <= NOT A;
wait for 1 ns;
end process;
signal_B: process
begin
B <= NOT B;
wait for 2 ns;
end process;
signal_C: process
begin
C <= NOT C;
wait for 4 ns;
end process;
signal_D: process
begin
D <= NOT D;
wait for 8 ns;
end process;
END testbench_arch;
User Constraints File (UCF)
# The pin assignments in this file are for the
# Nexys 3, Spartan 6 C6LS16-CS324. If you are
# using a different board, change the LOC = pin
# assignment as appropriate
NET "A" LOC = "T10"; #SW0
NET "B" LOC = "T9";
#SW1
NET "C" LOC = "V9";
#SW2
NET "D" LOC = "M8";
#SW3
NET "Y" LOC = "U16"; #LED0
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