Vi Xu Ly PIC16F887 NguyenDinhPhu PDF

PIC16F887_VXL_00_0_bia.
pdf
PIC16F887_VXL_01_LOINOIDAU.pdf
PIC16F887_VXL_003_MUCLUC.pdf
PIC16F887_VXL_CHAPTER_01_VDK_CAUTRUC_CHUCNANG_CHAN.pdf
PIC16F887_VXL_CHAPTER_02_VDK_BONHO_THANHGHI.pdf
PIC16F887_VXL_CHAPTER_03_VDK_LENH_ASSEMBLY.pdf
PIC16F887_VXL_CHAPTER_04_VDK_LENH_C.pdf
PIC16F887_VXL_CHAPTER_05_VDK_PORT.pdf
PIC16F887_VXL_CHAPTER_06_VDK_TIMER_COUNTER.pdf
PIC16F887_VXL_CHAPTER_07_VDK_GIAOTIEP_ADC.pdf
PIC16F887_VXL_CHAPTER_08_VDK_INTERRUPT.pdf
PIC16F887_VXL_CHAPTER_09_VDK_TRUYENDULIEU.pdf
PIC16F887_VXL_CHAPTER_10_VDK_PWM.pdf
I HC S PHM K THUT
KHOA IN IN T B MN IN T CNG NGHIP
GIO TRNH VI X L
NGUYN NH PH
NM 2014
LI NOI AU
Bo vi x ly ngay cang phat trien hoan thien va c s dung hau het trong cac he thong
ieu khien trong cong nghiep cung nh trong cac thiet b ien t dan dung. Chnh nh vai tro, chc
nang cua vi x ly a em lai nhieu u iem, nhieu tnh nang ac biet cho cac he thong ieu khien.
Cac nha nghien cu khong ngng nghien cu cac he thong ieu khien va s dung vi x ly e
thay the nham nang cao kha nang t ong thay the cho con ngi, va cung chnh v the a thuc
ay lnh vc vi x ly ngay cang phat trien khong ngng, thch nghi vi yeu cau ieu khien. e n gian
bt s phc tap cua phan cng khi dung vi x ly nen cac nha nghien cu a tch hp he vi x ly, bo
nh, cac ngoai vi thanh mot vi mach duy nhat goi la vi ieu khien.
Noi dung giao trnh nay nghien cu cac kien thc c ban cua vi ieu khien . Do co nhieu ho vi ieu
khien khac nhau, t he 8 bit cho en he 32 bit, mc o tch hp t n gian en phc tap, nhieu
hang che tao khac nhau, nhieu chung loai khac nhau se lam cho ngi bat au hoc hay nghien cu se
gap nhieu b ng khong biet bat au t he nao cho phu hp, chnh v the giao trnh nay ch trnh
bay ho vi ieu khien 8 bit cua hang Microchip nham giup cac ban sinh vien nganh ien noi chung co mot
giao trnh e hoc tap va nghien cu mot cach de dang.
Cac ng dung dung vi ieu khien nhieu cap o khac nhau t n gian en phc tap, giao trnh
nay ch trnh bay cac ng dung n gian e cac ban co the oc hieu, t cac kien thc c ban o
ban co the thc hien cac ng dung ieu khien phc tap hn, phan bai tap kem theo giup ban giai
quyet cac yeu cau phc tap. T cac kien thc c ban cua vi ieu khien 8 bit co the giup cac ban t
nghien cu cac vi ieu khien nhieu bit hn nh 16 bit, 32 bit.
Giao trnh bien soan chia thanh 10 chng, chu yeu trnh bay vi ieu khien PIC 16F887:
Chng 1. ac tnh, cau truc, chc nang cac port.
Chng 2. To chc bo nh, thanh ghi.
Chng 3. Lenh hp ng.
Chng 4. Ngon ng lap trnh C.
Chng 5. Giao tiep LED, LCD, phm n, ma tran phm.
Chng 6. Timer - Counter.
Chng 7. Chuyen oi tn hieu tng t sang so .
Chng 8. Ngat.
Chng 9. Truyen d lieu UART.
Chng 10. ieu che o rong xung - PWM.
Noi dung chng 1 chu yeu gii thieu ac tnh, cau truc va chc nang cac port cua vi ieu khien,
ngi oc can phai biet ac tnh cua vi ieu khien ang nghien cu . e so sanh kha nang cua cac vi
ieu khien khac nhau ta phai da vao ac tnh. Phan cau truc ben trong cho ban biet c to chc,
moi quan he gia cac khoi vi nhau, chc nang cua tng khoi . Ban phai biet ten, ky hieu at ten cho
tng port, chc nang cua tng port e giup ban s dung port ket noi ung vi cac oi tng ieu
khien.
Noi dung chng 2 gii thieu cau truc to chc cac loai bo nh tch hp ben trong vi ieu khien
bao gom bo nh chng trnh, bo nh d lieu RAM, bo nh ngan xep, bo nh Eeprom, cac cach truy
xuat bo nh.
Noi dung chng 3 gii thieu ve tap lenh hp ng cua vi ieu khien e viet cac chng trnh
bang hp ng nhng do lap trnh bang hp ng rat kho va dai khi giai quyet cac yeu cau tnh toan
phc tap nen phan nay ch gii thieu ch khong nghien cu sau.
Noi dung chng 4 gii thieu ve ngon ng lap trnh C cho vi ieu khien PIC, co nhieu trnh bien
dch ngon ng lap trnh C cho vi ieu khien nhng tai lieu nay trnh bay trnh bien dch CCS. Lap trnh
bang ngon ng C giup cac ban viet chng trnh de hn so vi hp ng, toan bo cac chng trnh
trong tai lieu nay eu viet bang ngon ng lap trnh C. e hieu cac chng trnh trong giao trnh va
viet cac chng trnh theo yeu cau th ban can phai nam ro to chc cua moat chng trnh C, cac
kieu d lieu, cac toan t, cac th vien viet san va cac lenh C c ban.
Noi dung chng 5 khao sat chi tiet chc nang cac port, s o mach cua cac port, s dung
cac port e xuat nhap tn hieu ieu khien nh led n, led 7 oan trc tiep, led 7 oan quet, LCD,
nut nhan, ban phm ma tran. Trong tng yeu cau se cho ban biet cach ket noi phan cng, nguyen ly
hoat ong, viet lu o hay trnh t ieu khien va chng trnh mau, co giai thch tng lenh hoac ca
chng trnh.
Noi dung chng 6 khao sat chi tiet chc nang cua timer-counter tch hp trong vi ieu khien,
cach s dung timer counter e nh thi va em s kien.
Noi dung chng 7 khao sat chi tiet chc nang cua bo chuyen oi tn hieu tng t thanh tn
hieu so (ADC) tch hp trong vi ieu khien, cach s dung ADC e chuyen oi cac tn hieu tng t
nh cam bien nhiet e thc hien cac ng dung o nhiet o, canh bao qua nhiet o trong ieu khien
va nhieu ng dung khac.
Noi dung chng 8 khao sat chi tiet chc nang ngat cua vi ieu khien, biet c tnh nang u
viec cua ngat, cach s dung ngat e ap ng toi u cac yeu cau ieu khien nham ap ng nhanh cac
s kien xay ra.
Noi dung chng 9 khao sat chi tiet chc nang truyen d lieu noi tiep UART cua vi ieu khien,
biet c trnh t thc hien gi d lieu va nhan d lieu, thc hien cac yeu cau truyen d lieu gia vi
ieu khien vi may tnh va gia cac vi ieu khien vi nhau.
Noi dung chng 10 khao sat chi tiet chc nang ieu che o rong xung PWM cua vi ieu khien,
biet c nguyen ly hoat ong, tnh toan cac thong so cua xung ieu che, biet lap trnh s dung
chc nang PWM e ieu khien thay oi o sang cua en, thay oi toc o cua ong c DC va nhie u
ng dung khac.
Ngoai cac kien thc c ban ma tac gia a trnh bay th con nhieu chc nang khac cua vi ieu
khien ma tac gia cha trnh bay th cac ban co the tham khao them cac tai lieu nha che tao cung
cap.
Trong qua trnh bien soan khong the tranh c cac sai sot nen rat mong cac ban oc ong
gop xay dng va xin hay gi ve tac gia theo a ch phu_nd@yahoo.com.
Tac gia xin cam n cac ban be ong nghiep a ong gop nhieu y kien, xin cam n ngi than
trong gia nh cho phep tac gia co nhieu thi gian thc hien bien soan giao trnh nay.
Nguyen nh Phu.
MC LC
LI NI U
CHNG 1. C TNH, CU TRC, CHC NNG CC PORT
I.
GII THIU
II.
KHO ST VI IU KHIN MICROCHIP
1.
2.
3.
III.
Cu hnh ca vi iu khin PIC 16F887

S cu trc vi iu khin PIC 16F887
Kho st s chn vi iu khin PIC 16F887
CU HI N TP TRC NGHIM BI TP
1.
2.
3.
4.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
Bi tp
2
5
7
12
12
13
13
14
CHNG 2. T CHC B NH, THANH GHI

I.
GII THIU
15
II.
KIN TRC B NH
16
III.
T CHC B NH CA VI IU KHIN PIC 16F887
16
1.
2.
3.
4.
IV.
T chc b nh chng trnh

M lnh 14 bit
Kho st b nh d liu v thanh ghi trng thi
B nh d liu Eeprom
1.
2.
3.
4.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
Bi tp
17
17
18
20
20
20
20
20
22
CHNG 3. LNH HP NG
I.
GII THIU
24
II.
LNH HP NG CA VI IU KHIN PIC 16F887
24
1.
2.
3.
III.
Gii thiu
Kho st tp lnh tm tt vi iu khin PIC 16F887
Tp lnh chi tit
1.
2.
3.
4.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
Bi tp
24
25
26
31
31
31
32
33
CHNG 4. NGN NG LP TRNH C

I.
GII THIU
36
II.
CC THNH PHN C BN CA NGN NG C
36
1.
2.
3.
4.
5.
6.
7.
III.
Cc kiu d liu ca bin

Cc ton t
Cc lnh C c bn
Cu trc ca chng trnh C
Cc thanh phn c bn ca chng trnh C
Con tr d liu
Khai bo mng
TRNH BIN DCH CCS-C
36
36
39
41
41
42
42
42
i
IV.
1.
2.
3.
4.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
Bi tp
50
50
50
50
52
CHNG 5. GIAO TIP LED, LCD, PHM N, MA TRN PHM

I.
GII THIU
54
II.
CHC NNG CC PORT CA VI IU KHIN
54
III.
CC PORT CA PIC 16F887
54
1.
2.
3.
4.
5.
55
57
61
64
65
IV.
Port A v thanh ghi TrisA

Port B v thanh ghi TrisB
Port C v thanh ghi TrisC
Port D v thanh ghi TrisD
Port E v thanh ghi TrisE
LNH TRUY XUT PORT DNG NGN NG CCS-C

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
66
Lnh set_tris_x(value)
Lnh output_x(value)
Lnh output_high(pin)
Lnh output_low(pin)
Lnh output_toggle(pin)
Lnh output_bit(pin,value)
Lnh value = get_tris_x()
Lnh value = input(pin)
Lnh value = input_state()
66
66
67
67
67
67
67
67
68
Lnh value=input_x()
Lnh output_drive(pin)
Lnh output_float(pin)
Lnh port_b_pullup()
68
68
68
68
V.
CC NG DNG IU KHIN LED N
69
VI.
CC NG DNG IU KHIN LED 7 ON TRC TIP
72
VII. CC NG DNG IU KHIN LED 7 ON QUT
76
VIII. CC NG DNG GIAO TIP VI NT NHN, BN PHM
79
1.
2.
IX.
CC NG DNG IU KHIN LCD

1.
2.
3.
4.
5.
6.
X.
H thng t phm
H thng nhiu phm
Gii thiu LCD
S chn LCD
S mch giao tip vi iu khin vi LCD
Cc lnh iu khin LCD
a ch ca tng k t trn LCD
Cc chng trnh hin th trn LCD
CU HI N TP TRC NGHIM
1.
2.
3.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
79
86
93
93
93
94
95
96
96
100
100
100
100
CHNG 6. TIMER - COUNTER

I.
GII THIU
104
II.
KHO ST TIMER0 CA PIC 16F887
104
1.
2.
3.
III.
Ngt ca Timer0
Timer0 m xung ngoi
B chia trc
105
106
106
106
ii
1.
2.
3.
4.
5.
6.
7.
8.
IV.
111
B chia trc v chia sau ca Timer2

Ng ra ca TMR2
112
112
CC LNH CA TIMER COUNTER TRONG NGN NG CCS-C

1.
2.
3.
4.
5.
6.
7.
VI.
108
108
109
110
110
110
110
111

1.
2.
V.
Timer1 ch nh thi
Timer1 ch m xung ngoi
Hot ng ca Timer1 ch counter ng b
Hot ng ca Timer1 ch counter bt ng b
c v ghi Timer1 trong ch m khng ng b
B dao ng ca Timer1
Reset timer1 s dng ng ra CCP trigger
Reset cp thanh ghi TMR1H, TMR1L ca Timer1
Lnh setup_timer_0(mode)
Lnh set_timerx(value)
Lnh get_timerx()
Lnh setup_wdt(mode)
Lnh restart_wdt()
CC NG DNG NH THI DNG TIMER
112
112
113
113
116
116
116
117
117
VII. CC NG DN M XUNG NGOI DNG COUNTER
121
VIII. CU HI N TP TRC NGHIM
126
1.
2.
3.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
126
127
127
CHNG 7. CHUYN I TNG T SANG S

I.
GII THIU
130
II.
ADC CA VI IU KHIN PIC 16F887
130
1.
2.
3.
4.
III.
Kho st adc ca pic 16F887

Kho st cc thanh ghi ca PIC 16F887
Trnh t thc hin chuyn i ADC
La chn ngun xung cho chuyn i ADC
CC LNH CA ADC TRONG NGN NG CCS-C

1.
2.
3.
4.
Lnh setup_adc (mode)

Lnh setup_adc_port (value)
Lnh set_adc_channel (chan)
Lnh value = read_ adc (mode)
130
131
133
133
134
134
134
134
134
IV.
CC NG DNG ADC CA PIC 16F887
135
V.
140
4.
5.
6.
7.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
Bi tp
140
140
140
141
CHNG 8. NGT
I.
GII THIU
144
II.
TNG QUAN V NGT
144
III.
NGT CA VI IU KHIN PIC16F887
144
Cc ngun ngt ca PIC16F887

Cc thanh ghi ngt ca PIC16F887
144
145
1.
2.
IV.
CC LNH NGT CA PIC16F887 TRONG NGN NG CCS-C

1.
lnh enable_interrupt (level)
148
148
iii
2.
lnh disable_interrupt (level)
148
V.
CC NG DNG NGT CA PIC 16F887
148
VI.
157
1.
2.
3.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
157
157
157
CHNG 9. TRUYN D LIU UART

I.
GII THIU
160
II.
TNG QUAN V CC KIU TRUYN D LIU
160
III.
TRUYN D LIU NI TIP NG B V KHNG NG B
160
IV.
TRUYN D LIU CA VI IU KHIN PIC 16F887
161
1.
2.
V.
CC LNH TRUYN D LIU EUSART

1.
2.
3.
4.
VI.
Truyn d liu EUSART

Cc thanh ghi phc v cho khi ESUART ca PIC16F887
Lnh setup_uart(baud,stream)
Lnh puts(string)
Lnh value = getc(), value = fgetc(stream), value = getch()
Lnh value = kbhit()
NG DNG TRUYN D LIU EUSART
VII. CU HI N TP TRC NGHIM

1.
2.
3.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
161
161
168
168
169
169
169
169
175
176
176
176
CHNG 10. IU CH RNG XUNG

I.
GII THIU
178
II.
KHO ST PWM
178
1.
2.
3.
4.
III.
Nguyn l iu ch rng xung PWM

Cu trc khi iu ch rng xung PWM
Tnh chu k xung PWM
Tnh h s chu k PWM
CC LNH IU KHIN PWM

1.
2.
3.
4.
Lnh nh cu hnh khi ccp setup_ccp(mode)

Lnh thit lp h s chu k set_pmwx_duty(value)
Lnh nh cu hnh cho timer_2 setup_timer_2 (mode, period, pastscale)
Lnh thit lp gi tr bt u cho timer set_timerx(value)
178
179
180
180
180
180
180
181
181
IV.
CC CHNG TRNH NG DNG PWM
190
V.
190
1.
2.
3.
Cu hi n tp
Cu hi m rng
Cu hi trc nghim
Ti liu tham kho.
190
190
190
191
iv
HNH NH
Hnh 1-1: Cc thit b s dng vi x l.
Hnh 1-2: H thng vi x l.
Hnh 1-3: Cu hnh ca vi iu khin.
Hnh 1-4: Cu trc bn trong ca vi iu khin.
Hnh 1-5: S chn ca PIC 16F887.
2
2
5
6
7
Hnh 2-1: Kin trc Von Neumann v Harvard.

Hnh 2-2: S b nh chng trnh v ngn xp.
Hnh 2-3: T chc b nh theo byte.
Hnh 2-4: T chc b nh cha c m lnh v d liu.
Hnh 2-5: Thanh ghi trng thi.
Hnh 2-6: T chc File thanh ghi.
16
17
18
18
18
19
Hnh 3-1: Cc dng m lnh.
25
Hnh 5-1: S kt ni port vi i tng iu khin.

Hnh 5-2: S kt ni port: xut nhp tn hiu iu khin.
Hnh 5-3: PortA v thanh ghi nh hng port A.
Hnh 5-4: Cu hnh chn RA0.
Hnh 5-12: PortB v thanh ghi nh hng port B.
Hnh 5-13: Thanh ghi ANSELH nh cu hnh s tng t cho portB.
Hnh 5-14: Thanh ghi WPUB thit lp cho php/cm in tr treo.
Hnh 5-15: Thanh ghi IOCB cho php/cm ngt portB thay i.
Hnh 5-16: Cu hnh chn RB<3:0>.
Hnh 5-18: Cc chn PortB giao tip vi mch np, g ri.
Hnh 5-19: Port C v thanh ghi TRISC.
Hnh 5-20: Cu hnh chn RC0.
Hnh 5-28: Port D v thanh ghi TRISD.
Hnh 5-29: Cu hnh chn RD<4:0>.
Hnh 5-31: Port E v thanh ghi TRISE.
Hnh 5-32: Cu hnh chn RE<2:0>.
Hnh 5-33: Cu hnh chn RE<3>.
Hnh 5-34: S iu khin led n.
Hnh 5-35: Lu iu khin led n chp tt.
Hnh 5-36: Lu iu khin led n chp tt 10 ln.
Hnh 5-37: Lu iu khin led n sng dn tt dn t phi sang tri.
Hnh 5-38: S kt ni portB vi 1 led 7 on.
Hnh 5-39: Hnh led 7 on
Hnh 5-40: Lu m t 0 n 9.
Hnh 5-41: S kt ni portB, C iu khin 2 led 7 on.
54
54
55
55
55
56
56
57
57
57
57
58
58
58
58
60
61
61
62
62
62
63
63
63
63
64
64
65
65
65
65
66
66
69
69
70
71
72
72
73
75
Hnh 5-42: Lu m t 00 n 99.

Hnh 5-43: S kt ni 2 port B v D iu khin 8 led 7 on qut.
Hnh 5-44: Lu iu khin 8 led qut sng 8 s.
Hnh 5-46: Lu m t 00 n 99 hin th trn 2 led qut.
Hnh 5-47: S iu khin led v nt nhn.
Hnh 5-48: Lu iu khin led n bng nt nhn ON-OFF.
Hnh 5-49: S iu khin led v 3 nt nhn.
Hnh 5-50: Lu iu khin led bng 3 nt ON-OFF-INV.
Hnh 5-51: Lu iu khin led c chng di phm INV.
Hnh 5-52: S kt ni 2 port iu khin 2 led 7 on, 2 nt nhn.
Hnh 5-53: Lu m c iu khin bng nt nhn Start-Stop.
Hnh 5-54: Bn phm ma trn 44.
Hnh 5-55: Bn phm ma trn 44 vi ct C1 bng 0.
Hnh 5-58: Lu qut bn phm ma trn 44.
Hnh 5-59: Lu qut bn phm ma trn 44 c chng di.
Hnh 5-60: Vi iu khin giao tip bn phm ma trn.
Hnh 5-61: Lu qut hin th ma trn phm.
Hnh 5-62: Vi iu khin giao tip bn phm ma trn v 2 led 7 on.
Hnh 5-63: Lu qut ma trn phm v hin th m phm.
Hnh 5-64. Hnh nh ca LCD.
Hnh 5-65. Giao tip vi iu khin PIC16F887 vi LCD.
Hnh 5-66. Dng sng iu khin ca LCD.
Hnh 5-67: Lu hin th thng tin trn 2 hng.
Hnh 5-68: Lu hin th thng tin v m giy.
75
76
77
78
78
80
80
81
82
83
84
85
86
87
87
87
88
89
89
90
92
92
93
95
96
97
99
Hnh 6-1: S khi ca timer0 ca PIC16F887.

Hnh 6-2: Thanh ghi OPTION_REG.
Hnh 6-3: Thanh ghi INTCON.
Hnh 6-4: B chia trc c gn cho timer.
Hnh 6-5: B chia trc c gn cho WDT.
Hnh 6-6: Thanh ghi lu kt qu ca T1.
Hnh 6-7: Cu trc timer T1.
Hnh 6-8: Thanh ghi T1CON.
Hnh 6-9: Timer1 hot ng nh thi.
Hnh 6-10: T1 hot ng m xung ngoi t mch dao ng T1.
Hnh 6-11: T1 hot ng m xung ngoi a n ng vo T1CKI.
Hnh 6-12: Gin thi gian xung m ca Counter1.
Hnh 6-13: Kt ni thch anh to dao ng.
Hnh 6-14: S khi ca Timer2.
Hnh 6-15: PIC iu khin 8 led sng tt.
Hnh 6-16: Lu iu khin 8 led sng tt nh thi 210ms.
Hnh 6-17: Lu iu khin 8 led sng tt dng ngt nh thi 200ms.
Hnh 6-18: Lu iu khin 8 led sng tt nh thi 1s.
Hnh 6-19: Lu iu khin 8 led sng tt, nh thi 13,107ms dng T0.
Hnh 6-20: Lu iu khin 8 led sng tt, nh thi 1s dng T0.
Hnh 6-22: m xung ngoi dng counter T0.
Hnh 6-23: Lu m xung ngoi dng counter T0.
Hnh 6-26: m xung ngoi dng counter T1 hin th trn 3 led qut.
Hnh 6-22: Lu chng trnh m dng counter T1 ca PIC 16F887.
104
105
106
106
106
107
107
107
108
109
109
109
110
111
112
114
115
116
117
118
119
120
121
122
123
124
Hnh 7-1: S khi ca ADC PIC 16F887.

Hnh 7-2: Thanh ghi ADCON0.
130
131
125
vi

Hnh 7-4: nh dng cp thanh ghi lu kt qu.
Hnh 7-5: Thi gian chuyn i 10 bit.
Hnh 7-6: S mch o nhit dng PIC16F887 hin th trn 3 led trc tip.
Hnh 7-7: Lu chuyn i ADC o nhit knh th 0.
Hnh 7-8: S mch giao tip iu khin relay, triac, buzzer.
Hnh 7-10: S mch o nhit dng PIC16F887, hin th 3 led qut.
Hnh 7-11: Lu chuyn i ADC o nhit hin th led qut.
132
132
134
135
136
137
138
138
139
Hnh 8-1: Vi iu khin thc hin chng trnh chnh trong 2 trng hp khng v c ngt.
Hnh 8-3: Thanh ghi PIE1 v PIR1.
Hnh 8-5: Mch in ngt ca PIC16F887.
Hnh 8-6: iu khin 8 led sng tt.
Hnh 8-7: Lu iu khin 8 led sng tt nh thi 262ms dng ngt.
Hnh 8-8: Mch giao tip 2 led 7 on qut hin th m giy.
Hnh 8-9: Lu m giy dng Timer nh thi bo ngt.
Hnh 8-10: Mch o nhit dng cm bin LM35.
Hnh 8-11: Lu chuyn i ADC c bo ngt.
Hnh 8-12: o nhit dng cm bin LM35 v m giy.
Hnh 8-13: Lu chuyn i ADC c bo ngt v m giy dng timer bo ngt.
144
145
146
145
148
149
149
150
150
152
153
154
155
Hnh 9-1: H thng truyn ng b.

Hnh 9-2: H thng truyn bt ng b.
Hnh 9-3: Thanh ghi TXSTA.
Hnh 9-4: S khi ca khi pht d liu ca PIC16F887.
Hnh 9-5: Dng sng truyn d liu.
Hnh 9-6: Dng sng truyn 2 byte d liu.
Hnh 9-7: Thanh ghi RCSTA.
Hnh 9-8: S khi ca khi nhn d liu ca PIC16F887.
Hnh 9-9: Dng sng nhn d liu.
Hnh 9-11: H thng truyn d liu gia my tnh v vi iu khin.
Hnh 9-12: Lu iu khin truyn d liu.
Hnh 9-13: Giao din phn mm Terminal gi d liu.
Hnh 9-14: H thng truyn d liu gia my tnh v vi iu khin, hin th LCD.
Hnh 9-15: Lu iu khin truyn d liu, hin th trn LCD.
Hnh 9-16: H thng truyn d liu gia my tnh v vi iu khin, c LCD, bn phm.
Hnh 9-17: Lu iu khin truyn d liu, c thm LCD v bn phm.
160
160
162
163
163
163
164
166
166
167
170
170
171
172
172
173
174
Hnh 10-1: Dng sng iu ch rng xung.

Hnh 10-2: S khi ca PWM PIC 16F887.
Hnh 10-3: Dng sng PWM.
Hnh 10-4: Mch iu khin thay i cng sng ca n dng PWM.
Hnh 10-5: Lu iu khin n sng dng PWM.
Hnh 10-6: Mch thay i cng sng ca n dng PWM v 2 nt nhn.
Hnh 10-7: Lu iu khin n sng dng PWM v 2 nt nhn.
Hnh 10-8: Mch iu khin thay i tc ng c dng PWM.
Hnh 10-9: Lu iu khin thay i tc ng c dng PWM.
178
179
180
182
183
184
184
186
187
vii
BNG
2
2
Bng 3-1: Cc tc t.
Bng 3-2: Tm tt tp lnh ca PIC.
25
25
Bng 4-1: Cc kiu d liu ca phn mm PIC-C.

Bng 4-2: Cc ton t ph bin trong ngn ng C.
36
36
Bng 5-1: M 7 on cho cc s thp phn.

Bng 5-2: Cc chn ca LCD.
Bng 5-3: Cc lnh iu khin LCD.
Bng 5-4: a ch ca tng k t.
Bng 5-7: Thng tin hin th 2 hng k t.
72
94
95
96
98
Bng 6-1. La chn h s chia ca Timer0.

Bng 6-2. La chn tn s v t tng ng ca Timer1.
105
110
Bng 7-1: Tn s xung clock ty chn ph thuc vo tn s b dao ng.
133
Bng 8-1: Tm tt chc nng cc bit trong thanh ghi cho php ngt INTCON c a ch 0x0B.
Bng 8-2: Tm tt chc nng cc bit trong thanh ghi cho php ngt PIE1 c a ch 0x8C.
Bng 8-3: Tm tt chc nng cc bit trong thanh ghi cho php ngt PIR1 c a ch 0x0C.
Bng 8-4: Tm tt chc nng cc bit trong thanh ghi cho php ngt PIE2 c a ch 0x8D.
Bng 8-5: Tm tt chc nng cc bit trong thanh ghi cho php ngt PIR2 c a ch 0x0D.
145
146
146
147
147
Bng 9-1: Tm tt chc nng cc bit trong thanh ghi TXSTA.

Bng 9-2: Tm tt chc nng cc bit trong thanh ghi RCSTA.
Bng 9-3: Tm tt chc nng cc bit trong thanh ghi BAUDCTL.
Bng 9-4: Tm tt cc cng thc tnh tc baud.
162
164
167
168
Bng 10-1: Cc trng thi iu khin ng c DC.
186
viii
Chng 1
GII THIU
KHO ST VI IU KHIN MICROCHIP
CU HNH CA VI IU KHIN PIC 16F887

S CU TRC CA VI IU KHIN PIC 16F887
KHO ST S CHN VI IU KHIN PIC 16F887
CU HI N TP
CU HI M RNG
CU HI TRC NGHIM
BI TP
Nguyen nh Phu
I.
ai hoc s pham ky thuat
GII THIU
Vi x l c rt nhiu loi bt u t 4 bit cho n 32 bit, vi x l 4 bit hin nay khng cn nhng
vi x l 8 bit vn cn mc d c vi x l 64 bit.
L do s tn ti ca vi x l 8 bit l ph hp vi mt s yu cu iu khin trong cng nghip.
Cc vi x l 32 bit, 64 bit thng s dng cho cc my tnh v khi lng d liu ca my tnh rt ln
nn cn cc vi x l cng mnh cng tt.
Cc h thng iu khin trong cng nghip s dng cc vi x l 8 bit hay 16 bit nh h thng
in ca xe hi, h thng iu ha, h thng iu khin cc dy chuyn sn xut,
Khi s dng vi x l th phi thit k mt h thng gm c: Vi x l, c b nh, cc ngoi vi.
B NH
PORT NHP
PORT XUT
BUS A CH
CPU
BUS D LIU
BUS IU KHIN

B nh dng lu chng trnh cho vi x l thc hin v lu d liu cn x l, cc ngoi vi
dng xut nhp d liu t bn ngoi vo x l v iu khin tr li. Cc khi ny lin kt vi nhau
to thnh mt h thng vi x l.
Yu cu iu khin cng cao th h thng cng phc tp v nu yu cu iu khin n gin th
h thng vi x l cng phi c y cc khi trn.
2
Nguyen nh Phu
kt ni cc khi trn to thnh mt h thng vi x l i hi ngi thit k phi rt hiu bit

v tt c cc thnh phn vi x l, b nh, cc thit b ngoi vi. H thng to ra kh phc tp, chim
nhiu khng gian, mch in, v vn chnh l i hi ngi thit k hiu tht r v h thng. Mt l
do na l vi x l thng x l d liu theo byte hoc word trong khi cc i tng iu khin
trong cng nghip thng iu khin theo bit.
Chnh v s phc tp nn cc nh ch to tch hp b nh v mt s cc thit b ngoi vi cng
vi vi x l to thnh mt IC gi l vi iu khin Microcontroller.
Khi vi iu khin ra i mang li s tin li l d dng s dng trong iu khin cng nghip,
vic s dng vi iu khin khng i hi ngi s dng phi hiu bit mt lng kin thc qu nhiu
nh ngi s dng vi x l.
Phn tip theo chng ta s kho st vi iu khin thy r s tin li trong iu khin.
C rt nhiu hng ch to c vi iu khin, hng sn xut ni ting l TI, Microchip, ATMEL,
.... ti liu ny s trnh by vi iu khin tiu biu l PIC16F887 ca MICROCHIP.
II. KHO ST VI IU KHIN MICROCHIP

Vi iu khin hng Microchip c rt nhiu chng loi, tch hp nhiu chc nng, ngi dng c
th chn mt vi iu khin ph hp vi yu cu iu khin. Ti liu ny kho st vi iu khin
PIC16F887.
1.
CU HNH CA VI IU KHIN PIC16F887

Trong ti liu ny trnh by vi iu khin PIC16F887, cc thng s ca vi iu khin nh sau:
c im thc thi tc cao CPU RISC l:
C 35 lnh n.
Thi gian thc hin tt c cc lnh l 1 chu k my, ngoi tr lnh r nhnh l 2.
Tc hot ng:
Ng vo xung clock c tn s 20MHz.
Chu k lnh thc hin lnh 200ns.

C nhiu ngun ngt.
C 3 kiu nh a ch trc tip, gin tip v tc thi.
Cu trc c bit ca vi iu khin

B dao ng ni chnh xc:
Sai s 1%
C th la chn tn s t 31 kHz n 8 Mhz bng phn mm.
Cng hng bng phn mm.
Ch bt u 2 cp tc .
Mch pht hin hng dao ng thch anh cho cc ng dng quan trng.
C chuyn mch ngun xung clock trong qu trnh hot ng tit kim cng
sut.
C ch ng tit kim cng sut.
Dy in p hot ng rng t 2V n 5,5V.
Tm nhit lm vic theo chun cng nghip.
C mch reset khi c in (Power On Reset POR).
C b nh thi ch n nh in p khi mi c in (Power up Timer PWRT) v b

nh thi ch dao ng hot ng n nh khi mi cp in (Oscillator Start-up Timer
OST).
C mch t ng reset khi pht hin ngun in cp b st gim, cho php la chn bng
phn mm (Brown out Reset BOR).
Nguyen nh Phu
C b nh thi gim st (Watchdog Timer WDT) dng dao ng trong chip cho php
bng phn mm (c th nh thi ln n 268 giy).
a hp ng vo reset vi ng vo c in tr ko ln.
C bo v code lp trnh.
B nh Flash cho php xa v lp trnh 100,000 ln.
B nh Eeprom cho php xa v lp trnh 1,000,000 ln v c th tn ti trn 40 nm.
Cho php c/ghi b nh chng trnh khi mch hot ng.
C tch hp mch g ri.
Cu trc ngun cng sut thp

Ch ch: dng tiu tn khong 50nA, s dng ngun 2V.
Dng hot ng:
11A tn s hot ng 32kHz, s dng ngun 2V.

220A tn s hot ng 4MHz, s dng ngun 2V.
B nh thi Watchdog Timer khi hot ng tiu th 1,4A, in p 2V.
Cu trc ngoi vi
C 35 chn I/O cho php la chn hng c lp:
Mi ng ra c th nhn/cp dng ln khong 25mA nn c th trc tip iu khin

led.
C cc port bo ngt khi c thay i mc logic.
C cc port c in tr ko ln bn trong c th lp trnh.
C ng vo bo thc khi ch cng sut cc thp.
C module so snh tng t:
C 2 b so snh in p tng t
C module ngun in p tham chiu c th lp trnh.
C ngun in p tham chiu c nh c gi tr bng 0,6V.
C cc ng vo v cc ng ra ca b so snh in p.
C ch cht SR.
C b chuyn i tng t sang s:
C 14 b chuyn i tng t vi phn gii 10 bit.

C timer0: 8 bit hot ng nh thi/m xung ngoi c b chia trc c th lp trnh.
C timer1:
16 bit hot ng nh thi/m xung ngoi c b chia trc c th lp trnh.

C ng vo cng ca timer1 c th iu khin timer1 m t tn hiu bn ngoi.
C b dao ng cng sut thp c tn s 32kHz.
C timer2: 8 bit hot ng nh thi vi thanh ghi chu k, c b chia trc v chia sau.
C module capture, compare v iu ch xung PWM+ nng cao
C b capture 16 bit c th m c xung vi phn gii cao nht l 12,5ns.

C b iu ch xung PWM vi s knh ng ra l 1, 2 hoc 4, c th lp trnh vi
tn s ln nht l 20kHz.
C ng ra PWM iu khin li.
C module capture, compare v iu ch xung PWM
C b capture 16 bit c th m c xung vi chu k cao nht l 12,5ns.

C b so snh 16 bit c th so snh xung m vi chu k ln nht l 200ns
C b iu ch xung PWM c th lp trnh vi tn s ln nht l 20kHz.
C th lp trnh trn bo ISP thng qua 2 chn.
Nguyen nh Phu
C module truyn d liu ni tip ng b MSSP h tr chun truyn 3 dy SPI, chun

I2C 2 ch ch v t.
Bng 1-1 trnh by tm tt cu trc ca 5 loi PIC16F88X.
Cu hnh c minh ha nh hnh sau:
Hnh 1-3: Cu hnh ca vi iu khin.

S CU TRC CA VI IU KHIN PIC 16F887
2.
S cu trc vi iu khin c trnh by hnh 1-4.

Cc khi bn trong vi iu khin bao gm:
-
C khi thanh ghi nh cu hnh cho vi iu khin.
C khi b nh chng trnh c nhiu dung lng cho 5 loi khc nhau.
C khi b nh ngn xp 8 cp (8 level stack).
C khi b nh Ram cng vi thanh ghi FSR tnh ton to a ch cho 2 cch truy xut
gin tip v trc tip.
C thanh ghi lnh (Instruction register) dng lu m lnh nhn v t b nh chng trnh.
C thanh ghi b m chng trnh (PC) dng qun l a ch ca b nh chng trnh.
Nguyen nh Phu
Hnh 1-4: Cu trc bn trong ca vi iu khin.
C thanh ghi trng thi (status register) cho bit trng thi sau khi tnh ton ca khi ALU.
C thanh ghi FSR.

Nguyen nh Phu
C khi ALU cng vi thanh ghi working hay thanh ghi A x l d liu.
C khi cc b nh thi khi cp in PUT, c b nh thi ch dao ng n nh, c mch

reset khi c in, c b nh thi gim st watchdog, c mch reset khi pht hin st gim
ngun.
C khi gii m lnh v iu khin (Instruction Decode and Control).
C khi dao ng ni (Internal Oscillator Block).
C khi dao ng kt ni vi 2 ng vo OSC1 v OSC2 to dao ng.
C khi b dao ng cho timer1 c tn s 32kHz kt ni vi 2 ng vo T1OSI v T1OSO.
C khi CCP2 v ECCP.
C khi mch g ri (In-Circuit Debugger IDC).
C khi timer0 vi ng vo xung m t bn ngoi l T0CKI.
C khi truyn d liu ng b/bt ng b nng cao.
C khi truyn d liu ng b MSSP cho SPI v I2C.
C khi b nh Eeprom 256 byte v thanh ghi qun l a ch EEADDR v thanh ghi d liu
EEDATA.
C khi chuyn i tn hiu tng t sang s ADC.
C khi 2 b so snh vi nhiu ng vo ra v in p tham chiu.
C khi cc port A, B, C, E v D
KHO ST S CHN VI IU KHIN PIC16F887
3.
S chn ca vi iu khin PIC16F887 loi 40 chn c trnh by hnh 1-5.
Hnh 1-5: S chn ca PIC 16F887.

Vi iu khin PIC16F887 loi 40 chn, trong cc chn u tch hp nhiu chc nng, chc
nng ca tng chn c kho st theo port.
a.
Chc nng cc chn ca portA
Chn RA0/AN0/ULPWU/C12IN0- (2): c 4 chc nng:
Nguyen nh Phu
RA0: xut/ nhp s - bit th 0 ca port A.
AN0: ng vo tng t ca knh th 0.
ULPWU (Ultra Low-power Wake up input): ng vo nh thc CPU cng sut cc

thp.
C12IN0- (Comparator C1 or C2 negative input): ng vo m th 0 ca b so snh C1

hoc C2.
Chn RA1/AN1/C12IN1- (3): c 3 chc nng:
RA1: xut/nhp s - bit th 1 ca port A.
C12IN1- (Comparator C1 or C2 negative input): ng vo m th 1 ca b so snh C1

hoc C2.
Chn RA2/AN2/VREF-/CVREF/C2IN+ (4): c 5 chc nng:
VREF-: ng vo in p chun (thp) ca b ADC.
CVREF: in p tham chiu VREF ng vo b so snh.
C2IN+: ng vo dng ca b so snh C2.
Chn RA3/AN3/VREF+/C1IN+ (5): c 4 chc nng:
AN3: ng vo tng t knh th 3.
VREF+: ng vo in p chun (cao) ca b A/D.
C1IN+: ng vo dng ca b so snh C1.
Chn RA4/TOCKI/C1OUT (6): c 3 chc nng:
RA4: xut/nhp s bit th 4 ca port A.
TOCKI: ng vo xung clock t bn ngoi cho Timer0.
C1OUT: ng ra b so snh 1.
Chn RA5/AN4/ SS / C2OUT (7): c 4 chc nng:
SS : ng vo chn la SPI t (Slave SPI device).
C2OUT: ng ra b so snh 2.
Chn RA6/OSC2/CLKOUT (14): c 3 chc nng:
OSC2: ng ra dao ng thch anh. Kt ni n thch anh hoc b cng hng.
CLKOUT: ch RC, ng ra ca OSC2, bng tn s ca OSC1.
Chn RA7/OSC1/CLKIN (13): c 3 chc nng:
OSC1: ng vo dao ng thch anh hoc ng vo ngun xung bn ngoi.
CLKI: ng vo ngun xung bn ngoi.

Nguyen nh Phu
b.
Chc nng cc chn ca portB
Chn RB0/AN12/INT (33): c 3 chc nng:
RB0: xut/nhp s bit th 0 ca port B.
INT: ng vo nhn tn hiu ngt ngoi.
Chn RB1/AN10/C12IN3- (34): c 3 chc nng:
C12IN3-: ng vo m th 3 ca b so snh C1 hoc C2.
Chn RB2/AN8 (35): c 2 chc nng:
Chn RB3/AN9/PGM/C12IN2 (36): c 4 chc nng:
PGM: Chn cho php lp trnh in p thp ICSP.
C12IN1-: ng vo m th 2 ca b so snh C1 hoc C2
Chn RB4/AN11 (37): c 2 chc nng:
Chn RB5/ AN13/ T1G (38): c 3 chc nng:
KPI1: ng vo pht sinh ngt khi thay i trng thi th 1.
T1G (Timer1 gate input): ng vo Gate cho php time1 m dng m rng xung.
Chn RB6/ICSPCLK (39): c 2 chc nng:
RB6: xut/nhp s.
ICSPCLK: xung clock lp trnh ni tip.
Chn RB7/ICSPDAT (40): c 2 chc nng:
c.
RB7: xut/nhp s.
ICSPDAT: ng xut nhp d liu lp trnh ni tip.
Chc nng cc chn ca portC
Chn RC0/T1OSO/T1CKI (15): c 3 chc nng:
RC0: xut/nhp s bit th 0 ca port C.
T1OSO: ng ra ca b dao ng Timer1.
T1CKI: ng vo xung clock t bn ngoi Timer1.
Chn RC1/T1OSI/CCP2 (16): c 3 chc nng:
T1OSI: ng vo ca b dao ng Timer1.
Nguyen nh Phu
P1A: ng ra PWM.
CCP1: ng vo Capture1, ng ra compare1, ng ra PWM1.
Chn RC3/SCK/SCL (18): c 3 chc nng:
SCK: ng vo xung clock ni tip ng b/ng ra ca ch SPI.
SCL: ng vo xung clock ni tip ng b/ng ra ca ch I2C.
Chn RC4/SDI/SDA (23): c 3 chc nng:
SDI: ng vo d liu trong truyn d liu kiu SPI.
SDA: xut/nhp d liu I2C.
Chn RC5/SDO (24): c 2 chc nng:
SDO: ng xut d liu trong truyn d liu kiu SPI.
Chn RC6/TX/CK (25): c 3 chc nng:
TX: ng ra pht d liu trong ch truyn bt ng b USART.
CK: ng ra cp xung clock trong ch truyn ng b USART.
Chn RC7/RX/DT (26): c 3 chc nng:
RX: ng vo nhn d liu trong ch truyn bt ng b EUSART.
DT: ng pht v nhn d liu ch truyn ng b EUSART.
Chc nng cc chn ca portD
Chn RD0 (19): c 1 chc nng:
10
RD3: xut/nhp s bit th 3 ca port D.
CCP2: ng vo Capture2, ng ra compare2, ng ra PWM2.
Chn RC2 /P1A/CCP1 (17): c 3 chc nng:
d.
Chn RD5/ P1B (28): c 2 chc nng:
P1B: ng ra PWM.
Nguyen nh Phu
Chn RD6/ P1C (29): c 2 chc nng:
P1C: ng ra PWM.
Chn RD7/P1D (30): c 2 chc nng:
P1D: ng ra tng cng CPP1
Chn RE0/AN5 (8): c 2 chc nng:
RE0: xut/nhp s.
AN5: ng vo tng t 5.
RE1: xut/nhp s.
RE2: xut/nhp s.
Chn RE3/ MCLR /VPP (1): c 3 chc nng:
RE3: xut/nhp s - bit th 3 ca port E.
MCLR : l ng vo reset tch cc mc thp.
VPP: ng vo nhn in p khi ghi d liu vo b nh ni flash.
Chn VDD (11), (32):
e.
Ngun cung cp dng t 2V n 5V.
Chn VSS (12), (31):
Ngun cung cp 0V.
Chc nng cc chn phn chia theo nhm chc nng
Chc nng l port I/O:
PortA gm cc tn hiu t RA0 n RA7.
PortB gm cc tn hiu t RB0 n RB7.
PortC gm cc tn hiu t RC0 n RC7.
PortD gm cc tn hiu t RD0 n RD7.
PortE gm cc tn hiu t RE0 n RE3.
Chc nng tng t l cc ng vo b chuyn i ADC: c 14 knh
14 knh ng vo tng t t AN0 n AN13.
Hai ng vo nhn in p tham chiu bn ngoi l Vref+ v Vref-.
Chc nng tng t l cc ng vo b so snh C1 v C2: c 2 b so snh
C 4 ng vo nhn in p ng vo m ca 2 b so snh l: C12IN0-, C12IN1-,

C12IN2-, C12IN3-.
C 2 ng vo nhn in p tng t dng cho 2 b so snh l: C1IN+ v C2IN+.
C 2 ng ra ca 2 b so snh l: C1OUT v C2OUT.
C 1 ng vo nhn in p tham chiu chun cp cho 2 b so snh l: C VREF.
11
Nguyen nh Phu
Chc nng dao ng cp xung cho CPU hot ng:
C 2 ng vo ni vi t thch anh to dao ng l OSC1 v OSC2.
C 1 ng vo nhn tn hiu dao ng t ngun khc l CLKIN nu khng dng t thch

anh, c 1 ng ra cp xung clock cho thit b khc l CLKOUT.
Chc nng nhn xung ngoi ca T0 v T1:
C 1 ng vo nhn xung ngoi cho timer/counter T0 c tn l T0CKI.
C 1 ng vo nhn xung ngoi cho timer/counter T1 c tn l T1CKI.
C 2 ng vo to dao ng ring cho Timer1 hot ng c lp c tn l T1OSO v

T1OSI.
Chc nng truyn d liu SPI:
C 1 ng vo nhn d liu l SDI.
C 1 ng ra pht d liu l SDO.
C 1 ng ra pht xung clock l SCK.
C 1 ng vo chn chip khi hot ng ch t l SS .
Chc nng truyn d liu I2C:
C 1 ng truyn/nhn d liu l SDA.
C 1 ng ra pht xung clock l SCL.
Chc nng truyn d liu ng b ESUART:
C 1 ng truyn/nhn d liu l DT.
C 1 ng ra pht xung clock l CK.
Chc nng truyn d liu khng ng b ESUART:
C 1 ng nhn d liu l RX.
C 1 ng pht d liu l RX.
Chc nng ngt:
C 1 ng nhn tn hiu ngt cng l INT.
Chc nng CCP (capture, compare, pulse width modulation):
C 2 tn hiu cho khi CCP l CCP1 v CCP2.
C 4 tn hiu cho khi PWM l P1A, P1B, P1C, P1D.
Chc nng np chng trnh vo b nh flash:
C 1 tn hiu truyn d liu l ICSPDAT.
C 1 tn hiu nhn xung clock l ICSPCLK.
C 1 tn hiu iu khin np l PGM.
C 1 tn hiu nhn in p lp trnh l VPP.
C 1 ng vo reset c tn l MCLR (master clear).
C 4 chn cp ngun: VDD cp ngun dng, VSS ni vi 0V.
III. CU HI N TP TRC NGHIM BI TP

1.
CU HI N TP
Cu s 1-1:
12
Hy nu cu hnh ca vi iu khin PIC16F887.

Nguyen nh Phu
Cu s 1-2:
Hy cho bit cc loi b nh m vi iu khin PIC16F887 tch hp.
Cu s 1-3:
Hy trnh by tn v chc nng portA ca vi iu khin PIC16F887.
Cu s 1-4:
Hy trnh by tn v chc nng portB ca vi iu khin PIC16F887.
Cu s 1-5:
Hy trnh by tn v chc nng portC ca vi iu khin PIC16F887.
Cu s 1-6:
Hy trnh by tn v chc nng portD ca vi iu khin PIC16F887.
Cu s 1-7:
Hy trnh by tn v chc nng portE ca vi iu khin PIC16F887.
2.
CU HI M RNG
Cu s 1-8:
Hy nu cu hnh ca vi iu khin AT89S52.
Cu s 1-9:
Hy cho bit cc loi b nh m vi iu khin AT89S52 tch hp v m rng.
Cu s 1-10: Hy trnh by tn v chc nng cc port ca vi iu khin AT89S52.

Cu s 1-11: Hy tm hiu qu trnh pht trin ca h vi iu khin MCS51 v MCS52.
Cu s 1-12: Hy tm hiu cc port vi iu khin AT89C52 v so snh vi vi iu khin AT89S52.
Cu s 1-13: Hy tm hiu cu hnh vi iu khin AT89S8252 v so snh vi vi iu khin AT89S52.
Cu s 1-14: Hy tm hiu cu hnh vi iu khin AT89C51RD2 v so snh vi vi iu khin
AT89S52.
Cu s 1-15: Hy tm hiu cu hnh vi iu khin PIC16F877A v so snh vi vi iu khin
PIC16F887.
Cu s 1-16: Hy tm hiu cu hnh vi iu khin PIC18F4550 v so snh vi vi iu khin
PIC16F887.
3.
CU HI TRC NGHIM
Cu 1-1:
PIC 16F887 c bao nhiu port:
(a) 3
(c) 5
Cu 1-2:
(b) 4
(d) 6
Port no ca PIC 16F887 c 4 ng:
(a) A
(c) C
Cu 1-3:
(b) B
(d) E
PIC 16F887 c tch hp ADC bao nhiu bit:
(a) 8 bit
(c) 10 bit
Cu 1-4:
PIC 16F887 c tch hp bao nhiu knh ADC:
(a) 8 knh
(c) 10 knh
Cu 1-5:
(b) SDI, SDO

(d) SDA, SDI
Cc tn hiu truyn d liu SPI ca PIC 16F887 c tn l:
(a) SDI, SCL, SDO, SS

(c) SDI, SCK, SDO, SS
Cu 1-7:
(b) 14 knh
(d) 12 knh
Cc tn hiu truyn d liu I2C ca PIC 16F887 c tn l:
(a) SDI, SCL

(c) SCL, SDA
Cu 1-6:
(b) 9 bit
(d) 12 bit
(b) SDI, SDO, SS

(d) SDA, SDI, SCK
Cc tn hiu truyn d liu UART ca PIC 16F887 c tn l:
(a) TX, RX, CK

(c) TX, RX
(b) TX, DT, CK

(d) DT, CK
13
Nguyen nh Phu
Cu 1-8:
Cc tn hiu truyn d liu SART ca PIC 16F887 c tn l:
(a) TX, RX, CK

(c) TX, RX
Cu 1-9:
(b) TX, DT, CK

(d) DT, CK
Cc tn hiu no nhn xung CK cho timer0:
(a) T0SCK
(c) T0CKI
(b) T0SCL
(d) T0CK
Cu 1-10: Cc tn hiu no thit lp in p tham chiu cho ADC:

(a) CVREF v VREF+
(c) VREF+ v VREF4.
14
(b) CVREF v VREF(d) CVREF- v VREF-
BI TP
Chng 2
GII THIU
KIN TRC B NH
T CHC B NH CA VI IU KHIN PIC16F887
T CHC B NH
M LNH 14 BIT
KHO ST B NH D LIU V THANH GHI TRNG THI CA PIC
CU HI N TP TRC NGHIM - BI TP
CU HI N TP
CU HI M RNG
CU HI TRC NGHIM
BI TP
Nguyen nh Phu
I. GII THIU
chng ny kho st t chc b nh bn trong, cc thanh ghi ca vi iu khin 8 bit. Sau khi
kt thc chng ny th ngi c c th bit t chc b nh bn trong, chc nng ca tng loi b
nh, tn v chc nng ca cc thanh ghi c bit.
II. KIN TRC B NH

C 2 loi kin trc b nh c bn l kin trc Von Neumann v Harvard.
Hnh 2-1 trnh by hai kin trc:
Hnh 2-1: Kin trc Von Neumann v Harvard.

Kin trc Von Neumann: vi kin trc ny th b nh giao tip vi CPU thng qua 1 bus d
liu 8 bit, b nh c cc nh cha d liu 8 bit, b nh va lu tr chng trnh v d liu.
u im: kin trc n gin.
Khuyt im: do ch c 1 bus nn tc truy sut chm, kh thay i dung lng lu tr ca
nh.
Kin trc Harvard: vi kin trc ny th b nh c tch ra lm 2 loi b nh c lp: b nh
lu chng trnh v b nh lu d liu, CPU giao tip vi 2 b nh c lp nn cn 2 bus c lp. V
c lp nn c th thay i s bit lu tr ca tng b nh m khng nh hng ln nhau.
u im: do ch c 2 bus nn tc truy sut nhanh, ty thay i s bit ca nh.
Khuyt im: kin trc phc tp.
III. T CHC B NH CA VI IU KHIN PIC 16F887

1.
T CHC B NH CHNG TRNH
B nh chng trnh ca PIC16F8xx c dung lng 8K c chia lm 4 trang b nh, mi trang

2K, xem hnh 2-2.
Thanh ghi b m chng trnh PC (Program Counter) s qun l a ch ca b nh chng
trnh, thanh ghi PC c di 13 bit s qun l 8192 nh tng ng vi 8K nh. Mi nh
chng trnh lu 14 bit d liu.
Khi PIC b reset th thanh ghi PC c gi tr l 0000H v PIC s bt u thc hin chng trnh
ti a ch 0000H.
Khi c bt k ngt no tc ng th PIC s thc hin chng trnh phc v ngt ti a ch
0004H.
Mi trang ca b nh chng trnh c a ch xc nh nh trong hnh 2-6, vic phn chia theo
trang b nh ch c tc dng i vi lnh nhy v lnh gi chng trnh con. Khi ni nhy n hoc
16
Nguyen nh Phu
khi gi chng trnh con nm trong cng 1 trang th lnh s vit ngn gn hn, m lnh t hn so vi
trng hp nm khc trang.
Trong cc h vi iu khin khc th b nh ngn xp dng chung vi b nh d liu, u im l
cu trc n gin, khuyt im l vic dng chung nu khng bit gii hn s ln chim ln nhau v
lm mt d liu lu trong b nh ngn xp v chng trnh thc thi sai.
vi iu khin PIC th nh thit k tch b nh ngn xp c lp vi b nh d liu v ch
dng lu a ch tr v khi thc hin lnh gi chng trnh con v khi thc hin ngt. Dung lng b
nh b nh ngn xp ch c 8 nh t stack level 1 n stack level 8 - xem hnh 2-2. Do ch c 8
nh nn khi thc hin cc chng trnh con lng vo nhau ti a l 8 cp. Do lu a ch tr v
trong thanh ghi PC, m thanh ghi PC c chiu di 13 bit nn mi nh ngn xp c s bit l 13.
Khi khng s dng ngt th chng trnh c th vit bt u v lin tc ti a ch 0000H, nhng
nu s dng ngt th nn dng lnh nhy trnh vng nh bt u ti a ch 0004H - v vng nh
ny dng vit chng trnh con phc v ngt.
B nh chng trnh c chc nng lu tr chng trnh. Chng trnh sau khi vit xong trn
my tnh, dch ra s nh phn s c np vo b nh chng trnh vi iu khin thc hin.
PC <12:0>
13
CALL, RETURN,
RETFIE, RETLW
STACK LEVEL 1
STACK LEVEL 2
.
.
.
STACK LEVEL 8
VECTOR RESET
0000H
VECTOR NGT
0004H
0005H
0001H
0002H
0003H
TRANG 0 (PAGE 0)
TRANG 1 (PAGE 1)
TRANG 2 (PAGE 2)
07FFH
0800H
0FFFH
1000H
17FFH
1800H
TRANG 3 (PAGE 3)
1FFFH
Hnh 2-2: S b nh chng trnh v ngn xp.

2.
M LNH 14 BIT
Vi cc vi iu khin 8 bit ca cc hng khc th b nh chng trnh t chc theo n v l

byte, mi nh lu tr d liu 1 byte xem hnh 2-3. Nu m lnh 2 byte (gm 1 byte m lnh v 1
byte d liu hay a ch) th dng 2 nh lin tip lu v khi CPU c m lnh thc hin lnh th
CPU phi thc hin 2 ln c - mi ln 1 byte.
Vi vi iu khin PIC th mi nh ca b nh chng trnh c th lu tr d liu nhiu bit bao
gm c m lnh v d liu xem hnh 2-4. Khi CPU c m lnh thc hin th CPU ch thc hin 1
ln c c m lnh v d liu.
Vy vi t chc b nh ca PIC th tit kim c 1 chu k c d liu v th PIC s c tc
thc hin chng trnh nhanh hn.
17
Nguyen nh Phu
Tp lnh ca PIC l tp lnh rt gn nn ch dng c 6 bit nh phn m ha cc lnh, cng vi

d liu x l l byte - 8 bit nn tng cng l 14 bit.
Hnh 2-3: T chc b nh theo byte.

3.
Hnh 2-4: T chc b nh cha c m lnh v d liu.
KHO ST B NH D LIU V THANH GHI TRNG THI

a.
Cu trc b nh d liu
B nh d liu c phn chia thnh 4 Bank, mi bank c 128byte bao gm mt s thanh ghi
chc nng c bit, cn li l cc nh thng dng c chc nng lu tr d liu.
Ton b cc nh ca b nh d liu c gi l File thanh ghi.
Cc thanh ghi c chc nng c bit nm vng a ch thp, cc nh cn li khng c g c
bit nm cng a ch bn trn cc thanh ghi chc nng c bit xem nh cc nh RAM dng
lu d liu. Tt c cc bank thanh ghi u cha nhng thanh ghi c bit - xem hnh 2-4.
Theo hnh 2-4 th b nh d liu c chia lm 4 bank thanh ghi, mi bank c 128, tng cng l
512 nh, nhng do c 1 s thanh ghi c chc nng c bit bank no cng c nn lm gim s
lng. V d thanh ghi trng thi (status) 4 bank u c, thay v 4 thanh ghi th ch xem l 1, tng
t cho cc thanh ghi khc. S lng thc ch cn 368 nh.
C 2 cch truy xut b nh d liu: truy xut trc tip v truy xut gin tip.
Khi truy xut trc tip: th cc lnh ch c php truy xut 1 bank, mun truy xut cc nh
hay thanh ghi nm bank khc th phi i bank. C 2 bit chn bank l RP1 v RP0 nm trong thanh
ghi trng thi.
Khi truy xut gin tip: th cc lnh truy xut c php truy xut 2 bank: bank 0, 1 hoc bank
2, 3. Khi ang bank 0, 1 nu mun truy xut cc nh bank 2, 3 th phi i bank. C 1 bit chn
bank 0, 1 hoc bank 2, 3 l IRP nm trong thanh ghi trng thi.
b.
Thanh ghi trng thi STATUS REGISTER A CH 03H, 83H, 103H, 83H
TGTT cha trng thi ca khi ALU, trng thi Reset v cc bit chn bank b nh d liu.
IRP
RP1
RP0
TO
PD
Bit 7
DC
Bit 0
Hnh 2-5: Thanh ghi trng thi.
Chc nng ca cc bit trong thanh ghi trng thi:

Bit 7
IRP: bit la chn thanh ghi (dng a ch gin tip).

1 = bank 2, 3 (100h-1FFh)
18
Nguyen nh Phu
0 = bank 0, 1 (000h- 0FFh)

FILE ADDRESS
Indirect addr(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
Indirect addr(*)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
OSCCON
OSCTUNE
SSPCON2
PR2
SSPADD
SSPSTAT
WPUB
IOCB
VRCON
TXSTA
SPBRG
SPBRGH
PWM1CON
ECCPAS
PSTRCON
ADRESL
ADCON1
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
92H
93H
94H
95H
96H
97H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
A0H
7FH
ACCESSES
70H 7FH
FILE ADDRESS
Indirect addr(*)
TMR0
PCL
STATUS
FSR
WDTCON
PORTB
CM1CON0
CM2CON0
CM2CON1
PCLATH
INTCON
EEDAT
EEADR
EEDATH
EEADRH
THANH GHI
THNG DNG
16 BYTE
100H
101H
102H
103H
104H
105H
106H
107H
108H
109H
10AH
10BH
10CH
10DH
10EH
10FH
110H
111H
112H
113H
114H
115H
116H
117H
118H
119H
11AH
11BH
11CH
11DH
11EH
11FH
120H
EFH
F0H
FFH
BANK 1
ACCESSES
70H 7FH
FILE ADDRESS
Indirect addr(*)
OPTION_REG
PCL
STATUS
FSR
SRCON
TRISB
BAUDCTL
ANSEL
ANSELH
PCLATH
INTCON
EECON1
EECON2
RESERVED
RESERVED
THANH GHI
THNG DNG
16 BYTE
180H
181H
182H
183H
184H
185H
186H
187H
188H
189H
18AH
18BH
18CH
18DH
18EH
18FH
190H
191H
192H
193H
194H
195H
196H
197H
198H
199H
19AH
19BH
19CH
19DH
19EH
19FH
1A0H
THANH GHI
THNG DNG
80 BYTE
THANH GHI
THNG DNG
80 BYTE
THANH GHI
THNG DNG
80 BYTE
THANH GHI
THNG DNG
96 BYTE
BANK 0
FILE ADDRESS
16FH
170H
17FH
BANK 2
ACCESSES
70H 7FH
1EFH
1F0H
1FFH
BANK 3
Hnh 2-6: T chc File thanh ghi.

Quy c: (1) Cc nh t mu xm l cha thit k nu c s c gi tr l 0.
Quy c: (2) Cc du (*) khng phi l thanh ghi vt l.
Bit 6-5
RP1:RP0: cc bit la chn thanh ghi (dng a ch trc tip)

11 = bank 3 (180h-1FFh)
10 = bank 2 (100h- 17Fh)
01 = bank 1 (80h- FFh)
00 = bank 0 (00h- 7Fh)
Bit 4
TO : Time-out bit (Bit thi gian ch)

1 = sau khi m ngun, lnh CLRWDT hoc SLEEP
0 = thi gian ch ca WDT c thc hin
19
Nguyen nh Phu
PD : Power-down bit (bit tt ngun)
Bit 3
1= sau khi m ngun hoc bng lnh CLRWDT

0= thc thi lnh SLEEP
Bit 2
Z: Zero bit (bit 0)

1 = khi kt qu bng 0.
0 = khi kt qu khc 0.
DC: Digit carry/ borrow bit (cc lnh ADDWF, ADDLW, SUBLW, SUBWF)
Bit 1
(bit trn / mn)

1 = khi cng 4 bit thp b trn.
0 = khi cng 4 bit thp khng b trn.
C: Carry/ borrow bit (cc lnh ADDWF, ADDLW, SUBLW, SUBWF)
Bit 0
1 = khi kt qu php ton c trn.

0 = khi kt qu php ton khng b trn.
Ch : Nu php ton tr th trng thi ca c C nh sau: nu php tr ln hn 0 th c C bng
0, nu kt qu tr nh hn hay bng 0 th c C bng 1.
Cc thanh ghi cn li s c kho st cc phn c lin quan.
4.
B NH D LIU EEPROM
B nh d liu Eeprom c dung lng 256 byte dng lu d liu quan trng khi mt in th
d liu ny vn cn. Cch thc ghi d liu vo b nh Eeprom s c trnh by phn b nh
Eeprom.
IV. CU HI N TP TRC NGHIM - BI TP

1.
CU HI N TP
Cu s 2-1:
Hy cho bit cc loi b nh m vi iu khin PIC16F887 tch hp.
Cu s 2-2:
Hy trnh by cu trc b nh RAM ni ca vi iu khin PIC16F887.
Cu s 2-3:
Hy cho bit cc thanh ghi no m cc bank u c ca vi iu khin PIC16F887.
Cu s 2-4:
Hy cho bit t chc b nh chng trnh ca vi iu khin PIC16F887.
2.
CU HI M RNG
Cu s 2-5:
Hy tm hiu t chc b nh vi iu khin PIC18F4550 v so snh vi PIC16F887.
Cu s 2-6:
Hy tm hiu t chc b nh vi iu khin PIC18F4620 v so snh vi PIC16F887.
3.
CU HI TRC NGHIM
Cu 2-1:
B nh chng trnh ca PIC 16F887 c dung lng l:
(a) 8KByte
(c) 8K16bit
Cu 2-2:
B nh d liu ca PIC 16F887 c dung lng l:
(a) 256Byte
(c) 8K16bit
Cu 2-3:
(b) 8K14bit
(d) 368Byte
B nh d liu EEPROM ca PIC 16F887 c dung lng l:
(a) 8KWord
20
(b) 8K14bit
(d) 368Byte
(b) 8K14bit
Nguyen nh Phu
(c) 256Byte
Cu 2-4:
(b) 1024 word

(d) 368 byte
Mi bank b nh d liu ca PIC 16F887 c dung lng:
(a) 256 byte

(c) 2048 byte
Cu 2-9:
(b) 4 trang
(d) 4 bank
Mi trang b nh chng trnh ca PIC 16F887 c dung lng:
(a) 256 byte

(c) 2048 word
Cu 2-8:
(b) 4 trang
(d) 4 bank
B nh d liu ca PIC 16F887 chia lm:
(a) 2 trang
(c) 2 bank
Cu 2-7:
(b) 814bit
(d) 813bit
B nh chng trnh ca PIC 16F887 chia lm:
(a) 2 trang
(c) 2 bank
Cu 2-6:
(d) 368Byte
B nh ngn xp ca PIC 16F887 c dung lng l:
(a) 8Byte
(c) 256Byte
Cu 2-5:
(b) 128 byte

(d) 368 byte
a ch ca nh 1234H thuc trang b nh no:
(a) Trang th 0
(c) Trang th 2
(b) Trang th 1
(d) Trang th 3
Cu 2-10: Thanh ghi PC ca PIC 16F887 c chiu di:

(a) 12 bit
(c) 14 bit
(b) 13 bit
(d) 15 bit
Cu 2-11: Phn chia b nh theo trang c u im:

(a) Lm vi iu khin chy nhanh
(c) Lm gim a ch b nh
(b) Lm tng s lng m code

(d) Lm gim s lng m code
Cu 2-12: Cc chng trnh con lng vo nhau ca PIC ph thuc vo dung lng:
(a) B nh chng trnh (b) B nh d liu
(c) B nh ngn xp
(d) B nh EEPROM
Cu 2-13: Truy xut trc tip b nh d liu ca PIC 16F887 th:

(a) Cho php ty c 4 bank
(c) Ch cho php 1 bank
(b) Cho php 2 bank

(d) Cho php 3 bank
Cu 2-14: Truy xut gin tip b nh d liu ca PIC 16F887 th:

(a) Cho php ty c 4 bank
(c) Ch cho php 1 bank
(b) Cho php 2 bank

(d) Cho php 3 bank
Cu 2-15: Bit cho php thay i cc bank trong truy xut trc tip b nh d liu ca PIC 16F887 l:
(a) IRP1, IRP2
(c) RP1, RP2
(b) RP1, RP0

(d) RP, IRP
Cu 2-16: Bit cho php thay i cc bank trong truy xut gin tip b nh d liu ca PIC 16F887 l:
(a) IRP1, IRP2
(c) IRP
(b) RP1, RP0

(d) IRP, RP1, RP0
Cu 2-17: Thanh ghi no u c trong 4 bank b nh d liu ca PIC 16F887:

(a) PORTB
(c) PORTA
(b) TRISB
(d) STATUS
Cu 2-18: Thanh ghi no u c trong 4 bank b nh d liu ca PIC 16F887:

21
Nguyen nh Phu
(a) TRISB
(c) TRISA
(b) PCL
(d) TMR0
Cu 2-19: Khi ngt xy ra th PIC 16F887 s thc hin chng trnh con phc v ngt ti a ch:
(a) 0004H
(c) 0000H
(b) 0014H
(d) 0024H
Cu 2-20: a ch b nh chng trnh ca PIC 16F887:

(a) T 0000H n 1FFFH
(c) T 0000H n 07FFH
4.
22
(b) T 0800H n 0FFFH

(d) T 0000H n 2FFFH
BI TP
Chng 3
GII THIU
LNH HP NG CA VI IU KHIN PIC 16F887
GII THIU
KHO ST TP LNH TM TT VI IU KHIN PIC 16F887
TP LNH CHI TIT
CU HI N TP
CU HI TRC NGHIM
CU HI M RNG
BI TP
Nguyen nh Phu
I. GII THIU
chng ny kho st tp lnh hp ng ca cc vi iu khin. Sau khi kt thc chng ny bn
s bit m lnh nh phn, lnh gi nh, cc kiu nh a ch b nh ca vi iu khin, bit tp lnh
hp ng ca vi iu khin
Vi iu khin hay vi x l l cc IC lp trnh, khi bn thit k h thng iu khin c s dng
vi x l hay vi iu khin v d nh h thng iu khin n giao thng cho mt ng t gm c cc
n Xanh, Vng, v cc led 7 on hin th thi gian th mi ch l phn cng, mun h
thng vn hnh th bn phi vit mt chng trnh iu khin np vo b nh ni bn trong vi iu
khin hoc b nh bn ngoi v gn vo trong h thng h thng vn hnh v d nhin bn phi vit
ng th h thng mi vn hnh ng. Chng trnh gi l phn mm.
Phn mm v phn cng c quan h vi nhau, ngi lp trnh phi hiu r hot ng ca phn
cng vit chng trnh. phn ny s trnh by chi tit v tp lnh ca vi iu khin gip bn hiu
r tng lnh bn c th lp trnh c.
Cc khi nim v chng trnh, lnh, tp lnh v ngn ng gi nh trnh by chng 1,
y ch tm tt li.
Chng trnh l mt tp hp cc lnh c t chc theo mt trnh t hp l gii quyt ng
cc yu cu ca ngi lp trnh.
Ngi lp trnh l ngi bit gii thut vit chng trnh v sp xp ng cc lnh theo gii
thut. Ngi lp trnh phi bit chc nng ca tt c cc lnh ca vi iu khin vit chng trnh.
Tt c cc lnh c th c ca mt ngn ng lp trnh cn gi l tp lnh.
Lnh ca vi iu khin l mt s nh phn 8 bit [cn gi l m my]. 256 byte t 0000 0000b
n 1111 1111b tng ng vi 256 lnh khc nhau. Do m lnh dng s nh phn qu di v kh nh
nn cc nh lp trnh xy dng mt ngn ng lp trnh Assembly cho d nh, iu ny gip cho
vic lp trnh c thc hin mt cch d dng v nhanh chng cng nh c hiu v g ri chng
trnh.
Khi vit chng trnh bng ngn ng lp trnh Assembly th vi iu khin s khng thc hin
c m phi dng chng trnh bin dch Assembler chuyn i cc lnh vit bng Assembly ra
m lnh nh phn tng ng ri np vo b nh khi vi iu khin mi thc hin c chng
trnh.
Ngn ng lp trnh Assembly do con ngi to ra, khi s dng ngn ng Assembly vit th
ngi lp trnh vi iu khin phi hc ht tt c cc lnh v vit ng theo qui c v c php, trnh t
sp xp d liu chng trnh bin dch c th bin dch ng.
II. LNH HP NG CA VI IU KHIN PIC 16F887

1.
GII THIU
Tp lnh ca PIC 16 c chia ra lm 3 nhm lnh:
Lnh x l bit
Lnh x l byte
Lnh x l hng s v iu khin
Mi lnh ca PIC l mt t d liu 14 bit c chia ra lm 2 nhm gm m lnh hot ng

(opcode: operation code) v tc t (operand).
M lnh Opcode cho bit loi lnh m CPU phi thc hin. Cc dng m lnh nh hnh 3-1:
13
8
OPCODE
13
24
7 6
d
10 9 8 7
OPCODE
(BIT)
0
f(FILE#)
0
f(FILE#)
Chng 3.Lenh hp ng
Nguyen nh Phu
13
OPCODE
k (literal)
13
11 10
OPCODE
0
k (literal)
Hnh 3-1: Cc dng m lnh.

Tc t operand l d liu m lnh s x l.
Bng 3-1: Cc tc t:
TT Tc
M t
t
1
f
Register file address (000 to 07F): l a ch 7 bit ca file thanh ghi 8 bit, ca 1 bank.
2
W
Working register: Thanh ghi lm vic hay thanh ghi A.
3
b
Bit address within an 8-bit file register: l a ch ca 1 bit nm trong thanh ghi file 8 bit
4
k
Literal field, constant data or label: L hng s hoc a ch ca nhn.
5
d
Destination select: la chn ni lu d liu: d=0 th lu vo W, d=1 th lu vo f, mc
nhin khng ghi d trong lnh th tng ng d=1.
6
PC Program counter: b m chng trnh.
7
TO Time-out bit: bit bo thi gian ht.
8
PD Power -down bit: bit bo CPU ang lm vic ch ng.
Vi lnh x l byte: th 'f' i din cho file thanh ghi v 'd' i din cho hng lu d liu: nu
'd' bng 0 th d liu sau khi x l lu vo thanh ghi 'W', nu 'd' bng 1 th d liu sau khi x l lu
vo thanh ghi 'f'.
Vi lnh x l bit: th 'b' i din cho bit nm trong file thanh ghi 'f''.
Vi lnh x l hng s hoc iu khin: th 'k' i din cho hng s 8 bit hoc a ch 11 bit.
Mt chu k lnh gm 4 chu k dao ng, nu s dng thch anh c tn s 4MHz th thi gian
thc hin mi lnh l 1s. Hu ht cc lnh thc hin mt 1 chu k lnh, ngoi tr lnh kim tra iu
kin ng sai hoc lnh lm thay i gi tr ca thanh ghi PC th thc hin mt 2 chu k my.
2.
KHO ST TP LNH TM TT VI IU KHIN PIC 16F887

Bng 3-2: Tm tt tp lnh ca PIC:
Nhm lnh x l byte gia thanh ghi W vi f
TT C php
Chc nng
Chu
k
M lnh
C b nh
hng
ADDWF f,d
(W) cng (f)
00 0111 dfff ffff
C, DC, Z
ANDWF f,d
(W) and (f)
00 0101 dfff ffff
CLRF f
Xa (f)
00 0001 1fff ffff
CLRW -
Xa (W)
00 0001 0xxx
xxxx
COMF f,d
B (f)
00 1001 dfff ffff
DECF f,d
Gim f
00 0011 dfff ffff
DECEFSZF
f,d
Gim f, b lnh k nu f =
0
1(2)
00 1011 dfff ffff
INCF f,d
Tng f
00 1010 dfff ffff
INCEFSZF f,d
Tng f, b lnh k nu f = 0
1(2)
00 1111 dfff ffff
Chng 3. Lenh hp ng.
25
Nguyen nh Phu
10
IORWF f,d
(W) or (f)
00 0100 dfff ffff
11
MOVF f,d
copy (f)
00 1000 dfff ffff
12
MOVWF f
(W) (f)
00 0000 1fff ffff
13
NOP
Khng lm g
00 0000 0xx0
0000
14
RLF f,d
Xoay tri f xuyn qua c C
00 1101 dfff ffff
15
RRF f,d
Xoay phi f xuyn qua c

C
00 1100 dfff ffff
16
SUBWF f,d
(F) tr (f)
00 0010 dfff ffff
C, DC, Z
17
SWAPF f,d
Hon chuyn 4 bit ca f
00 1110 dfff ffff
18
IORWF f,d
(W) xor (f)
00 0110 dfff ffff
Nhm lnh x l bit

TT C php
Chc nng
Chu k M lnh
C b nh hng
BCF f,b
Lm bit b trong f xung 0
01 00bb bfff ffff
BSF f,b
Lm bit b trong f ln 1
01 01bb bfff ffff
BTFSC f,b Nu bit b bng 0 th b lnh k 1
01 10bb bfff ffff
BTFSS f,b
Nu bit b bng 1 th b lnh k 1
01 11bb bfff ffff
Nhm lnh hng s v iu khin

TT C php
Chc nng
Chu k M lnh
C b nh hng
ADDLW k
(W) cng k (W)
11 111x kkkk kkkk C, DC, Z
ANDLW k
(W) and k (W)
11 1001 kkkk kkkk Z
CALL k
Gi chng trnh con
10 0kkk kkkk kkkk
CLRWDT
Xa b nh thi
00 0000 0110 0100 TO , PD
GOTO k
Nhy n a ch k
10 1kkk kkkk kkkk
IORLW k
(W) or k
11 1000 kkkk kkkk Z
MOVLW k K (W)
11 00xx kkkk kkkk
RETFIE
Tr v t ngt
00 0000 0000 1000
RETLW
Tr v t chng trnh con 2
11 01xx kkkk kkkk
v np hng s vo W
10
RETURN
Tr v t chng trnh con 2
00 0000 0000 1000
11
SLEEP
Cpu vo ch ch
00 0000 0110 0011 TO , PD
12
SUBLW k
K (W) (W)
11 110x kkkk kkkk C, DC, Z
13
XORLW k
(W) xor k
11 1010 kkkk kkkk Z
3.
TP LNH CHI TIT
1. Lnh: ADDLW
C php:
Tc t:
26
Cng hng s k vo W
ADDLW
k
0 k 255
Chng 3.Lenh hp ng
Nguyen nh Phu
Thc thi:
(W) + k (W).
C nh hng: C, DC, Z.
Chu k thc hin: 1.
Chc nng: cng ni dung thanh ghi W vi hng s k 8 bit v kt qu lu vo W.
2. Lnh: ADDWF
Cng W vi f
C php:
ADDWF
f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(W) + (f) (dest). C nh hng: C, DC, Z. Chu k thc hin: 1.
Chc nng: cng ni dung thanh ghi W vi thanh ghi f. Nu d= 0 th lu kt qu vo
thanh ghi W, cn d=1 th lu vo thanh ghi f.
3. Lnh: ANDLW
And hng s vi W
C php:
ANDLW
k
Tc t:
0 k 255
Thc thi:
(W) AND (k)(W). C nh hng: Z.
Chu k thc hin: 1.
Chc nng: And ni dung thanh ghi W vi hng s k 8 bit, kt qu lu vo thanh ghi
W.
4. Lnh: ANDWF
And W vi F
C php:
ANDWF
f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(W) AND (f) (dest).
C nh hng: Z.
Chu k thc hin: 1.
Chc nng: And thanh ghi W vi thanh ghi f. Nu d = 0 th kt qu lu vo thanh ghi
W, nu d=1 th kt qu lu vo thanh ghi f.
5. Lnh: BCF
xo bit trong thanh ghi F - BIT CLEAR FILE
C php:
BCF
f,b
Tc t:
0 f 127, 0 b <7
Thc thi:
0 (f<b>).
C nh hng: khng. Chu k thc hin: 1.
Chc nng: xa bit b trong thanh ghi f.
6. Lnh: BSF
set bit trong thanh ghi F
- BIT SET FILE
C php:
BSF f,b
Tc t:
0 f 127, 0 b <7
Thc thi:
1 (f<b>).
Chc nng: set bit b trong thanh ghi f ln 1.
7. Lnh: BTFSS
kim tra 1 bit trong thanh ghi F v nhy nu bng 1
C php:
BTFSS
f,b
- BIT TEST FILE SKIP IF SET
Tc t:
0 f 127, 0 b <7
Thc thi:
nhy nu f<b>=1.
C nh hng: khng. Chu k thc hin: 1(2).
Chc nng: kim tra bit b: nu bit b bng 1 th lnh k b b qua v thay bng lnh
NOP, nu bit b bng 0 th thc thi lnh k.
8. Lnh: BTFSC
kim tra 1 bit trong thanh ghi F v nhy nu bng 0
C php:
BTFSC
f,b
- BIT TEST FILE SKIP IF CLEAR
Tc t:
0 f 127, 0 b <7
Thc thi:
nhy nu f<b>=0.
Chc nng: kim tra bit b: nu bit b bng 0 th lnh k b b qua v thay bng lnh
NOP, nu bit b bng 1 th thc thi lnh k.
9. Lnh: CALL
gi chng trnh con
C php:
CALL k
Tc t:
0 k 2047
Thc thi:
(PC + 1) TOS; kPC
Chng 3. Lenh hp ng.
- TOP OF STACK
27
Nguyen nh Phu

Chc nng: gi chng trnh con. a ch tr v (PC+1) c ct vo ngn xp. Thanh
ghi PC c np a ch ca chng trnh con v chng trnh con c thc hin.
10. Lnh: CLRF

xo thanh ghi f
C php:
CLRF f
- CLEAR FILE
Tc t:
0 f 127
Thc thi:
00h (f); 1 Z.
Trng thi nh hng: Z. Chu k thc hin: 1.
Chc nng: xo thanh ghi f v c Z bng 1.
11. Lnh: CLRW
xo thanh ghi W
C php:
CLRW
- CLEAR WORKING
Tc t:
khng
Thc thi:
00h (W), 1 Z. C nh hng: Z. Chu k thc hin: 1.
Chc nng: xo thanh ghi W v c Z bng 1.
12. Lnh: CLRWDT
xo WDT
C php:
CLRWDT
- CLEAR WATCHDOG TIMER
Tc t:
khng
Thc thi:
00 WDT; 0 B m chia trc ca WDT; 1 TO ; 1 PD
C nh hng: TO , PD . Chu k thc hin: 1.
Chc nng: lnh CLRWDT s xo b nh thi WDT v b m chia trc ca WDT.
Cc bit PD , TO v mc 1.
13. Lnh: COMF
b thanh ghi f
C php:
COMF f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
( f ) (dest).
C nh hng: Z.
Chu k thc hin: 1.
Chc nng: b 1 ni dung thanh ghi f. Nu d=0 th kt qu lu vo thanh ghi W. Nu
d=1 th kt qu lu vo thanh ghi f.
14. Lnh: DECF
gim ni dung thanh ghi f
C php:
DECF
f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(f) 1 (dest).
C nh hng: Z.
Chu k thc hin: 1.
Chc nng: gim ni dung thanh ghi f i 1. Nu d= 0 th kt qu lu vo thanh ghi W.
Nu d= 1 th kt qu lu vo thanh ghi f.
15. Lnh: DECFSZ
gim ni dung thanh ghi f v nhy nu bng 0
C php:
DECFSZ
f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(f) 1 (dest); C nh hng: khng. Chu k thc hin: 1(2).
Chc nng: gim ni dung thanh ghi f i 1. Nu d = 0 th kt qu lu vo thanh ghi W.
Nu d = 1 th kt qu lu vo thanh ghi f. Nu kt qu bng 0 th b qua lnh k v thay
bng lnh NOP.
16. Lnh: GOTO
lnh r nhnh khng iu kin
C php:
GOTO k
Tc t:
0 k 2047
Thc thi:
k PC.
Chc nng: nhy khng iu kin n a ch k. a ch ni nhy n np vo PC v
CPU tip tc thc hin lnh ti ni nhy n.
28
Chng 3.Lenh hp ng
Nguyen nh Phu
17. Lnh: INCF

lnh tng ni dung thanh ghi f
C php:
INCF f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(f) + 1 (dest).
C nh hng: Z.
Chu k thc hin: 1.
Chc nng: tng ni dung ca thanh ghi f ln 1. Nu d = 0 th kt qu lu vo thanh ghi
W. Nu d = 1 th kt qu lu tr li vo thanh ghi f.
18. Lnh: INCFSZ
lnh tng ni dung thanh ghi f v nhy nu bng 0
C php:
INCFSZ
f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(f) + 1 (dest).
Chc nng: tng ni dung ca thanh ghi f ln 1. Nu d= 0 th kt qu lu vo thanh ghi
W. Nu d= 1 th kt qu lu vo thanh ghi f. Nu kt qu l bng 0 th b qua lnh k
v c thay bng lnh NOP.
19. Lnh: IORLW
lnh OR hng s vi W
C php:
IORLW
k
Tc t:
0 k 255
Thc thi:
(W) OR k W.
C nh hng: Z.
Chc nng: Or hng s k 8 bit vi W.
Chu k thc hin: 1.
20. Lnh: IORWF

lnh OR W vi f
C php:
IORWF
f,d
Tc t:
0 f 127
Thc thi:
(W) OR f (dest). C nh hng: Z.
Chu k thc hin: 1.
Chc nng: Or ni dung thanh ghi W vi thanh ghi f. Nu d= 0 th kt qu lu vo
thanh ghi W. Nu d= 1 th kt qu lu vo thanh ghi f.
21. Lnh: MOVLW
lnh np d liu vo thanh ghi W
C php:
MOVLW
k
Tc t:
0 k 255
Thc thi:
k W.
Chc nng: np d liu 8 bit k vo thanh ghi W.
22. Lnh: MOVF
lnh copy d liu t thanh ghi W sang f
C php:
MOVF
f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(f) (ni n).
C nh hng: Z.
Chu k thc hin: 1.
Chc nng: copy ni dung thanh ghi f sang ni n ty thuc vo gi tr ca d. Nu
d = 0 th ni n l thanh ghi W. Nu d=1 th ni n chnh l thanh ghi f. Trng
hp d=1 rt tin li kim tra thanh ghi file v c Z b nh hng: nu ni dung
thanh ghi f bng 0 th c Z bng 1, nu khc 0 th c Z bng 0.
23. Lnh: MOVWF
lnh copy d liu
C php:
MOVWF
f
Tc t:
0 f 127, d [0,1]
Thc thi:
(W) f.
Trng thi nh hng: khng. Chu k thc hin:
1.
Chc nng: copy ni dung thanh ghi W sang thanh ghi f.
24. Lnh: NOP
lnh khng hot ng
C php:
NOP
Tc t:
khng c
Thc thi:
khng lm g c. Trng thi nh hng: khng. Chu k thc hin: 1.
Chng 3. Lenh hp ng.
29
Nguyen nh Phu
Chc nng: khng lm g c
25. Lnh: RETFIE

lnh tr v t chng trnh con phc v ngt.
C php:
RETFIE
Tc t:
khng c.
Thc thi:
TOS PC, 1 GIE.
C nh hng: khng. Chu k thc hin:
2.
Chc nng: kt thc chng trnh con phc v ngt, tr li chng trnh chnh. a
ch tr v nh ngn xp tr li cho PC, bit cho php ngt ton cc GIE = 1 cho
php ngt.
26. Lnh: RETLW
lnh tr v t chng trnh con
C php:
RETLW
k
Tc t:
0 k 255
Thc thi:
k W, TOS PC. Trng thi nh hng: khng. Chu k thc hin:
2.
Chc nng: kt thc chng trnh con tr li chng trnh chnh, ng thi np hng
s k vo thanh ghi W, a ch tr v trong nh ngn xp tr li cho PC.
27. Lnh: RLF
lnh xoay tri qua c C
C php:
RLF f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
MSB
LSB
Trng thi nh hng: C. Chu k thc hin: 1.

Chc nng: xoay ni dung ca thanh ghi f v c C sang tri mt bit. Nu d= 0 th kt
qu c lu vo thanh ghi W. Nu d= 1 th kt qu lu vo thanh ghi f.
28. Lnh: RRF

lnh xoay phi qua c C
C php:
RRF f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
MSB
LSB
Trng thi nh hng: C.

Chu k thc hin: 1.
Chc nng: xoay ni dung ca thanh ghi f v c C sang phi 1 bit. Nu d= 0 th kt qu
c lu vo thanh ghi W. Nu d= 1 th kt qu lu vo thanh ghi f.
29. Lnh: RETURN

lnh kt thc chng trnh con
C php:
RETURN
Tc t:
khng
Thc thi:
TOS PC. Trng thi nh hng: khng. Chu k thc hin: 2.
Chc nng: lnh kt thc chng trnh con tr li chng trnh chnh, a ch tr v
trong nh ngn xp tr li cho PC.
30. Lnh: SLEEP
30
lnh ng
Chng 3.Lenh hp ng
Nguyen nh Phu
C php:
SLEEP
Tc t:
khng
Thc thi:
00h WDT; 0 b m chia trc ca WDT; 1 TO ; 0 PD
C nh hng: TO , PD .
Chu k thc hin: 1.
Chc nng: PD = 0 cho bit CPU ang ch ng, b dao ng ngng hot ng.
Bit TO =1. B nh thi WDT v b chia trc b xa.
31. Lnh: SUBLW

lnh tr hng s cho thanh ghi W
C php:
SUBLW
k
Tc t:
0 k 255
Thc thi:
k (W) (W).
C nh hng: C, DC, Z. Chu k thc hin: 1.
Chc nng: hng s k 8 bit tr cho ni dung thanh ghi W v kt qu lu vo thanh ghi
W.
32. Lnh: SUBWF
lnh tr thanh ghi f cho thanh ghi W
C php:
SUBLW
f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(f) (W) (dest).
C nh hng: C, DC, Z. Chu k thc hin: 1.
Chc nng: ni dung thanh ghi f tr cho ni dung thanh ghi W. Nu d= 0 th kt qu lu
vo thanh ghi W. Nu d= 1 th kt qu lu vo thanh ghi f.
33. Lnh: SWAPF
lnh hon chuyn 4 bit ca thanh ghi f
C php:
SWAPF
f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>)
Chc nng: 4 bit cao v 4 bit thp ca thanh ghi f c i vi nhau. Nu d= 0 th kt
qu lu vo thanh ghi W. Nu d= 1 th kt qu lu vo thanh ghi f.
34. Lnh: XORLW
lnh XOR hng s vi W
C php:
XORLW
k
Tc t:
0 k 255
Thc thi:
(W) XOR k (W)
C nh hng: Z.
Chu k thc hin: 1.
Chc nng: XOR ni dung thanh ghi W vi hng s k 8 bit, kt qu lu vo thanh ghi
W.
35. Lnh: XORWF
lnh XOR W vi f
C php:
XORLW
f,d
Tc t:
0 f 127, d [0,1]
Thc thi:
(W) XOR (f) (dest).
C nh hng: Z
Chc nng: XOR ni dung thanh ghi W vi ni dung thanh ghi f. Nu d= 0 th kt qu
c lu vo thanh ghi W. Nu d= 1 th kt qu lu vo thanh ghi f.
III. CU HI N TP TRC NGHIM - BI TP

1.
CU HI N TP
Cu s 3-1:
Hy cho bit cc kiu nh a ch ca vi iu khin PIC16F887.
Cu s 3-2:
Hy cho bit cc nhm lnh ca vi iu khin PIC16F887.
2.
CU HI M RNG
Chng 3. Lenh hp ng.
31
Nguyen nh Phu
Cu s 3-3:
Hy tm hiu lnh so snh cu trc CISC v RISC.
Cu s 3-4:
Hy tm cu trc ng ng lnh.
CU HI TRC NGHIM
3.
Cu 3-1:
Tp lnh ca PIC 16F877A gm:
(a) Lnh x l bit

(c) Lnh x l byte
Cu 3-2:
M lnh ca PIC 16F877A c chiu di:
(a) 12 bit
(c) 14 bit
Cu 3-3:
(a)
(c)
Cu 3-7:
(a)
(c)
Cu 3-8:
(b) Cho bit ni nhn d liu

(d) L a ch ca 1 bit
K hiu b trong tp lnh ca PIC 16F877A c chiu di:

3 bit
7 bit
(b) 1 bit
(d) 14 bit
K hiu f trong tp lnh ca PIC 16F877A c chiu di:

3 bit
7 bit
(b) 1 bit
(d) 14 bit
Lnh ADDLW k c chc nng:
(a) Cng W vi hng s k

(c) Cng W vi hng s l
Cu 3-9:
(b) L a ch ca 1 thanh ghi

(d) L a ch ca 1 bit
K hiu d trong tp lnh ca PIC 16F877A:
(a) L tn ca thanh ghi

(c) L hng s
Cu 3-6:
(b) L a ch ca 1 thanh ghi

(d) L a ch ca 1 bit
K hiu b trong tp lnh ca PIC 16F877A:

(c) L hng s
Cu 3-5:
(b) 13 bit
(d) 15 bit
K hiu f trong tp lnh ca PIC 16F877A:

(c) L hng s
Cu 3-4:
(b) Lnh x l hng s v iu khin

(d) Tt c u ng
(b) And W vi hng s k

(d) And W vi hng s l
Lnh ADDWF f, d c chc nng:
(a) Cng W vi hng s f

(c) Cng W vi nh f
(b) Cng W vi hng s d

(d) Cng f vi hng s d
Cu 3-10: Lnh BCF f, b c chc nng:

(a) Xa bit f trong thanh ghi b
(c) Lm bit f trong thanh ghi b ln 1
(b) Xa bit b trong thanh ghi f

(d) Lm bit b trong thanh ghi f ln 1
Cu 3-11: Lnh BSF f, b c chc nng:

(a) Xa bit f trong thanh ghi b
(c) Lm bit f trong thanh ghi b ln 1
(b) Xa bit b trong thanh ghi f

(d) Lm bit b trong thanh ghi f ln 1
Cu 3-12: Lnh BTFSS f, b c chc nng kim tra:

(a) Bit b trong thanh ghi f v nhy nu bng 1
(c) Bit b trong thanh ghi f v nhy nu bng 0
(b) Bit f trong thanh ghi b v nhy nu = 1

(d) Bit f trong thanh ghi b v nhy nu = 0
Cu 3-13: Lnh BTFSC f, b c chc nng kim tra:

(a) Bit b trong thanh ghi f v nhy nu bng 1
(c) Bit b trong thanh ghi f v nhy nu bng 0
32
(b) Bit f trong thanh ghi b v nhy nu = 1

(d) Bit f trong thanh ghi b v nhy nu = 0
Chng 3.Lenh hp ng
Nguyen nh Phu
Cu 3-14: Lnh DECF f, d c chc nng:

(a) Gim ni dung thanh ghi f
(c) Gim ni dung thanh ghi d
(b) Tng ni dung thanh ghi f

(d) Tng ni dung thanh ghi d
Cu 3-15: Lnh DECFSZ f, d c chc nng:

(a) Gim thanh ghi f v nhy nu Z=1
(c) Gim thanh ghi f v nhy nu d=0
(b) Gim thanh ghi f v nhy nu Z=0

(d) Gim thanh ghi f v nhy nu d=1
Cu 3-16: Lnh INCFSZ f, d c chc nng:

(a) Tng thanh ghi f v nhy nu Z=1
(c) Tng thanh ghi f v nhy nu d=0
4.
(b) Tng thanh ghi f v nhy nu Z=0

(d) Tng thanh ghi f v nhy nu d=1
BI TP
Chng 3. Lenh hp ng.
33
Chng 4
GII THIU
CC THNH PHN C BN CA NGN NG C
CC KIU D LIU CA BIN

CC TON T
CC LNH C C BN
CU TRC CA CHNG TRNH C
TRNH BIN DCH CCS-C

CU HI N TP
CU HI M RNG
CU HI TRC NGHIM
BI TP
Nguyen nh Phu
GII THIU
I.
Ngn ng lp trnh C l mt ngn ng lp trnh c s dng ph bin, l ngn ng to m hiu

qu, cc phn t lp trnh c cu trc, v mt tp hp phong ph cc ton t.
Ngn ng C mt ngn ng lp trnh thun tin v hiu qu, nhiu ng dng c th c gii
quyt d dng hn v hiu qu hn bng ngn ng C so vi cc ngn ng chuyn bit khc.
chng ny gii thiu cc ngn ng lp trnh C cho cc loi vi iu khin v cc lnh C c
bn phc v lp trnh cho cc ng dng. Do c nhiu h vi iu khin ca nhiu hng khc nhau
nn cc phn mm lp trnh C cho vi iu khin cng khc nhau, phn ny ch trnh by nhng kin
thc lp trnh C chung v c bn nht v ty thuc vo tng phn mm bin dch m cc bn tm hiu
thm.
Sau khi kt thc phn ny s gip cc bn bit cu trc mt chng trnh, bit cc lnh C c bn
lp trnh, bit khai bo cc kiu d liu cho cc bin, bit vit chng trnh.
II. CC THNH PHN C BN CA NGN NG C

1.
CC KIU D LIU CA BIN
Trong chng trnh thng khai bo bin lu d liu v x l d liu, ty thuc vo loi d
liu m ta phi chn loi d liu cho ph hp. Cc bin ca vi x l bao gm bit, byte, word v long
word tng ng vi d liu 1 bit, 8 bit, 16 bit v 32 bit.
Cc kiu d liu c bn ty thuc vo phn mm s dng, vi iu khin PIC c rt nhiu phn
mm bin dch nh PIC-C, MIKRO-C, MPLAB, trong phn ny trnh by phn mm PIC-C.
Bng 4-1: Cc kiu d liu ca phn mm PIC-C:
TT
1
2
3
4
Kiu d liu
Int1
signed char
unsigned char
signed int hay signed int8
S bit
1
8
8
8
Gii hn
01
-128127
0255
-128127
5
unsigned int hay unsigned int8 8
0255
6
signed int16
16
-3276832767
7
unsigned int16
16
065535
8
signed long long
32
-2147483648 to 2147483647
9
unsigned long long
32
0 to 4294967295
10
float
32
1.175494E-38 to 3.402823E+38
V d 4-1: Khai bo cc bin
Int1 TT;
//khai bo bin trng thi thuc kiu d liu bit.
Unsigned char dem; //khai bo bin m (dem) thuc kiu k t khng du 8 bit.
Ch : phn mm lp trnh PIC-C khng phn bit ch hoa hay ch thng nhng cc phn
mm khc th c phn bit.
2.
CC TON T
Cc ton t l thnh phn quan trng trong lp trnh, lp trnh th chng ta cn phi hiu r
rng chc nng ca cc loi ton t.
Bng 4-2: Cc ton t ph bin trong ngn ng C:
TT
1
2
3
36
Ton
t
+
+=
&=
Chc nng
V d
Ton t cng
Ton t cng v gn.
Ton t and v gn.
x+=y tng ng vi x=x+y

x&=y tng ng vi x=x&y
Chng 4.Ngon ng C.
Nguyen nh Phu
4
5
6
7
8
9
@
&
^=
^
|=
|
10
11
12
13
14
15
16
17
-/=
/
==
>
>=
++
*
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
!=
<<=
<
<<
<=
&&
!
||
%=
%
*=
*
~
>>=
>>
->
-=
sizeof
Ton t a ch
Ton t and
Ton t ex-or v gn.
Ton t ex-or
Ton t or v gn.
Ton t or nhiu i lng vi nhau thnh
1.
Gim
Ton t chia v gn.
Ton t chia
Ton t bng dng so snh
Ton t ln hn
Ton t ln hn hay bng
Tng
Ton t truy xut gin tip, i trc con
tr
Ton t khng bng
Ton t dch tri v gn
Ton t nh hn
Ton t dch tri
Ton t nh hn hay bng
Ton t and
Ton t ph nh (not)
Ton t or
Ton t chia ly s d v gn
Ton t module
Ton t nhn v gn
Ton t nhn
Ton t b 1
Ton t dch phi v gn
Ton t dch phi
Ton t con tr cu trc
Ton t tr v gn
Ton t tr
Xc nh kch thc theo byte ca ton t
x^=y tng ng vi x=x^y

x|=y tng ng vi x=x|y.
V d or nhiu bit trong 1 byte vi
nhau
x/=y tng ng vi x=x/y
x << = y tng ng vi x=x<<y
x % = y tng ng vi x=x%y
x * = y tng ng vi x=x*y
x >> = y tng ng vi x=x>>y
x - = y tng ng vi x=x-y
a.
Ton t gn (=)
Dng gn mt gi tr no cho mt bin
V d 4-2: A = 5; Gn bin A bng 5
V d 4-3: A = 2+ (B = 5);
C chc nng gn bin b bng 5 ri cng vi 2 v gn cho bin A, kt qu B = 5 v A = 7.
b.
Ton t s hc (+, -, *, /, %)
C 5 ton t thc hin cc php ton cng, tr, nhn, chia v chia ly phn d.
V d 4-4:
A = 24;
B = A % 5;
Gn A bng 24, B gn s d ca A chia cho 5, kt qu B bng 4
Chng 4. Ngon ng C.
37
Nguyen nh Phu
V d 4-5:
A=123;
X = A%10;
//X=3
A= A/10;
//A = 12
Y = A%10;
//Y=2
Z = A/10;
//Z=1
V d ny c chc nng tch tng con s n v, chc, trm gn cho 3 bin x, y, z.
Cc lnh trn c th vit gn li nh sau:
X = A%10;
//X=3
Y = A/10%10;
//Y=2
Z = A/100;
//Z=1
V d 4-6:
A=1234;
X = A%10;
//X=4
A= A/10;
//A = 12
Y = A%10;
//Y=3
A= A/10;
//A = 12
Z = A%10;
//Z=2
V = A/10;
//V=1
V d ny c chc nng tch tng con s n v, chc, trm, ngn gn cho 4 bin x, y, z, v.
Cc lnh trn c th vit gn li nh sau:
X = A%10;
//X=3
Y = A/10%10;
//Y=2
Z = A/100%10;
//Z=1
V = A/1000;
//V=1
c.
Ton t gn phc hp (+=, -=, *=, /=, %=, >>=, <<=, &=, ^=, |=)
Tng qut cho ton t gn phc hp: bin += gi_tr tng ng vi bin = bin + gi_tr.
V d 4-7:
A+=5; tng ng vi A = A +5;
A /= 5; tng ng A = A / 5;
B *= X + 1; tng ng B = B * (X+1);
d.
Ton t tng v gim (++, --)
Tng qut cho ton t gn phc hp: bin += gi_tr tng ng vi bin = bin + gi_tr.
V d 4-8:
A++; tng ng vi A = A +1 hay A+=1;
V d 4-9:
B = 3;
gn B bng 3
A=++B;
kt qu A bng 4, B bng 4
V d 4-10:
B = 3;
gn B bng 3
A=B++;
kt qu A bng B v bng 3, B tng ln 1 bng 4
S khc nhau l ++ t trc th tnh trc ri mi gn, t sau th gn trc ri mi tnh.
e.
Ton t quan h (==, !=, > , <, >=, <=)
Cc ton t quan h dng so snh cc biu thc, kt qu so snh l ng hoc sai.
Cc ton t trn tng ng l bng, khc, ln hn, nh hn, ln hn hay bng, nh hn hay
bng.
V d 4-11:
if (X<100)
X+=1;
Lnh trn kim tra nu X cn nh hn 100 th tng X ln 1.
f.
Ton t logic (!, && ,||)
Cc ton t trn tng ng l NOT, AND v OR.
V d 4-12:
!true s cho kt qu l false
38
Chng 4.Ngon ng C.
Nguyen nh Phu
((5==5) && (6>4)) and 2 iu kin li vi nhau v kt qu l true.

g.
Ton t x l bit (&, |,^, ~, <<, >>)
Cc ton t x l bit vi bit, cc ton t trn tng ng l AND, OR, XOR, NOT, SHL (dch
tri), SHR (dch phi).
V d 4-13:
A=0x77;
//gn A = 0111 0111B
B=0XC9;
//gn B = 1100 1001B
X = A & B; // X bng A and vi B, kt qu X = 0100 0001B = 0X41
Y = A | B;
// Y bng A or vi B, kt qu Y = 1111 1111B = 0XFF
Z = A ^ B;
// Z bng A xor vi B, kt qu Z = 1011 1110B = 0XBE
W = ~A;
// W bng not A, kt qu W = 1000 1000B = 0X88
V d 4-14:
A=0x01;
//gn A = 0000 0001B
A= (A <<1); //dch A sang tri 1 bit, kt qu A = 0000 0010B.
A= (A <<1); //dch A sang tri 1 bit, kt qu A = 0000 0100B.
Khi dch tri th bit bn tri mt, bit 0 thm vo bn phi.
V d 4-15:
A=0x81;
//gn A = 1000 0001B
A= (A >>1); //dch A sang phi 1 bit, kt qu A = 0100 0000B.
Khi dch phi th bit bn phi mt, bit 0 thm vo bn tri.
V d 4-16:
A=0x00 ;
//gn A = 0000 0000B
A= (A <<1) +0x01 ; //dch A sang tri 1 bit ri cng vi 1, kt qu A = 0000 0001B.
A= (A <<1) +0x01 ; //dch A sang tri 1 bit ri cng vi 1, kt qu A = 0000 0011B.
Khi dch tri v cng vi 1 th c chc nng y s 1 thm vo bn phi, vi d liu 8
bit th sau 8 ln s lp y 8 bit 1.
h.
Ton t ly kch thc chui theo bye ()
V d 4-17:
A = sizeof (charac); kt qu l A s cha s byte ca chui charac
3.
CC LNH C C BN
Thnh phn quan trng th 3 trong lp trnh C l cc lnh ca ngn ng C, phn tip theo s
kho st cc lnh c bn.
a.
Lnh if v else:
Chc nng: kim tra iu kin nu tha th lm.
C php: if (iu_kin)
{
Lnh 1;
Lnh 2;
}
else
{
Lnh 3;
Lnh 4;
}
V d 4-18:
if (x==50)
x=1;
Chng 4. Ngon ng C.
39
Nguyen nh Phu
else
x=x+1;
b.
Lnh lp while:
Chc nng: lp li mt thao tc vi mt s ln nht nh hoc khi cn tha 1 iu kin no .
C php: while (iu_kin)
{
Lnh 1;
Lnh 2;
}
V d 4-19:
while (x > 0)
{x = x - 1 ;}
c.
Lnh lp do while:
Chc nng: lm cc lnh trong du ngoc v thot nu iu kin theo sau lnh while khng ng.
C php: do
{
Lnh 1;
Lnh 2;
}
while (iu_kin)
V d 4-20:
Do
{x=x+10;}
while (x < 100)
Thc hin lnh x bng x cng vi 10, lm cho n khi x nh hn 100.
d.
Lnh lp for:
Chc nng: lm cc lnh trong du ngoc mt s ln nht nh.
C php: for (gi_tr_bt_u; iu_kin_kt_thc; tng_gi_tr )
{
Lnh 1;
Lnh 2;
}
V d 4-21:
For (int n = 0; n <100; n++)
{x=x+10;}
Vng lp thc hin vi bin n bng 0 cho n khi n bng 100 th ngng.
e.
Lnh r nhnh break:
Chc nng: Lnh ny dng thot khi vng lp d cho iu kin kt thc cha tha mn.
f.
Lnh continue:
Chc nng: Lnh ny dng kt thc phn cn li ca vng lp lm ln lp tip theo.
g.
Lnh r nhnh goto:
Chc nng: Lnh ny dng nhy n nhy trong chng trnh.
h.
Lnh switch case:
Chc nng: thc hin 1 cng vic ty thuc vo hm.
C php: switch (cmd)
{
Case constant1: Lnh a1;
Lnh a2;
Break;
40
Chng 4.Ngon ng C.
Nguyen nh Phu
Case constant2:
Lnh b1;
Lnh b2;
Break;
Default:
Lnh c1;
Lnh c2;
Break;
}
V d 4-22:
switch (cmd)
{
Case 0: printf(cmd 0);
Break;
Case 1: printf(cmd 1);
Break;
Default: printf(bad cmd );
Break;
}
4.
CU TRC CA CHNG TRNH C

Chng trnh C n gin nh sau
/* my first C program*/
#INCLUDE <16F887.H>
#FUSES NOWDT, PUT, HS, NOPROTECT, NOLVP
VOID MAIN()
{
SET_TRIS_B(0x00);
//PORTB LA OUTPUT
OUTPUT_B(0x0F);
//4 LED TAT 4 LED SANG
WHILE(1)
{}
}
/* my first C program*/ l ch thch cho chng trnh nm trong cp du /* . */ hoc
nm sau //.
Lnh #include <16F887.H > c chc nng bo cho trnh bin dch bit chng trnh dng cc
thnh phn ca vi iu khin c trong file 16F887.H.
Tip theo l khai bo cu hnh ca vi iu khin.
VOID MAIN () cho bit bt u chng trnh chnh v cc lnh tip theo ca chng trnh
chnh nm trong cp du {}.
5.
CC THNH PHN CA CHNG TRNH C
Tt c cc chng trnh vit bng ngn ng C bao gm cc ch dn, cc khai bo bin, cc nh

ngha bin, cc biu thc, cc lnh v hm.
a.
Ch dn tin x l
C 2 ch dn l #define v #include.
Ch dn #define c chc nng thay th 1 on chui bng mt ch nh c bit no .
Ch dn # include c chc nng chn vo mt on lnh t 1 file khc vo trong chng trnh.
V d 4-23:
#define RW PIN_B1
Chng 4. Ngon ng C.
41
Nguyen nh Phu
#include <16F887.H>
Ch dn th nht c chc nng nh ngha bin RW l bit th 1 ca portB.
Ch dn th hai c chc nng khai bo chng trnh th vin ca vi iu khin 16F887.h
b.
Khai bo
Khai bo bin bao gm tn v thuc tnh, khai bo hm, khai bo hng. Khai bo bin ton cc
nm bn ngoi hm, khai bo bin cc b th nm bn trong hm.
c.
nh ngha gi tr cho bin
Dng thit lp gi tr cho 1 bin hoc 1 hm.
d.
Biu thc
L s kt hp ca ton t v tc t cho ra 1 kt qu duy nht.
e.
Hm
Mt hm bao gm cc khai bo bin, nh ngha gi tr, cc biu thc v cc lnh thc hin 1
chc nng c bit no .
6.
CON TR D LIU
Con tr d liu trong ngn ng C chnh l kiu truy xut gin tip dng thanh ghi, a ch ca
nh cn truy xut lu trong thanh ghi.
V d 4-24: khai bo con tr, gn a ch con tr v lu d liu:
unsigned char *pointer0 ;
//khai bo con tr
pointer0 = mem_address;
//gn a ch bt u ca vng nh cho con tr
*pointer0 = 0xFF;
7.
//lu gi tr 0xFF vo nh c a ch lu trong con tr.
KHAI BO MNG
V d 4-25: khai bo mng:
unsigned char ma7doan[] = {0XC0,0XF9,0xA4,0XB0,0X99,0X92,0X82,0XF8,0X80,0X90} ;
char chuoi_hien_thi = {HELLO ! } ;
III. TRNH BIN DCH CCS-C

Trnh bin dch PIC-C dng bin dch tp tin m ngun C cho h vi iu khin PIC vi nhiu
chng loi khc nhau, lp trnh C chng ta c th s dng phn mm bin dch PIC-C, cch ci t,
lp trnh, bin dch v s dng bn c th tham kho ti liu thc hnh vi iu khin.
Khi lp trnh cho vi iu khin PIC dng PIC-C th cc thnh phn c bn cng ging nh cc
loi vi iu khin khc, s khc bit ch yu phn cng ca tng vi iu khin. Cc lnh lin quan
n phn cng c trnh by theo phn cng , khi kho st port th c cc lnh PIC-C lin quan n
port, khi kho st timer/counter th c cc lnh PIC-C lin quan n timer/counter.
Khi dng phn mm PIC-C lp trnh cho vi iu khin PIC16F887 th phi khai bo th vin
<PIC16F887.h>. Trong file ny nh ngha tn cc thnh phn ca vi iu khin, nu cc tn trong
file ny khng c th bn c th nh ngha thm, trong phn mm PIC-C c rt nhiu th vin h tr
cho cc ng dng gip bn vit chng trnh gn hn.
Ni dung ca file th vin:
//////// Standard Header file for the PIC16F887 device ////////////////
#device PIC16F887
#nolist
//////// Program memory: 8192x14 Data RAM: 367 Stack: 8
//////// I/O: 36 Analog Pins: 14
//////// Data EEPROM: 256
//////// C Scratch area: 77 ID Location: 2000
//////// Fuses: LP,XT,HS,EC_IO,INTRC_IO,INTRC,RC_IO,RC,NOWDT,WDT,NOPUT,PUT
42
Chng 4.Ngon ng C.
Nguyen nh Phu
//////// Fuses: NOMCLR,MCLR,NOPROTECT,PROTECT,NOCPD,CPD,NOBROWNOUT,BROWNOUT
//////// Fuses: BROWNOUT_NOSL,BROWNOUT_SW,NOIESO,IESO,NOFCMEN,FCMEN,NOLVP
//////// Fuses: LVP,NODEBUG,DEBUG,WRT,NOWRT,BORV40,BORV21
////////
////////////////////////////////////////////////////////////////// I/O
// Discrete I/O Functions: SET_TRIS_x(), OUTPUT_x(), INPUT_x(),
//
PORT_x_PULLUPS(), INPUT(),
//
OUTPUT_LOW(), OUTPUT_HIGH(),
//
OUTPUT_FLOAT(), OUTPUT_BIT()
// Constants used to identify pins in the above are:
#define
#define
#define
#define
#define
#define
#define
#define
PIN_A0
PIN_A1
PIN_A2
PIN_A3
PIN_A4
PIN_A5
PIN_A6
PIN_A7
40
41
42
43
44
45
46
47
#define
#define
#define
#define
#define
#define
#define
#define
PIN_B0
PIN_B1
PIN_B2
PIN_B3
PIN_B4
PIN_B5
PIN_B6
PIN_B7
48
49
50
51
52
53
54
55
#define
#define
#define
#define
#define
#define
#define
#define
PIN_C0
PIN_C1
PIN_C2
PIN_C3
PIN_C4
PIN_C5
PIN_C6
PIN_C7
56
57
58
59
60
61
62
63
#define
#define
#define
#define
#define
#define
#define
#define
PIN_D0
PIN_D1
PIN_D2
PIN_D3
PIN_D4
PIN_D5
PIN_D6
PIN_D7
64
65
66
67
68
69
70
71
#define
#define
#define
#define
PIN_E0
PIN_E1
PIN_E2
PIN_E3
72
73
74
75
////////////////////////////////////////////////////////////////// Useful defines

Chng 4. Ngon ng C.
43
Nguyen nh Phu
#define
#define
FALSE
TRUE
0
1
#define
#define
BYTE
BOOLEAN
int8
int1
#define
#define
#define
#define
#define
#define
#define
getc
fgetc
getchar
putc
fputc
fgets
fputs
getch
getch
getch
putchar
putchar
gets
puts
////////////////////////////////////////////////////////////////// Control
// Control Functions: RESET_CPU(), SLEEP(), RESTART_CAUSE()
// Constants returned from RESTART_CAUSE() are:
#define WDT_FROM_SLEEP 3
#define WDT_TIMEOUT 11
#define MCLR_FROM_SLEEP 19
#define MCLR_FROM_RUN 27
#define NORMAL_POWER_UP 25
#define BROWNOUT_RESTART 26
////////////////////////////////////////////////////////////////// Timer 0
// Timer 0 (AKA RTCC)Functions: SETUP_COUNTERS() or SETUP_TIMER_0(),
//
SET_TIMER0() or SET_RTCC(),
//
GET_TIMER0() or GET_RTCC()
// Constants used for SETUP_TIMER_0() are:
#define
T0_INTERNAL
0
#define
T0_EXT_L_TO_H
32
#define
T0_EXT_H_TO_L
48
#define
#define
#define
#define
#define
#define
#define
#define
#define
T0_DIV_1
T0_DIV_2
T0_DIV_4
T0_DIV_8
T0_DIV_16
T0_DIV_32
T0_DIV_64
T0_DIV_128
T0_DIV_256
8
0
1
2
3
4
5
6
7
#define
T0_8_BIT
#define
#define
#define
#define
#define
#define
#define
RTCC_INTERNAL
RTCC_EXT_L_TO_H
RTCC_EXT_H_TO_L
RTCC_DIV_1
RTCC_DIV_2
RTCC_DIV_4
RTCC_DIV_8
0
32
48
8
0
1
2
44
// The following are provided for compatibility

// with older compiler versions
Chng 4.Ngon ng C.
Nguyen nh Phu
#define
RTCC_DIV_16
#define
RTCC_DIV_32
#define
RTCC_DIV_64
#define
RTCC_DIV_128
#define
RTCC_DIV_256
#define
RTCC_8_BIT
3
4
5
6
7
0
// Constants used for SETUP_COUNTERS() are the above

// constants for the 1st param and the following for
// the 2nd param:
////////////////////////////////////////////////////////////////// WDT
// Watch Dog Timer Functions: SETUP_WDT() or SETUP_COUNTERS() (see above)
//
RESTART_WDT()
// WDT base is 18ms
//
#define
#define
#define
#define
#define
#define
#define
#define
WDT_18MS
WDT_36MS
WDT_72MS
WDT_144MS
WDT_288MS
WDT_576MS
WDT_1152MS
WDT_2304MS
8
9
10
11
12
13
14
15
// One of the following may be OR'ed in with the above:

#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
WDT_ON
WDT_OFF
WDT_DIV_16
WDT_DIV_8
WDT_DIV_4
WDT_DIV_2
WDT_TIMES_1
WDT_TIMES_2
WDT_TIMES_4
WDT_TIMES_8
WDT_TIMES_16
WDT_TIMES_32
WDT_TIMES_64
WDT_TIMES_128
0x4100
0
0x100
0x300
0x500
0x700
0x900 // Default
0xB00
0xD00
0xF00
0x1100
0x1300
0x1500
0x1700
////////////////////////////////////////////////////////////////// Timer 1
// Timer 1 Functions: SETUP_TIMER_1, GET_TIMER1, SET_TIMER1
// (or (via |) together constants from each group)
#define
T1_DISABLED
0
#define
T1_INTERNAL
5
#define
T1_EXTERNAL
7
#define
T1_EXTERNAL_SYNC 3
#define
T1_CLK_OUT
Chng 4. Ngon ng C.
45
Nguyen nh Phu
#define
#define
#define
#define
T1_DIV_BY_1
T1_DIV_BY_2
T1_DIV_BY_4
T1_DIV_BY_8
0
0x10
0x20
0x30
#define
T1_GATE
0x40
#define
T1_GATE_INVERTED
0xC0
////////////////////////////////////////////////////////////////// Timer 2
// Timer 2 Functions: SETUP_TIMER_2, GET_TIMER2, SET_TIMER2
#define
T2_DISABLED
0
#define
T2_DIV_BY_1
4
#define
T2_DIV_BY_4
5
#define
T2_DIV_BY_16
6
////////////////////////////////////////////////////////////////// CCP
// CCP Functions: SETUP_CCPx, SET_PWMx_DUTY
// CCP Variables: CCP_x, CCP_x_LOW, CCP_x_HIGH
// Constants used for SETUP_CCPx() are:
#define
CCP_OFF
0
#define
CCP_CAPTURE_FE
4
#define
CCP_CAPTURE_RE
5
#define
CCP_CAPTURE_DIV_4
6
#define
CCP_CAPTURE_DIV_16
7
#define
CCP_COMPARE_SET_ON_MATCH
8
#define
CCP_COMPARE_CLR_ON_MATCH
9
#define
CCP_COMPARE_INT
0xA
#define
CCP_COMPARE_RESET_TIMER
0xB
#define
CCP_PWM
0xC
#define
CCP_PWM_PLUS_1
0x1c
#define
CCP_PWM_PLUS_2
0x2c
#define
CCP_PWM_PLUS_3
0x3c
#word
CCP_1 =
getenv("SFR:CCPR1L")
#byte
CCP_1_LOW=
#byte
CCP_1_HIGH=
getenv("SFR:CCPR1H")
// The following should be used with the ECCP unit only (or these in)
#define
CCP_PWM_H_H
0x0c
#define
CCP_PWM_H_L
0x0d
#define
CCP_PWM_L_H
0x0e
#define
CCP_PWM_L_L
0x0f
#define
#define
#define
CCP_PWM_FULL_BRIDGE
CCP_PWM_FULL_BRIDGE_REV
CCP_PWM_HALF_BRIDGE
0x40
0xC0
0x80
#define
#define
#define
#define
#define
#define
#define
CCP_SHUTDOWN_ON_COMP1
CCP_SHUTDOWN_ON_COMP2
CCP_SHUTDOWN_ON_COMP
CCP_SHUTDOWN_ON_INT0
CCP_SHUTDOWN_ON_COMP1_INT0
CCP_SHUTDOWN_ON_COMP2_INT0
CCP_SHUTDOWN_ON_COMP_INT0
0x100000
0x200000
0x300000
0x400000
0x500000
0x600000
0x700000
46
Chng 4.Ngon ng C.
Nguyen nh Phu
#define
CCP_SHUTDOWN_AC_L
#define
CCP_SHUTDOWN_AC_H
#define
CCP_SHUTDOWN_AC_F
0x000000
0x040000
0x080000
#define
#define
#define
CCP_SHUTDOWN_BD_L
CCP_SHUTDOWN_BD_H
CCP_SHUTDOWN_BD_F
0x000000
0x010000
0x020000
#define
CCP_SHUTDOWN_RESTART
0x80000000
#define
#define
#define
#define
#define
CCP_PULSE_STEERING_A
CCP_PULSE_STEERING_B
CCP_PULSE_STEERING_C
CCP_PULSE_STEERING_D
CCP_PULSE_STEERING_SYNC
0x01000000
0x02000000
0x04000000
0x08000000
0x10000000
#word
CCP_2 =
#byte
CCP_2_LOW=
#byte
CCP_2_HIGH=
getenv("SFR:CCPR2H")
////////////////////////////////////////////////////////////////// SPI
// SPI Functions: SETUP_SPI, SPI_WRITE, SPI_READ, SPI_DATA_IN
// Constants used in SETUP_SPI() are:
#define
SPI_MASTER
0x20
#define
SPI_SLAVE
0x24
#define
SPI_L_TO_H
0
#define
SPI_H_TO_L
0x10
#define
SPI_CLK_DIV_4
0
#define
SPI_CLK_DIV_16
1
#define
SPI_CLK_DIV_64
2
#define
SPI_CLK_T2
3
#define
SPI_SS_DISABLED
1
#define
#define
SPI_SAMPLE_AT_END
SPI_XMIT_L_TO_H
0x8000
0x4000
////////////////////////////////////////////////////////////////// UART
// Constants used in setup_uart() are:
// FALSE - Turn UART off
// TRUE - Turn UART on
#define
UART_ADDRESS
#define
UART_DATA
#define
UART_AUTODETECT
#define
UART_AUTODETECT_NOWAIT
#define
UART_WAKEUP_ON_RDA
#define
UART_SEND_BREAK
////////////////////////////////////////////////////////////////// COMP
// Comparator Variables: C1OUT, C2OUT
// Constants used in setup_comparator() are:
//
2
4
8
9
10
13
#define
#define
0x00
0x00
NC_NC_NC_NC
NC_NC
Chng 4. Ngon ng C.
47
Nguyen nh Phu
//Pick one constant for COMP1

#define
CP1_A0_A3
#define
CP1_A1_A3
#define
CP1_B3_A3
#define
CP1_B1_A3
#define
CP1_A0_VREF
#define
CP1_A1_VREF
#define
CP1_B3_VREF
#define
CP1_B1_VREF
//Optionally OR with one or both of the following
#define
CP1_OUT_ON_A4
#define
CP1_INVERT
#define
CP1_ABSOLUTE_VREF
//OR with one constant for COMP2
#define
CP2_A0_A2
#define
CP2_A1_A2
#define
CP2_B3_A2
#define
CP2_B1_A2
#define
CP2_A0_VREF
#define
CP2_A1_VREF
#define
CP2_B3_VREF
#define
CP2_B1_VREF
#define
CP2_OUT_ON_A5
#define
CP2_INVERT
#define
CP2_ABSOLUTE_VREF
#define
CP2_T1_SYNC
#define
CP2_T1_GATE
#bit
C1OUT = 0x107.6
#bit
C2OUT = 0x108.6
////////////////////////////////////////////////////////////////// VREF
// Constants used in setup_vref() are:
//
#define
VREF_LOW
0xa0
#define
VREF_HIGH
0x80
// Or (with |) the above with a number 0-15
0x00090080
0x000A0081
0x00880082
0x00280083
0x00010084
0x00020085
0x00800086
0x00200087
0x00000020
0x00000010
0x20000000
0x00058000
0x00068100
0x00848200
0x00248300
0x00018400
0x00028500
0x00808600
0x00208700
0x00002000
0x00001000
0x10000000
0x01000000
0x02000000
////////////////////////////////////////////////////////////////// INTERNAL RC
// Constants used in setup_oscillator() are:
#define
OSC_31KHZ
1
#define
OSC_125KHZ
0x11
#define
OSC_250KHZ
0x21
#define
OSC_500KHZ
0x31
#define
OSC_1MHZ
0x41
#define
OSC_2MHZ
0x51
#define
OSC_4MHZ
0x61
#define
OSC_8MHZ
0x71
#define
OSC_INTRC
1
#define
OSC_NORMAL
0
48
Chng 4.Ngon ng C.
Nguyen nh Phu
// Result may be (ignore all other bits)
#define
OSC_STATE_STABLE 4
#define
OSC_31KHZ_STABLE 2
////////////////////////////////////////////////////////////////// ADC
// ADC Functions: SETUP_ADC(), SETUP_ADC_PORTS() (aka SETUP_PORT_A),
//
SET_ADC_CHANNEL(), READ_ADC()
// Constants used for SETUP_ADC() are:
#define
ADC_OFF
0
// ADC Off
#define
ADC_CLOCK_DIV_2
0x100
#define
ADC_CLOCK_DIV_8
0x40
#define
ADC_CLOCK_DIV_32
0x80
#define
ADC_CLOCK_INTERNAL
0xc0
// Internal 2-6us
// Constants used in SETUP_ADC_PORTS() are:

#define
sAN0
#define
sAN1
#define
sAN2
#define
sAN3
#define
sAN4
#define
sAN5
#define
sAN6
#define
sAN7
#define
sAN8
#define
sAN9
#define
sAN10
#define
sAN11
#define
sAN12
#define
sAN13
#define
NO_ANALOGS
#define
ALL_ANALOG
0x1F00FF
1
//| A0
2
//| A1
4
//| A2
8
//| A3
16
//| A5
32
//| E0
64
//| E1
128 //| E2
0x10000 //| B2
0x20000 //| B3
0x40000 //| B1
0x80000 //| B4
0x100000 //| B0
0x200000 //| B5
0
// None
// A0 A1 A2 A3 A5 E0 E1 E2 B0 B1 B2 B3 B4 B5
// One of the following may be OR'ed in with the above using |

#define
VSS_VDD
0x0000
#define
VSS_VREF
0x1000
#define
VREF_VREF
0x3000
#define
VREF_VDD
0x2000
// Constants used in READ_ADC() are:
#define
ADC_START_AND_READ
#define
DC_START_ONLY
#define
ADC_READ_ONLY
//| Range 0-Vdd

//| Range 0-Vref
//| Range Vref-Vref
//| Range Vref-Vdd
7 // This is the default if nothing is specified

1
6
////////////////////////////////////////////////////////////////// INT
// Interrupt Functions: ENABLE_INTERRUPTS(), DISABLE_INTERRUPTS(),
//
CLEAR_INTERRUPT(), INTERRUPT_ACTIVE(),
//
EXT_INT_EDGE()
// Constants used in EXT_INT_EDGE() are:
#define
L_TO_H
0x40
#define
H_TO_L
0
Chng 4. Ngon ng C.
49
Nguyen nh Phu
// Constants used in ENABLE/DISABLE_INTERRUPTS() are:

#define
GLOBAL
0x0BC0
#define
INT_RTCC
0x000B20
#define
INT_RB
0x01FF0B08
#define
INT_EXT_L2H
0x50000B10
#define
INT_EXT_H2L
0x60000B10
#define
INT_EXT
0x000B10
#define
INT_AD
0x008C40
#define
INT_TBE
0x008C10
#define
INT_RDA
0x008C20
#define
INT_TIMER1
0x008C01
#define
INT_TIMER2
0x008C02
#define
INT_CCP1
0x008C04
#define
INT_CCP2
0x008D01
#define
INT_SSP
0x008C08
#define
INT_BUSCOL
0x008D08
#define
INT_EEPROM
0x008D10
#define
INT_TIMER0
0x000B20
#define
INT_OSC_FAIL
0x008D80
#define
INT_COMP
0x008D20
#define
INT_COMP2
0x008D40
#define
INT_ULPWU
0x008D04
#define
INT_RB0
0x0010B08
#define
INT_RB1
0x0020B08
#define
INT_RB2
0x0040B08
#define
INT_RB3
0x0080B08
#define
INT_RB4
0x0100B08
#define
INT_RB5
0x0200B08
#define
INT_RB6
0x0400B08
#define
INT_RB7
0x0800B08
#list
IV. CU HI N TP TRC NGHIM - BI TP

1.
CU HI N TP
Cu s 4-1:
Hy cho bit loi d liu trong ngn ng lp trnh C cho vi iu khin.
Cu s 4-2:
Hy cho bit cc ton t trong trong ngn ng lp trnh C.
2.
CU HI M RNG
Cu s 4-3:
Hy tm hiu cc kiu b nh trong ngn ng lp trnh C ca vi iu ATMEGA128.
Cu s 4-4:
Hy tm trnh bin dch Mikro-C.
3.
CU HI TRC NGHIM
Cu 4-1:
Kiu d liu signed char l kiu:
(a) 8 bit
(c) 24 bit
Cu 4-2:
Gii hn ca kiu d liu signed char l:
(a) T 0 n 255
(c) T -256 n 255
50
(b) 16 bit
(d) 32 bit
(b) T 0 n 65535
(d) T -128 n 127
Chng 4.Ngon ng C.
Nguyen nh Phu
Cu 4-3:
Kiu d liu unsigned char l kiu:
(a) 8 bit
(c) 24 bit
Cu 4-4:
(b) %
(d) &
Ton t no l chia ly s d:
(a) =
(c) /
Cu 4-9:
(b) T 0 n 65535
(d) T -128 n 127
Ton t no l ton t gn:
(a) =
(c) /
Cu 4-8:
(b) 16 bit
(d) 32 bit
Gii hn ca kiu d liu unsigned int l:
(a) T 0 n 255
(c) T -256 n 255
Cu 4-7:
(b) T 0 n 65535
(d) T -128 n 127
Kiu d liu unsigned int l kiu:
(a) 8 bit
(c) 24 bit
Cu 4-6:
(b) 16 bit
(d) 32 bit
Gii hn ca kiu d liu unsigned char l:
(a) T 0 n 255
(c) T -256 n 255
Cu 4-5:
(b) %
(d) &
Ton t no l chia ly kt qu nguyn:
(a) =
(c) /
(b) %
(d) &
Cu 4-10: Ton t no l so snh xem c bng hay khng:

(a) =
(c) ==
(b) !=
(d) <=
Cu 4-11: Ton t no l so snh khng bng:

(a) =
(c) ==
(b) !=
(d) <=
Cu 4-12: Ton t no l so snh nh hn hoc bng:

(a) >=
(c) ==
(b) !=
(d) <=
Cu 4-13: Ton t no l AND 2 iu kin vi nhau:

(a) !
(c) &
(b) &&
(d) ||
Cu 4-14: Kiu d liu no l 32 bit:

(a) int
(c) unsigned int
(b) unsigned long

(d) signed int
Cu 4-15: Ton t no l OR 2 iu kin vi nhau:

(a) !
(c) &
(b) &&
(d) ||
Cu 4-16: Ton t no l ph nh d liu:

(a) !
(c) &
(b) ~
(d) |
Cu 4-17: Ton t no l ph nh iu kin:

Chng 4. Ngon ng C.
51
Nguyen nh Phu
(a) !
(c) &
(b) &&
(d) ||
Cu 4-18: Ton t no l AND 2 d liu:

(a) >>
(c) &
(b) ~
(d) |
Cu 4-19: Ton t no l dch tri d liu:

(a) <<
(c) &
(b) ~
(d) >>
Cu 4-20: Ton t ly kch thc theo byte:

(a) size
(c) sizeoff
(b) sizeof
(d) sizeon
Cu 4-21: Vng lp while(iu_kin) s lm khi iu kin:

(a) Ln hn 1
(c) Sai
(b) Nh hn 1
(d) ng
Cu 4-22: Vng lp for(i=1;i<10;i++) s thc hin cc lnh trong vng lp:

(a) 10 ln
(c) 9 ln
(b) 100 ln
(d) 99 ln
Cu 4-23: Ch dn #define c chc nng:

(a) Chn 1 on lnh t 1 file khc vo
(c) nh ngha 1 on chui
(b) Khai bo th vin ca vi iu khin

(d) Khai bo th vin ca C
Cu 4-24: Ch dn #include c chc nng:

(a) Chn 1 on lnh t 1 file khc vo
(c) Khai bo th vin
4.
52
(b) Khai bo th vin ca vi iu khin

(d) Tt c u ng
BI TP
Chng 4.Ngon ng C.
Chng 5
GII THIU
CHC NNG CC PORT CA VI IU KHIN
CC PORT CA PIC 16F887
LNH TRUY XUT PORT DNG NGN NG CCS-C
H THNG T PHM
H THNG NHIU PHM
CC NG DNG IU KHIN LCD
LNH SET_TRIS_X()
LNH OUTPUT_X()
LNH OUTPUT_HIGH(PIN)
LNH OUTPUT_LOW(PIN)
LNH OUTPUT_TOGGLE(PIN)
LNH OUTPUT_BIT(PIN,VALUE)
LNH VALUE=GET_TRIS_X()
LNH VALUE=INPUT(PIN)
LNH VALUE=INPUT_STATE(PIN)
LNH VALUE=INPUT_X()
LNH OUTPUT_DRIVE(PIN)
LNH OUTPUT_FLOAT(PIN)
LNH PORT_B_PULLUP()

CC NG DNG IU KHIN LED 7 ON TRC TIP
CC NG DNG IU KHIN LED 7 ON QUT
CC NG DNG GIAO TIP VI NT NHN, BN PHM
PORTA V THANH GHI TRISA

PORTB V THANH GHI TRISB
PORTC V THANH GHI TRISC
PORTD V THANH GHI TRISD
PORTE V THANH GHI TRISE
GII THIU LCD

S CHN LCD
S MCH GIAO TIP VI IU KHIN VI LCD
CC LNH IU KHIN LCD
A CH CA TNG K T TRN LCD
CC CHNG TRNH HIN TH TRN LCD
CU HI N TP
CU HI M RNG
CU HI TRC NGHIM
Nguyen nh Phu
I. GII THIU
chng ny kho st cc port xut nhp ca cc vi iu khin, cc lnh nh cu hnh cho
port v cc lnh xut nhp d liu cho port.
Sau khi kt thc chng ny th ngi c c th s dng c cc port iu khin cc i
tng nh led n, led 7 on, LCD, nhn tn hiu iu khin t nt nhn, bn phm ma trn, cc cm
bin.
II. CHC NNG CC PORT CA VI IU KHIN

Vi iu khin c cc port xut nhp d liu giao tip vi cc i tng iu khin. Tn hiu
iu khin t CPU gi ra port iu khin, ng thi c cc port nhn d liu v x l. Trong mt
h thng lun c cc tn hiu vo ra v nh h thng iu khin robo nh hnh sau:
Hnh 5-1: S kt ni port vi i tng iu khin.

Cc port ch to ra cc mc logic tng thch vi chun TLL, nu iu khin cc i tng cng
sut ln th phi thm mch giao tip.
III. CC PORT CA PIC 16F887

Vi iu khin PIC 16F887 c 5 port l portA, B, C, D v E, kh nng cp v nhn dng l 25mA.
Hnh 5-2: S kt ni port: xut nhp tn hiu iu khin.

Mi port ca vi iu khin PIC gm c thanh ghi port v thanh ghi nh hng cho port.
54
Chng 5. Giao tiep led, lcd, phm n, ma tran phm.
Nguyen nh Phu
Hnh 5-2 trnh by PORTA v thanh ghi nh hng TRISA. Bit ca thanh ghi nh hng TRIS
bng 0 th port c chc nng xut d liu, nu bng 1 th c chc nng nhp d liu.
Ch : '0' tng ng vi 'OUT', '1' tng ng vi 'IN'.
Phn tip s kho st chi tit tng port.
1.
PORTA V THANH GHI TRISA
PortA l port hai chiu 8 bit, thanh ghi nh hng l TRISA c chc nng nh cu hnh vo ra
cho cc bit xut nhp ca portA, bit nh hng bng 0 th port tng ng xut, bit bng 1 th bit tng
ng l nhp, portA v thanh ghi nh hng TRISA nh hnh 5-3:
PORTA
R/W(x)
R/W(x)
RA7
RA6
Bit 7
R/W(1)
TRISA
TRISA7
Bit 7
R/W(x)
RA5
R/W(x)
R/W(x)
R/W(x)
R/W(x)
R/W(x)
RA4
RA3
RA2
RA1
RA0
R/W(x): l cho php c/ghi v khi reset th khng xc nh

R/W(1)
TRISA6
R/W(1)
TRISA5
Bit 0
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
R/W(1): l cho php c/ghi v khi reset th bng 1
Bit 0
Hnh 5-3: PortA v thanh ghi nh hng port A.

Kho st cu hnh mch cho tng tn hiu.
Chn RA0/AN0/ULPWU/C12IN0-:
Chn RA1/AN1/C12IN1-:
C s mch nh hnh 5-4:
C s mch nh hnh 5-5:
C th nh cu hnh thc hin 1 trong cc
chc nng sau:
chc nng sau:
L tn hiu xut nhp s I/O.
L ng vo knh th 1 ca khi ADC.
L ng vo m th 1 ca b so snh C1, C2
L ng vo m th 0 ca b so snh C1, C2
L ng vo tng t nh thc CPU khi
ch ng
Chn RA2/AN2/VREF-/CVREF/C2IN+:
C s mch nh hnh 5-6:
Chn RA3/AN3/VREF+/ C1IN+

C s mch nh hnh 5-7:
55
Nguyen nh Phu
chc nng sau:
chc nng sau:

L ng vo in p tham chiu dng cho
L ng vo in p tham chiu m cho ADC
ADC
L ng vo in p tham chiu b so snh.
L ng vo dng ca b so snh C1
L ng vo dng ca b so snh C2
Chn RA4/T0CLI/C1OUT:
Chn RA5/AN4/ SS / C2OUT:

C s mch nh hnh 5-8:
C s mch nh hnh 5-9:
chc
nng
sau:
chc nng sau:
L ng vo nhn xung ngoi ca timer T0.
L ng vo chn t ca truyn d liu SPI.
L ng ra ca b so snh C1.
L ng ra ca b so snh C2.
Chn RA6/OSC2/CLKOUT:
Chn RA7/OSC1/CLKIN:
C s mch nh hnh 5-10:
chc nng sau:
chc nng sau:
L ni vi dao ng thch anh.
L ni vi dao ng thch anh.
L ng vo nhn xung clock.
L ng ra cp xung clock.
56
Nguyen nh Phu

2.
PORTB V THANH GHI TRISB:
PortB l port hai chiu 8 bit, thanh ghi nh hng l TRISB c chc nng nh cu hnh vo ra
cho cc bit xut nhp ca portB, bit nh hng bng 0 th port tng ng xut, bit bng 1 th bit tng
ng l nhp, portB v thanh ghi nh hng TRISB nh hnh 5-12:
PORTB
R/W(x)
R/W(x)
RB7
RB6
Bit 7
R/W(1)
TRISB
TRISB7
Bit 7
R/W(x)
RB5
R/W(x)
R/W(x)
RB4
RB3
R/W(x)
RB2
R/W(x)
RB1

R/W(1)
TRISB6
R/W(1)
TRISB5
R/W(x)
RB0
Bit 0
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
Bit 0
57
Nguyen nh Phu
Hnh 5-12: PortB v thanh ghi nh hng port B.

Cc chc nng tch hp ca portB
PortB c thm chc nng bo ngt khi portB c s thay i tn hiu v c in tr ko ln c th
lp trnh.
Chc nng tng t: PortB c a hp vi cc ng vo tng t ca khi ADC v ty chn tn
hiu s hay tng t ph thuc vo thanh ghi ANSELH, nu cho cc bit trong thanh ghi ANSELH
bng 1 th khi cc bit a hp cc knh tng t s ng vai tr l ng vo tng t.
Thanh ghi ANSELH (analog select high register) c cu trc nh hnh 5-13. Cc bit AN<13:8>
trong thanh ghi ANSELH nu bng 1 th chn nh cu hnh tng t, bng 0 th nh cu hnh s I/O.
U(0)
U(0)
R/W(1)
ANS13
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
ANS12
ANS11
ANS10
ANS9
ANS8
Bit 0
Bit 7
Hnh 5-13: Thanh ghi ANSELH nh cu hnh s tng t cho portB.

Chc nng in tr ko ln: mi bit ca PortB u c 1 in tr ko ln, 8 bit trong thanh ghi
WPUB s cho php /cm in tr ko ln. Khi port ng vai tr l ng ra th mch t ng tt ch
in tr ko ln. Sau khi reset th cm in tr ko ln do xa bit RBPU trong thanh ghi OPTION.
Thanh ghi WPUB (Weak Pull Up-Port B register) c cu trc nh hnh 5-14. Cc bit
WPUB<7:0> trong thanh ghi WPUB nu bng 1 th cho php in tr ko ln, bng 0 th khng cho
php ko ln.
R/W(1)
WPUB7
R/W(1)
WPUB6
R/W(1)
WPUB5
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
Bit 0
Bit 7
Hnh 5-14: Thanh ghi WPUB thit lp cho php/cm in tr treo.

Chc nng ngt khi c thay i: tt c cc bit ca PortB u c th nh cu hnh l ng vo
ngt khi c thay i trng thi logic. 8 bit trong thanh ghi IOCB s cho php hay cm chc nng ny.
Nguyn l thc hin chc nng ny nh sau: gi tr hin ti ca portB c so snh vi gi tr
trc cht ln c sau cng ca portB xc nh bit no thay i v bo ngt nu c s
thay i.
Ngt ny c th nh thc CPU khi ch ng. Ngi lp trnh phi xa ngt ny bng cch
thc hin 2 yu cu sau:
c gi tr ca portB th iu kin tng thch khng cn xy ra.
Xa c bo ngt RBIF. Do gi tr cht trc khng b nh hng bi reset CPU nn

sau khi reset th c bo ngt RBIF tip tc bng 1 nu vn cn s khng tng thch nu
khng c portB.
Thanh ghi IOCB (Interrupt On-Change Port B register) c cu trc nh hnh 5-15. Cc bit
IOCB<7:0> trong thanh ghi IOCB nu bng 1 th cho php ngt, bng 0 th cm.
R/W(0)
IOCB7
R/W(0)
IOCB6
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
Bit 0
Bit 7
Hnh 5-15: Thanh ghi IOCB cho php/cm ngt portB thay i.
58
Nguyen nh Phu
Chn RB0/AN12/INT:
Chn RB1/AN10/P1C/C12IN3-:
chc
nng
sau:
chc nng sau:
L
ng
ra
PWM
(ch
c
L ng vo ngt ngoi INT tc ng bng

PIC16F882/883/886).
cnh.
L ng vo m th 3 ca b so snh C1, C2.
Chn RB2/AN8/P1B:
Chn RB3/AN9/PGM/C12IN2-:
chc
nng
sau:
chc nng sau:
L ng vo cho php lp trnh ni tip in
L
ng
ra
PWM
(ch
c
p thp.
PIC16F882/883/886).
L ng vo m th 2 ca b so snh C1, C2.
Chn RB4/AN11/P1D:
Chn RB5/AN13/ T1G :

chc nng sau:
chc nng sau:
L ng vo cng ca Timer1.
L
ng
ra
PWM
(ch
c
PIC16F882/883/886).
Chn RB6/ICSPCLK:
Chn RB7/ ICSPDAT:
chc nng sau:
chc nng sau:
L ng d liu lp trnh ni tip cho b nh
L ng vo nhn xung clock lp trnh ni
chng trnh.
tip cho b nh chng trnh.
59
Nguyen nh Phu
60
Nguyen nh Phu

Ba chn RB3/PGM, RB6/ ICSPCLK v RB7/ICSPDA c a hp vi mch in g ri bn
trong v mnh lp trnh np chng trnh vo b nh ni. S kt ni mch np v mch g ri:
Hnh 5-18: Cc chn PortB giao tip vi mch np, g ri.

3.
PORTC V THANH GHI TRISC:
PortC l port hai chiu 8 bit, thanh ghi nh hng l TRISC c chc nng nh cu hnh vo ra
cho cc bit xut nhp ca portC, bit nh hng bng 0 th port tng ng xut, bit bng 1 th bit tng
ng l nhp, portC v thanh ghi nh hng TRISC nh hnh 5-19:
61
Nguyen nh Phu
PORTC
R/W(x)
R/W(x)
RC7
RC6
Bit 7
R/W(1)
TRISC
TRISC7
Bit 7
R/W(x)
RC5
R/W(x)
R/W(x)
R/W(x)
R/W(x)
R/W(x)
RC4
RC3
RC2
RC1
RC0

R/W(1)
TRISC6
R/W(1)
TRISC5
Bit 0
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Bit 0
Hnh 5-19: Port C v thanh ghi TRISC.

Chn RC0/T1OSO/T1CKI:
Chn RC1/T1OSI/CCP2:
chc nng sau:
chc nng sau:
L ng vo ca b dao ng Timer1.
L ng ra ca b dao ng Timer1.
L ng vo ca Capture v ng ra ca
L ng vo nhn xung ngoi ca Timer1.
Compare/PWM ca b so snh C2.
Chn RC2/P1A/CCP1:
Chn RC3/SCK/SCL:
chc
nng
sau:
chc nng sau:
L ng cp xung cho truyn d liu SPI.
L ng ra ca PWM.
L ng cp xung cho truyn d liu I2C.
L ng vo ca Capture v ng ra ca
Compare ca b so snh C1.
62
Nguyen nh Phu
Chn RC4/SDI/SDA:
Chn RC5/SDO:
chc
nng
sau:
chc nng sau:
L ng ra d liu cho truyn d liu SPI.
L ng vo d liu cho truyn d liu SPI.
L ng d liu cho truyn d liu I2C.
Chn RC6/TX/CK:
Chn RC7/RX/DT:
chc
nng
sau:
chc nng sau:
L ng vo nhn d liu cho truyn d liu
L ng ra pht d liu cho truyn d liu
ni tip bt ng b.
ni tip bt ng b.
L ng ra cp xung clock cho truyn d liu
L ng vo ra cho truyn d liu ni tip
63
Nguyen nh Phu
ng b.
ni tip ng b.

4.
PORTD V THANH GHI TRISD:
PortD l port hai chiu 8 bit, thanh ghi nh hng l TRISD c chc nng nh cu hnh vo ra
cho cc bit xut nhp ca portD, bit nh hng bng 0 th port tng ng xut, bit bng 1 th bit tng
ng l nhp, portD v thanh ghi nh hng TRISD nh hnh 5-28:
PORTD
R/W(x)
R/W(x)
RD7
RD6
Bit 7
R/W(1)
TRISD
TRISD7
Bit 7
R/W(x)
RD5
R/W(x)
R/W(x)
R/W(x)
R/W(x)
R/W(x)
RD4
RD3
RD2
RD1
RD0

R/W(1)
R/W(1)
TRISD6
TRISD5
Bit 0
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
Bit 0
Hnh 5-28: Port D v thanh ghi TRISD.

Chn RD<4 :0>:
S mch in ca cc chn t RC0 nh hnh 5-29: ch c chc nng l xut nhp s.
Chn RD5/P1B:
S mch in ca cc chn t RD5 nh hnh 5-30:
Chn ny c cu hnh thc hin 1 trong cc chc nng sau:
L ng ra ca PWM.
Chn RD6/P1C:
64

Nguyen nh Phu
L ng ra ca PWM (ch c PIC16F884/887).
Chn RD7/P1D:
L ng ra ca PWM (ch c PIC16F884/887).

5.
PORTE V THANH GHI TRISE:
PortE l port hai chiu 4 bit, thanh ghi nh hng l TRISE c chc nng nh cu hnh vo ra
cho cc bit xut nhp ca portE, bit nh hng bng 0 th port tng ng xut, bit bng 1 th bit tng
ng l nhp, portE v thanh ghi nh hng TRISE nh hnh 5-31:
U(0)
PORTE
Bit 7
U(0)
TRISE
Bit 7
U(0)
-
U(0)
U(0)
R/W(x)
R/W(x)
R/W(x)
R/W(x)
RE3
RE2
RE1
RE0

U(0)
-
U(0)
Bit 0
U(0)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
TRISE3
TRISE2
TRISE1
TRISE0
Bit 0
Hnh 5-31: Port E v thanh ghi TRISE.

Chn RE0/AN5:
Chn RE1/AN6:
chc nng sau:
chc nng sau:
L ng vo knh tng t th 6 ca ADC.
65
Nguyen nh Phu
Chn RE2/AN7:
Chn RE3/ MCLR /VPP:

chc
nng
sau:
chc nng sau:
L tn hiu xut nhp s I/O ty thuc vo
bit chn reset trong thanh ghi nh cu hnh.
L ng vo reset CPU.
L ng nhn in p lp trnh Vpp.
Hnh 5-32: Cu hnh chn RE<2:0>.
Hnh 5-33: Cu hnh chn RE<3>.
IV. LNH TRUY XUT PORT DNG NGN NG CCS-C

Cc lnh ca ngn ng lp trnh C lin quan n cc port bao gm:
o Lnh OUTPUT_FLOAT(pin): c chc nng th ni chn ca port.
o Lnh OUTPUT_LOW(pin): c chc nng cho 1 chn ca port xung mc 0.
o Lnh OUTPUT_HIGH(pin): c chc nng cho 1 chn ca port ln mc 1.
o Lnh OUTPUT_TOGGLE(pin): c chc nng o trng thi 1 chn ca port.
o Lnh OUTPUT_BIT(pin,value): c chc nng xut gi tr value ra 1 chn ca port.
o Lnh OUTPUT_X(value): c chc nng xut d liu 8 bit ra portX.
o Lnh SET_TRIS_X(value): c chc nng nh cu hnh cho portX.
o Lnh GET_TRIS_X(): c chc nng c gi tr nh cu hnh cho port gn cho bin.
o Lnh INPUT_X(): c chc nng c gi tr ca port gn cho bin.
o Lnh INPUT(pin):c chc nng c gi tr 1 chn ca port gn cho bin.
o Lnh PORT_A_PULLUPS(value): c chc nng treo in tr ca portA.
o Lnh PORT_B_PULLUPS(value):c chc nng treo in tr ca portB.
o Lnh INPUT_STATE(pin): c chc nng c trng thi 1 chn ca port.
o Lnh OUTPUT_DRIVE(pin): c chc nng nh cu hnh cho 1 chn ca port.
1.
LNH SET_TRIS_X()
C php:
Thng s:
Chc nng:
set_tris_x(value);
x l port A, B, C, D, E
value l 1 s nguyn 8 bit tng ng vi cc bit ca port I/O.
nh hng cho cc port I/O (TRI-State) l vo hay ra. Mi bit tng ng 1 chn. Mc
1 th chn tng ng l ng vo, mc 0 l ng ra.
C hiu lc: cho tt c cc vi iu khin PIC.
V d 5-1:
SET_TRIS_B (0x0F);
// 0F=00001111: B7- B4 l ng ra, B3-B0 l ng vo.
2.
66
LNH OUTPUT_X(VALUE)
Nguyen nh Phu
C php:
output_x (value)
Thng s:
value l hng s 8 bit kiu int
Chc nng:
Xut d liu 1 byte ra portx.
C hiu lc:
Lnh ny p dng cho tt c cc port.
V d 5-2:
OUTPUT_B(0xF0); xut d liu F0 ra portB
3.
LNH OUTPUT_HIGH(PIN)
output_high(pin);
tng ng lnh
BSF PORTX,B
pin l chn xut d liu - hy xem file nh ngha ca thit b "device.h" bit tn
chnh xc.
Chc nng: lm 1 chn ca port ln mc cao.
C hiu lc: lnh ny p dng cho tt c cc thit b.
V d 5-3:
OUTPUT_HIGH(PIN_A0); // lm cho chn RA0 ca port A ln 1
C php:
Thng s:
4.
LNH OUTPUT_LOW(PIN)
output_low(pin);
tng ng lnh
BCF PORTX,B
chnh xc.
Chc nng: lm 1 chn ca port xung mc thp.
V d 5-4:
output_low(pin_a0); // lm cho chn RA0 ca PortA xung mc 0
C php:
Thng s:
5.
LNH OUTPUT_TOGGLE(PIN)
C php:
Thng s:
output_toggle(pin);
chnh xc.
Chc nng: lm o trng thi 1 chn ca port.
V d 5-5:
OUTPUT_TOGGLE(PIN_B0); // o trng thi chn RB0 ca port B
6.
LNH OUTPUT_BIT(PIN,VALUE)
C php:
Thng s:
output_bit(pin,value);
chnh xc.
Chc nng: xut d liu 0 hoc 1 ra 1 chn ca port.
V d 5-6:
output_bit(pin_b0,0); // xut d liu 0 ra RB0
7.
LNH value = GET_TRIS_X()
C php:
value = get_tris_x();
Thng s:
khng c thng s
Kt qu tr v: l byte d liu nh cu hnh t thanh ghi TRIS
Chc nng: kt qu tr v l gi tr ca thanh ghi TRIS ca cc port A, B, C or D.
8.
LNH value = INPUT(pin)
C php:
value = input(pin);
Thng s:
pin l chn c - hy xem file nh ngha ca thit b "device.h" bit tn chnh xc
Kt qu tr v: 0 (or FALSE) nu chn mc thp, 1 (or TRUE) nu chn mc cao.
67
Nguyen nh Phu
Chc nng: c d liu 1 bit t 1 chn ca port, chn ny phi cu hnh l chn vo.
V d 5-7:
while (! Input (PIN_B1));
//i cho n khi chn Rb1 ln mc cao
If (input(PIN_A0))
Printf(A0 is now high \r\n);
Int16 i = PIN_B1
Whiel (!i);
//i chn RB1 ln mc cao
9.
LNH INPUT_STATE()
C php:
Thng s:
Tr v:
value = input_state(pin);
pin l chn c - hy xem file nh ngha ca thit b "device.h" bit tn chnh xc
kt qu c bng 1 nu chn c mc cao, kt qu c bng 0 nu chn c mc
thp.
Chc nng: lnh c mc logic ca 1 chn nhng khng lm thay i hng ca chn.
V d 5-8:
level = input_state(pin_A3);
10.
Value = INPUT_X()
C php:
value = input_x();
Thng s:
khng c.
Kt qu tr v: l d liu 8 bit ca portx.
Chc nng: lnh c mc logic ca 1 chn nhng khng lm thay i hng ca chn.
11.
LNH OUTPUT_DRIVE(PIN)
C php:
Thng s:
Tr v:
Chc nng:
C hiu lc:
V d 5-10:
12.
output_drive(pin);
pin l chn c nh ngha trong file "device.h".
khng c.
thit lp chn (pin) l ch xut.
lnh ny p dng cho tt c cc thit b.
output (pin_A0);
LNH OUTPUT_FLOAT(PIN)
C php:
Thng s:
Tr v:
Chc nng:
output_float(pin);
pin l chn c nh ngha trong file "device.h".
khng c.
thit lp chn (pin) l ch nhp v th ni chn tn hiu ny thit b khc bn
ngoi ton quyn iu khin chn ny a d liu vo vi iu khin.
V d 5-11: if ((data & 0x80) == 0)
Output_low (pin_A0);
else
output_float (pin_A0);
13.
LNH PORT_B_PULLUP( )
C php:
Thng s:
Tr v:
Chc nng:
68
port_b_pullup(value);
value c 2 gi tr l true v false.
khng c.
thit lp port B treo ln ngun qua in tr ko ln bn trong. Nu value l true th treo
ln ngun, nu l false th khng treo.
Nguyen nh Phu

V d 5-12: port_b_pullup(false);
V.

Bi 5-1: Dng vi iu khin 16F887 iu khin 8 led n sng tt.
S mch:
Hnh 5-34: S iu khin led n.

Mch dng portD kt ni vi 8 led n. Mc logic 0 lm led tt, mc logic 1 lm led sng, in
p ca led l 2V, dng qua led chn 10mA, in tr hn dng cho led c tnh nh sau:
V VLED 5V 2V
R CC
300
I LED
10mA
C th dng in tr 300 hoc 330.
Mch s dng thch anh c tn s 20MHz, c nt nhn reset, in tr reset 10k v c
pinheader 5 chn dng kt ni vi mch np ni tip.
Lu :
BEGIN
8 LED sng, delay
8 LED tt, delay
Hnh 5-35: Lu iu khin led n chp tt.
Chng trnh:
#INCLUDE <16F887.H>
#FUSES NOWDT, PUT, HS, NOPROTECT, NOLVP
#USE DELAY(CLOCK=20M)
VOID MAIN()
{
SET_TRIS_D(0x00);
WHILE(TRUE)
{
OUTPUT_D(0xFF);
DELAY_MS(1000);
69
Nguyen nh Phu
OUTPUT_D(0x00);
DELAY_MS(1000);
}
}
Gii thch chng trnh:

Hng th nht #INCLUDE <16F887.H> l khai bo th vin ang s dng l PIC 16F887.
Hng th hai #FUSES NOWDT, PUT, HS, NOPROTECT, NOLVP l khai bo cu hnh cho PIC.
Hng th ba #USE DELAY(CLOCK=20M) khai bo tn s t thch anh m vi iu khin s
dng, vi khai bo trn th tn s s dng l 20MHz.
Cc hm nh thi l:
o DELAY_MS(VALUE)
- Thi gian nh thi l mili giy.
o DELAY_US(VALUE)
- Thi gian nh thi l S.
Chng trnh chnh gm: Lnh SET_TRIS_D(0x00); c chc nng khi to portD l port xut.
Lnh OUTPUT_D(0xFF); c chc nng xut d liu 0xFF ra portD lm 8 led sng, tin hnh
gi hm delay, sau xut d liu 0x00 ra portD lm 8 led tt, gi hm delay v lp li.
Cc thng s cu hnh: NOWDT l khng s dng b nh thi gim st (No watchdog timer),
PUT l s dng b nh thi khi c ngun ko di them thi gian reset vi iu khin ch
ngun in n nh, thi gian ko di them 72ms (Power up timer), HS l s dng b dao ng tn
s cao t 4MHz n 20MHz (High Speed), NOPROTECT l khng s dng bo v m code np vo
b nh flash bn trong, NOLVP l khng s dng ch np code dng ngun in p thp 5V m
dng ngun 12,5V.
Bi 5-2: Dng vi iu khin 16F887 iu khin 8 led n sng tt 10 ln ri tt lun.
S mch: ging hnh 5-34.

Lu :
BEGIN
THC HIN VNG LP 10 LN:

TT 8 LED, DELAY
SNG 8 LED, DELAY
NGNG
Hnh 5-36: Lu iu khin led n chp tt 10 ln.
Chng trnh:
#INCLUDE <16F887.H>
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
UNSIGNED INT8 I;
VOID MAIN()
{ SET_TRIS_D(0x00);
FOR(I=0;I<10;I++)
{
OUTPUT_D(0xFF); DELAY_MS(1000);
OUTPUT_D(0x00); DELAY_MS(1000);
}
WHILE(TRUE){}
}
Gii thch chng trnh:

Chng trnh ny cho vng lp for thc hin 10 ln iu khin 8 led chp tt, sau thc hin
lnh while(1) v khng c lnh no trong vng lp nn xem nh nhy ti ch.
70
Nguyen nh Phu
Bi 5-3: Dng vi iu khin 16F887 iu khin 8 led n sng dn tt dn t phi sang tri.
S mch: ging hnh 5-34.

Lu :
BEGIN

DCH BIT 1 VO LM LED SNG DN

DCH BIT 0 VO LM LED TT DN
Hnh 5-37: Lu iu khin led n sng dn tt dn t phi sang tri.
Chng trnh:
#INCLUDE <16F887.H>
UNSIGNED INT8 I, X;
VOID MAIN()
{ SET_TRIS_D(0x00); X=0X00; OUTPUT_D(X); DELAY_MS(500);
WHILE(TRUE)
{ FOR (I=0;I<8;I++)
{ X = (X<<1)+0X01; OUTPUT_D(X); DELAY_MS(500);}
FOR (I=0;I<8;I++)
{ X = (X<<1);
OUTPUT_D(X); DELAY_MS(500);}
}
}
Gii thch chng trnh:

Khi to portD l xut d liu, gn bin X bng 0x00, xut gi tr ca X ra portD lm 8 led tt,
delay.
Vng lp for th nht thc hin 8 ln: tin hnh xoay tri d liu ca X v cng vi 0x01. Khi
xoay tri d liu th s 0 c y vo, cng vi 0x01 l y s 1 vo X. D liu bin X c xut
ra portD iu khin led sng dn, sau 8 ln th X s bng 1111_1111 8 led sng ht.
Vng lp for th hai thc hin 8 ln: tin hnh xoay tri d liu ca X. Khi xoay tri d liu th
s 0 c y vo. D liu bin X c xut ra portD iu khin led tt dn, sau 8 ln th X s bng
0000_0000 8 led tt ht.
Sau lp li c th 8 led sng dn xong ri tt dn.
Bi tp 5-1: Hy vit chng trnh iu khin 1 led n L00 ca mch in hnh 5-34 sng 1
giy tt 1 giy, cc led cn li khng nh hng.
Bi tp 5-2: Hy vit chng trnh iu khin 8 led n ca mch in hnh 5-34 sng dn ln
v tt dn t phi sang tri, sau sng dn v tt dn t tri sang. Cc bc thc hin gm vit lu
v chng trnh.
71
Nguyen nh Phu
Bi tp 5-3: Hy vit chng trnh iu khin 16 led n sng dn ln v tt dn t phi sang

tri dng 2 port B v D, thi gian tr 1 giy. Cc bc thc hin gm v mch, vit lu v chng
trnh.
VI. CC NG DNG IU KHIN LED 7 ON TRC TIP

Bi 5-4: Dng vi iu khin 16F887 kt ni vi 1 led 7 on anode chung v vit chng trnh
m t 0 n 9 vi thi gian tr tu chn.
S mch: dng portB kt ni vi 1 led 7 on anode chung. Mc logic 1 lm led tt,

mc logic 0 lm led sng, in tr hn dng cho led l 330.
Hnh 5-38: S kt ni portB vi 1 led 7 on.
M 7 on:
Led 7 on v tn cc on nh hnh 5-39:
Hnh 5-39: Hnh led 7 on.

Bng 5-1: M 7 on cho cc s thp phn:
TP
SO NH PHAN
HEX
7
6 5 4 3 2 1 0
DP G F E D C B A
1 1 0 0 0 0 0 0
C0
72
F9
TP
SO NH PHAN
HEX
7 6 5 4 3 2 1 0
DP G F E D C B A
1 0 0 1 0 0 1 0
92
82
Nguyen nh Phu
A4
F8
B0
80
99
90
Lu :
BEGIN
LU 10 M 7 ON T 0 N 9

GII M 7 ON V HIN TH GI TR
M CA VNG LP
Hnh 5-40: Lu m t 0 n 9.
Chng trnh:
#INCLUDE <16F887.H>
CONST UNSIGNED CHAR MA7DOAN [10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,
0x80,0x90};
SIGNED INT DEM;
UNSIGNED INT MA_DEM;
VOID MAIN()
{ SET_TRIS_B(0x00);
WHILE(TRUE)
{ FOR (DEM=0;DEM<10;DEM++)
{
MA_DEM = MA7DOAN[DEM];
OUTPUT_B(MA_DEM);
DELAY_MS(300);
}
}
}
Gii thch chng trnh:

Sau cc lnh khai bo th vin, cu hnh v khai bo tn s s dng l khai bo mng cha m 7
on v cc bin m, bin cha m.
Chng trnh chnh khi to cc portB l xut, cho vng lp for vi bin DEM chy t 0 n
9, tin hnh gii m v gi m led 7 on tng ng vi bin DEM ra port hin th, delay v lp li.
Chng trnh trn c th vit gn hn nh sau:
#INCLUDE <16F887.H>
73
Nguyen nh Phu
0x80,0x90};
SIGNED INT DEM;
VOID MAIN()
{ SET_TRIS_B(0x00);
WHILE(TRUE)
{
OUTPUT_B(MA7DOAN[DEM]);
DELAY_MS(300);
}
}
}
Trong chng trnh xut m 7 on ca bin DEM ra portB hin th lun nn khng cn s
dng bin trung gian MA_DEM.
Trong chng trnh th cc hng khai bo loi vi iu khin, cu hnh, tn s clock v m 7 on
t thay i nn to thnh 1 file th vin < TV_16F887.C > lu cc khai bo nh sau:
#INCLUDE <TV_16F887.H>
0x80,0x90};
Khi chng trnh chnh c vit li nh sau:
#INCLUDE <TV_16F887.C>
SIGNED INT DEM;
VOID MAIN()
{ SET_TRIS_B(0x00);
WHILE(TRUE)
{ FOR (DEM=0; DEM<10; DEM++)
{
OUTPUT_B(MA7DOAN[DEM]);
DELAY_MS(300);
}
}
}
T y v sau ta s s dng th vin ny v c th b sung thm cc ni dung mi.
Bi tp 5-4: Hy vit chng trnh thc hin m t 9 xung 0.
Hy v mch bng Proteus v m phng.
Bi 5-5: Dng vi iu khin 16F887 kt ni vi 2 led 7 on anode chung v vit chng trnh
m t 00 n 99 vi thi gian tr tu chn.
74
S mch: dng portB v C kt ni vi 2 led 7 on anode chung.
Nguyen nh Phu
Hnh 5-41: S kt ni portB, C iu khin 2 led 7 on.
Lu :
BEGIN
LU 10 M 7 ON T 0 N 9

-TCH GI TR HNG N V, HNG
CHC CA BIN M VNG LP
-KT HP GII M V HIN TH
Hnh 5-42: Lu m t 00 n 99.
Chng trnh:
#INCLUDE<TV_16F887.C>
SIGNED INT DEM;
VOID MAIN()
{ SET_TRIS_B(0x00); SET_TRIS_C(0x00);
WHILE(TRUE)
{
OUTPUT_C(MA7DOAN[DEM/10]); //CHUC
OUTPUT_B(MA7DOAN[DEM%10]); //DONVI
DELAY_MS(300);
}
}
}
Gii thch chng trnh:
75
Nguyen nh Phu
Chng trnh chnh khi to cc portB v C l xut, cho vng lp for vi bin DEM chy t 0
n 99, tin hnh chia tch hng n v, hng chc ri gii m v gi ra port tng ng hin th,
delay.
Bi tp 5-5: Hy vit chng trnh thc hin m t 000 n 999 hin th trn 3 led 7 on, thi
gian tr tu chn. Cc bc thc hin bao gm: v mch, vit lu , vit chng trnh v m phng.
VII. CC NG DNG IU KHIN LED 7 ON QUT

Khi s led 7 on cn nhiu hn v d l 8 led th ta khng th kt ni trc tip 1 port iu khin
1 led v khng port. C nhiu phng php m rng iu khin c nhiu led nhng y
trnh by phng php qut 8 led dng 2 port.
Bi 5-6: Dng vi iu khin 16F887 kt ni vi 8 led 7 on anode chung theo phng php
qut v vit chng trnh hin th 8 s t s 0 n s 7 trn 8 led.
S mch:

Mch dng portB kt ni vi cc on a, b, c, d, e, f, g, dp v portD kt ni iu khin 8
transistor ng ngt.
Nguyn l qut 8 led: do 8 led ni song song cc on nn mi mt thi im bn ch xut 1
m 7 on ca led cn hin th ra portB ng thi bn xut m iu khin transistor ra portD cho
76
Nguyen nh Phu
php transistor ca led cn sng dn, thc hin delay mt khong thi gian ngn ri tt transistor
m v thc hin tng t cho led th 2, c th cho n led cui cng ri lp li.
Thi gian cho led sng tu thuc vo s lng led sao cho chu k qut tt c cc led nhanh hn
p ng tn s ca mt ta quan st th ta s nhn thy cc led sng ht.
Vi 8 led 7 on theo s trn th thi gian sng l 1/8 v thi gian tt l 7/8 th bn chn
chu k qut 8ms tng ng vi tn s 125Hz l ph hp, bn c th chn tn s cao hn.
u im phng php qut led: hin th c nhiu thng tin, mch n gin.
Khuyt im: chng trnh phi qut lin tc th led mi sng, do thi gian sng t, thi gian tt
nhiu nn led s sng m hn so vi phng php kt ni trc tip.
Gii php tng sng ca led: nu qut khong 4 led th led sng r, nu nhiu led hn th
nn gim in tr hn dng t 330 xung cn khong 220.
Cu hi: nu qut 16 led th bn s chn gii php no cho led sng?
Tr li: c 2 gii php: gii php th nht l kt ni ging nh s trn dng portB ni song
song cc on ca 16 led, dng 2 port iu khin 16 transistor cho php led sng.
Vi gii php ny th thi gian tt ca led l 15/16 thi gian qu ln led s m v c th nhp
nhy.
Gii php th hai l tch lm 2 nhm 8 led: dng port th nht iu khin cc on ca 8 led
nhm th nht, dng port th hai iu khin cc on ca 8 led nhm th hai, dng port th ba iu
khin 8 transistor iu khin chung 2 nhm, mi ln m 1 transistor dng chung cho c 2 led.
Vi gii php ny th thi gian tt ca led l 7/8 t hn gii php 1 nn led sng r hn.
Lu :
BEGIN
GI M S 0 RA PORT, CHO LED 0 SNG

DELAY1MS, TT LED 0
GI M S 1 RA PORT, CHO PHP LED 1 SNG
DELAY1MS, TT LED 1
GI M S 7 RA PORT, CHO PHP LED 7 SNG

DELAY1MS, TT LED 7
Hnh 5-44: Lu iu khin 8 led qut sng 8 s.
Chng trnh:
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
WHILE(TRUE)
{
OUTPUT_B(0xC0); OUTPUT_LOW(PIN_D0); DELAY_MS(1); OUTPUT_HIGH(PIN_D0);
OUTPUT_B(0XF9); OUTPUT_LOW(PIN_D1); DELAY_MS(1); OUTPUT_HIGH(PIN_D1);
OUTPUT_B(0XA4); OUTPUT_LOW(PIN_D2); DELAY_MS(1); OUTPUT_HIGH(PIN_D2);
77
Nguyen nh Phu
OUTPUT_B(0XB0);
OUTPUT_B(0x99);
OUTPUT_B(0X92);
OUTPUT_B(0X82);
OUTPUT_B(0XF8);
}
OUTPUT_LOW(PIN_D3); DELAY_MS(1);
OUTPUT_HIGH(PIN_D3);
Gii thch chng trnh:

Chng trnh chnh khi to 2 port B v D xut d liu. Lnh xut m 7 on ra portB v lnh
lm 1 bit ca portD xung mc 0 cho transistor dn, gi hm delay 1ms sau tt transistor v tin
hnh cho led tip theo.
Bi 5-7: Dng vi iu khin 16F887 kt ni vi 2 led 7 on anode chung theo phng php
qut v vit chng trnh m t 00 n 99 hin th trn 2 led 7 on qut, thi gian tr tu chn.
S mch: do m 2 s nn kt ni 2 led.
Lu :
BEGIN
LU 10 M 7 ON T 0 N 9

-TCH HNG N V, HNG CHC
CA BIN M VNG LP
- GII M
- HIN TH NHIU LN (DELAY)
Hnh 5-46: Lu m t 00 n 99 hin th trn 2 led qut.
Chng trnh:
UNSIGNED INT8 DEM, I;
78
Nguyen nh Phu
VOID HIENTHI_DELAY()
{
FOR (I=0;I<200;I++)
{
OUTPUT_B(MA7DOAN[DEM %10]);
DELAY_MS(1);
OUTPUT_B(MA7DOAN[DEM /10]);
DELAY_MS(1);
}
}
VOID MAIN()
{ SET_TRIS_B(0x00); SET_TRIS_D(0x00);
WHILE(TRUE)
{
FOR(DEM=0;DEM<100;DEM++)
{
HIENTHI_DELAY();
}
}
}
OUTPUT_LOW(PIN_D0);
OUTPUT_LOW(PIN_D1);
OUTPUT_D(0XFF);
Gii thch: vng lp for thc hin 100 ln t 00 n 99, ly gi tr m chia tch hng n
v, hng chc, gii m v gi ra port hin th.
Bi tp 5-6: Hy vit chng trnh thc hin m t 000 n 999 hin th trn 3 led 7 on kt
ni theo phng php qut, thi gian tr tu chn. Cc bc thc hin bao gm: v mch, vit lu ,
vit chng trnh v m phng.
VIII. CC NG DNG GIAO TIP VI NT NHN, BN PHM

Nt nhn, bn phm dng giao tip gia con ngi v mch in t iu khin, v d: bn
phm my tnh, bn phm in thoi, bn phm my bn xng du dng nhp s tin cn bn, s lt cn
bn my git t ng c bn phm chnh ch git, chn mc nc
C 2 dng giao tip vi iu khin vi bn phm, nt nhn:
H thng t phm: v d iu khin ng c bng 3 phm: start, stop, inv, ng h c 3
n 4 phm chnh thi gian.
H thng nhiu phm: bn phm my tnh, bn phm in thoi,
H THNG T PHM
1.
hiu giao tip vi iu khin vi bn phm ta kho st cc bi ng dng theo sau.

Bi 5-8: Dng vi iu khin 16F887 giao tip vi 8 led n v 2 nt nhn ON, OFF. Khi cp
in th 8 led tt, khi nhn ON th 8 led sng, khi nhn OFF th 8 led tt.
S mch:
79
Nguyen nh Phu
Hnh 5-47: S iu khin led v nt nhn.
Nguyn l hot ng ca phm nhn:

Hot ng ca 2 nt nhn: theo s kt ni trn th bnh thng 2 nt nhn h, 2 ng vo c 2
in tr ko ln ngun nn mc logic l 1.
Khi c ta nhn phm th ngn mch ng vo xung mass lm ng vo mc logic 0, khi nh
phm th ng vo tr v li mc logic 1.
Khi lp trnh ta kim tra xem c nhn phm hay khng bng cch kim tra mc logic nu bng 1
th khng nhn, bng 0 th c nhn.
Lu :
BEGIN
Khi to cc port
TT 8 LED
Nhn ON
SNG 8 LED
Nhn OFF
END
Hnh 5-48: Lu iu khin led n bng nt nhn ON-OFF.
Chng trnh:
#DEFINE ON
PIN_E0
#DEFINE OFF
PIN_E1
VOID MAIN()
80
Nguyen nh Phu
SET_TRIS_E(0xFF);
SET_TRIS_D(0x00); OUTPUT_D(0X00);
WHILE(TRUE)
{
WHILE (INPUT(ON));
OUTPUT_D(0XFF);
WHILE (INPUT(OFF));
OUTPUT_D(0X00);
}
}
Gii thch chng trnh:

Lnh SET_TRIS_E(0FF) c chc nng khi to portE l port nhp v ni vi 2 nt nhn.
Lnh SET_TRIS_D(0x00); c chc nng khi to portD l port xut v lnh
OUTPUT_D(0x00); c chc nng tt 8 led.
Lnh WHILE (INPUT(ON)); c chc nng kim tra nt nhn ON: nu bng 1 l khng nhn
phm ON th tip tc kim tra cho n khi nhn phm ON th vng lp while kt thc v thc hin lnh
xut d liu 0xFF ra portD lm 8 led sng,.
Lnh WHILE (INPUT(OFF)); c chc nng kim tra nt nhn OFF: nu bng 1 l khng nhn
phm OFF th tip tc kim tra cho n khi nhn phm OFF th vng lp while kt thc v thc hin
lnh xut d liu 0x00 ra portD lm 8 led tt.
Bi 5-9: Dng vi iu khin 16F887 giao tip vi 8 led n v 3 nt nhn ON, OFF, INV. Khi
cp in th 8 led tt, khi nhn ON th 4 led thp (D<3:0>) sng, khi nhn INV th o trng thi ca 8
led: 4 sng thnh tt, 4 tt thnh sng, khi nhn OFF th 8 led tt.
S mch:
Hnh 5-49: S iu khin led v 3 nt nhn.
Lu :
81
Nguyen nh Phu
BEGIN
Khi to cc port
TT 8 LED
Nhn ON
SNG 4 LED
Nhn OFF
Nhn INV
S
O 8 LED
Hnh 5-50: Lu iu khin led bng 3 nt ON-OFF-INV.
Chng trnh:
#DEFINE ON
PIN_E0
#DEFINE OFF
PIN_E1
#DEFINE INV
PIN_E2
UNSIGNED INT8 X=0;
VOID MAIN()
{
SET_TRIS_E(0xFF); X=0;
SET_TRIS_D(0x00); OUTPUT_D(X);
WHILE(TRUE)
{
WHILE (INPUT(ON));
X= 0X0F; OUTPUT_D(X);
DO
{
IF(!INPUT(INV))
{
X= ~ X;
OUTPUT_D(X);
}
}WHILE(INPUT(OFF));
OUTPUT_D(0X00);
}
}
Gii thch chng trnh:

Trong vng lp while(true) th lnh while tip theo kim tra c nhn nt ON hay khng? Nu c
nhn th cho 4 led sng, nu khng th ch nhn.
Lnh do while tin hnh nu c nhn nt INV th o gi tr 8 led, vng lp ch thot khi nhn
phm OFF.
82
Nguyen nh Phu
Bi 5-10: Dng vi iu khin 16F887 giao tip vi 8 led n v 3 nt nhn ON, OFF, INV. Khi
cp in th 8 led tt, khi nhn ON th 4 led thp (D<3:0>) sng, khi nhn INV th o trng thi ca 8
led: 4 sng thnh tt, 4 tt thnh sng, khi nhn OFF th 8 led tt. C chng di nt nhn INV.
Trong chng trnh ny khi chy thc t th do tc ca vi iu khin qu nhanh, khi nhn o
chiu th do thi gian nhn phm di nn vi iu khin thc hin o led lin tc, ta s nhn thy 8 led
sng lun cho n khi ta bung phm, hoc ta nhn nhanh th trng thi o ca led khng th xc nh
r rng.
xc nh r rng th phi chng di bng cch kim tra phm nhn, nu c th delay, ri x l
v kim tra bung phm.
Trong bi iu khin ch c phm INV gy ra nh hng nn lu v chng trnh x l phn
chng di v ch bung phm INV nh sau:
Lu : nh hnh 5-50.
CHNG DI
Nhn INV
DELAY 20MS
Nhn INV
O 8 LED
CH BUNG PHM
END
Hnh 5-51: Lu iu khin led c chng di phm INV.
Chng trnh:
#DEFINE ON
PIN_E0
#DEFINE OFF
PIN_E1
#DEFINE INV
PIN_E2
UNSIGNED INT8 X=0;
VOID CHONGDOI_INV ()
{
IF (!INPUT(INV))
{ DELAY_MS (20);
IF(!INPUT(INV))
{ {X = ~ X; OUTPUT_D(X);}
DO {}
WHILE (!INPUT(INV));
}
}
}
83
Nguyen nh Phu
VOID MAIN()
{
SET_TRIS_E(0xFF); X=0;
SET_TRIS_D(0x00); OUTPUT_D(X);
WHILE(TRUE)
{
WHILE (INPUT(ON));
X= 0X0F; OUTPUT_D(X);
DO
{
CHONGDOI_INV ();
}WHILE(INPUT(OFF));
OUTPUT_D(0X00);
}
}
Bi tp 5-7: Hy vit chng trnh iu khin 8 led n bng 2 nt nhn SANG, TAT. Khi nhn
nt SANG th 8 led sng dn t phi sang tri, mi ln nhn th 1 led sng, khi nhn nt TAT th 8 led
tt dn t tri sang phi, mi ln 1 led. Cc bc thc hin bao gm: v mch, vit lu , vit chng
trnh v m phng.
Bi 5-11: Mch m thi gian t 00 n 99, dng vi iu khin PIC 16F887 kt ni vi 2 led 7
on anode chung v 2 nt nhn Start, Stop. Vit chng trnh thc hin chc nng: khi cp in th
led hin th 00, khi nhn Start th mch m t 00 n 99, nu nhn Stop th ngng ti gi tr ang
m, nhn Start th m tip.
S mch:
Hnh 5-52: S kt ni 2 port iu khin 2 led 7 on, 2 nt nhn.
84
Lu :
Nguyen nh Phu
BEGIN
LU 10 M 7 ON T 0 N 9
VNG LP 100 LN:

-TCH HNG N V, HNG CHC
CA BIN M VNG LP
- GII M - HIN TH DELAY
- KIM TRA NHN ON, OFF V CH
THOT KHI BIN CHO PHP BNG 1
Hnh 5-53: Lu m c iu khin bng nt nhn Start-Stop.
Gii thch lu :
Bi ny ging bi m kho st, ch thm phn kim tra nt nhn, bin cho php ban u gn
bng 0 khng cho php m, chng trnh kim tra c nhn nt Start lm bin cho php bng 1 cho
php mch m. Nu nhn nt Stop s lm bin cho php bng 0, mch ngng ti gi tr ang m.
Chng trnh:
#INCLUDE
<TV_16F887.C>
#DEFINE START PIN_E0
#DEFINE STOP
PIN_E1
SIGNED INT8 DEM;
INT1 CHOPHEP = 0;
VOID MAIN()
{
SET_TRIS_E(0xFF);
SET_TRIS_C(0x00);
SET_TRIS_D(0x00);
CHOPHEP=0;
WHILE(TRUE)
{
FOR (DEM=0;DEM<100;DEM++)
{
OUTPUT_C(MA7DOAN[DEM %10]);
OUTPUT_D(MA7DOAN[DEM /10]);
DELAY_MS(500);
DO
{
IF (!INPUT(START))
{CHOPHEP=1;}
ELSE IF (!INPUT(STOP) )
{CHOPHEP=0;}
}WHILE(CHOPHEP==0);
}
}
}
Bi tp 5-8: Hy thm vo bi 5-11 mt nt nhn c tn l INV c chc nng o chiu m
ln, m xung. ang m ln nu nhn INV th s m xung t gi tr ang m, tng t khi ang
m xung m nhn INV th s m ln. Cc bc thc hin bao gm: v mch, vit lu , vit
chng trnh v m phng.
85
Nguyen nh Phu
2.
H THNG NHIU PHM
Vi cch 1 th mi phm s dng 1 ng vo kt ni, 16 phm s dng 16 ng vo nh vy s

dng rt nhiu ng tn hiu giao tip, cch kt ni dng t tn hiu hn l kiu ma trn phm.
Cch kt ni dng ma trn th 16 phm ch dng 8 tn hiu: 4 cho hng v 4 cho ct gi l ma
trn 44 s c 16 phm, ma trn 88 s c 64 phm.
Tng qut ma trn bn phm mn th s ng tn hiu bng m+n, s phm bng mn
u im ca cch kt ni theo dng ma trn l tit kim ng iu khin.
Khuyt im: chng trnh phc tp.
Kho st bn phm ma trn 44 = 16 phm:

S mch bn phm nh hnh 5-54:
VCC=1
0
H0
H1
H2
H3
C3
C2
C1
C0
Hnh 5-54: Bn phm ma trn 44.

Trong ma trn 44 th c 4 hng v 4 ct, hng c chn l tn hiu vo ct c chn l tn
hiu ra, hng th treo ln ngun Vcc qua in tr nn mc logic ca hng lun l mc 1.
Cc phm nhn thng h nn 4 hng lun mc 1 hay H3H2H1H0 =1111.
Ct l tn hiu ra nn chng ta iu khin xut d liu ra ct ty .
phn bit cc phm th mi phm c 1 tn c nh theo s thp lc phn t 0 n F.
xem c phm no nhn hay khng ta tin hnh qut tng ct bng cch cho 1 ct mc 0, 3
ct cn li mc 1 v kim tra tt c cc hng, nu tt c cc hng vn mc logic 1 tc l khng c
nhn phm, nu c 1 hng xung mc 0 th c nhn phm. C th nh sau:
Qut ct th 0:
Xut d liu ra ct l: C3C2C1C0 =1110 nh hnh 5-54, kim tra hng no bng khng?
Nu bng H0 = 0 th nhn phm s 0.
Nu khng c phm nhn no ct C0 c nhn th phi qut ct tip theo.
Qut ct th 1:
86

Nguyen nh Phu

VCC=1
0
3
1
H0
H1
H2
H3
C3
C2
C1
C0

Qut ct th 2:
Nu bng H2 = 0 th nhn phm s A.
Nu bng H3 = 0 th nhn phm s B.
0
H0
H1
H2
H3
C3
C2
C1
C0

Qut ct th 3:
Xut d liu ra ct l: C3C2C1C0 = 0111 nh hnh 5-57, kim tra hng no bng khng?
Nu bng H0 = 0 th nhn phm s C.
Nu bng H1 = 0 th nhn phm s D.
Nu bng H2 = 0 th nhn phm s E.
Nu bng H3 = 0 th nhn phm s F.
Nu khng c phm nhn no ct C3 n y xem nh kt thc.
VCC=1
0
H0
H1
H2
H3
C3
C2
C1
C0

87
Nguyen nh Phu
Tn cc phm chng ta phn bit, cn chng trnh phn bit cc phm bng m, mi phm c
1 m phm do phn mm lp trnh xy dng, n gin mi phm c t m nh sau :
Phm s 0 c m l 00H, phm s 1 c m l 01H, phm F c m l 0FH.
Hot ng qut bn phm c thc hin theo lu nh hnh 5-58.
QUET_MT_PHIM
MAQUETCOT={FE,FD,FB,F7}
CT=0, HNG=FF,
MAPHIM=FF
VNG LP VI BIN CHY L CT

XUT LN LT 4 MAQUETCOT RA CT
H0=0
S
HNG=0
H1=0
S
HNG=1
H2=0
S
HNG=2
H3=0
S
HNG=3
HNG =FF
S
MAPHIM=CT*4 + HNG
RETURN(MAPHIM)
Hnh 5-58: Lu qut bn phm ma trn 44.

Gii thch lu :
M qut ct l 4 bit thp bao gm cc trng thi: 1110B, 1101B, 1011B, 0111B kt hp
vi 4 bit cao ca hng lun l 1111B nn d liu kt hp theo byte vit dng s hex l FEH,
FDH, FBH, F7H.
Gn ct bt u t 0, hng gn bng FFH, m phm ban u gn bng FFH.
Xut ln lt tng m qut ct ra port qut phm, tin hnh kim tra tng hng xem hng no
bng 0 th phm tng ng c nhn. Khi ta gn gi tr tng ng cho tng hng.
88
Nguyen nh Phu
Cui cng kim tra hng xem c bng FFH hay khng, nu bng th khng phm no c nhn
trong lc thc hin chng trnh qut, thot vi m phm bng FFH, nu khc FFH th c nhn
phm, tin hnh tnh ton m phm v thot vi m phm l ca phm nhn.
Nu qut ct th 0 th ct bng 0, theo cng thc m phm s c gi tr t 0H n 3H.
Nu qut ct th 1 th ct bng 1, theo cng thc m phm s c gi tr t 4H n 7H.
Nu qut ct th 2 th ct bng 2, theo cng thc m phm s c gi tr t 8H n BH.
Nu qut ct th 3 th ct bng 3, theo cng thc m phm s c gi tr t CH n FH.
Khi qut phm th sinh ra hin tng di phm nn ta phi thc hin thm phn chng di.
KEY 4X4
MP1= HM QUET_MT_PHIM
MP1=FF
s
MP2= HM QUET_MT_PHIM
MP1 =MP2
S
RETURN(MP1)
Hnh 5-59: Lu qut bn phm ma trn 44 c chng di.

Trong lu ny gi hm qut phm ma trn 4x4, sau gn m phm cho bin MP1, kim tra
nu MP1 bng FFH th khng c nhn phm nn khng cn chng di v thot.
Nu c nhn th gi hm qut phm v gn m phm cho bin MP2, so snh 2 m phm: nu 2 m
phm bng nhau th c ngha l ta cha bung phm nhn nn quay li kim tra ch cho n khi ta
bung phm. Khi ta bung phm th 2 m phm s khc nhau v chng trnh s thot v tr v m
phm nhn ln u l MT1.
hiu chng trnh qut bn phm ma trn ta kho st bi ng dng theo sau.
Bi 5-12: Dng vi iu khin PIC 16F887 giao tip vi 1 led 7 on v ma trn phm 44. Vit
chng trnh qut bn phm ma trn, hin th tn ca phm trn led 7 on.
S mch:
89
Nguyen nh Phu
Hnh 5-60: Vi iu khin giao tip bn phm ma trn.

Trong s dng portB giao tip vi bn phm ma trn 44 v portD iu khin 1 led 7 on.
Lu :
BEGIN
LU 10 M 7 ON T 0 N 9,
KHI TO PORT
QUT PHM MA TRN, CHNG DI
C NHN
S
GII M HIN TH
Hnh 5-61: Lu qut hin th ma trn phm.
Chng trnh chnh:

#INCLUDE<TV_KEY4X4.C>
SIGNED INT8 MP;
VOID MAIN()
{
SET_TRIS_D(0x00); OUTPUT_D(0x7F);
SET_TRIS_B(0xF0); PORT_B_PULLUPS(0XF0);
WHILE(TRUE)
{
MP= KEY_4X4();
IF (MP!=0XFF)
{
OUTPUT_D(MA7DOAN[MP]);
}
}
}
90
Nguyen nh Phu
Chng trnh con qut phm: TV_KEY4X4.C

CONST UNSIGNED CHAR MAQUETCOT[4]= {0xFE,0xFD,0xFB,0xF7};
UNSIGNED INT QUET_MT_PHIM()
{ SIGNED INT8 MAPHIM,HANG,COT;
MAPHIM=HANG=0XFF;
FOR(COT=0;COT<4;COT++)
{
OUTPUT_B(MAQUETCOT[COT]);
IF
(!INPUT(PIN_B4))
{HANG=0; BREAK;}
ELSE IF (!INPUT(PIN_B5))
{HANG=1; BREAK;}
{HANG=2; BREAK;}
{HANG=3; BREAK;}
}
IF (HANG!=0XFF) MAPHIM = COT*4 + HANG;
RETURN(MAPHIM);
}
UNSIGNED INT KEY_4X4()
{ UNSIGNED INT8 MPT1,MPT2;
MPT1=QUET_MT_PHIM();
IF (MPT1!=0XFF)
{
DELAY_MS(10);
MPT1=QUET_MT_PHIM();
DO{MPT2=QUET_MT_PHIM();}
WHILE (MPT2==MPT1);
}
RETURN(MPT1);
}
Gii thch chng trnh chnh:

Cc lnh khi to portB, D v in tr ko ln, theo s th dng 4 in tr bn ngoi th
khng cn nhng nu ta dng bn phm 4x4 c sn cha c in tr th ta phi dng in tr ko ln
bn trong.
Lnh OUTPUT_D(0x7F); c chc nng lm du chm ca led 7 on sng bo hiu chng
trnh hot ng.
Lnh MP=KEY_4X4(); c chc nng gi chng trnh con qut phm ma trn c chng di.
Nu c nhn th tin hnh gii m 7 on v gi ra portD nhn thy m phm dng s hex. Cc m 7
on ca 16 s hex lu trong file th vin.
Nu khng nhn phm no th quay tr li ch nhn phm.
Gii thch chng trnh con:

Chng trnh con KEY_4x4 c chc nng gi chng trnh con qut phm v chng di.
Hai chng trnh con ny ging nh lu vit v gii thch.
Bi 5-13: Dng vi iu khin PIC 16F887 giao tip vi 2 led 7 on v ma trn phm 44. Vit
chng trnh qut bn phm ma trn, hin th m phm nhn v dch. Bt u th hin th du chm
led 7 on th 0, khi nhn phm bt k v d l 3 th du chm s dch sang led 7 on th 1, s 3 s
hin th led th 0, nu nhn tip phm s 5 th s 3 ca led th 0 s chuyn sang led th 1, s 5 s
hin th led th 0.
S mch:
91
Nguyen nh Phu
Hnh 5-62: Vi iu khin giao tip bn phm ma trn v 2 led 7 on.

Trong s dng portB giao tip vi bn phm ma trn 44, portC v D iu khin 2 led 7 on.
Lu :
BEGIN
LU 10 M 7 ON T 0 N 9,
KHI TO PORT
QUT PHM MA TRN, CHNG DI
C NHN
S
GII M HIN TH
Hnh 5-63: Lu qut ma trn phm v hin th m phm.
Chng trnh chnh:

#INCLUDE<TV_KEY4X4.C>
SIGNED INT8 MP, SOTHU1, SOTHU0;
VOID MAIN()
{
SET_TRIS_D(0x00);
SET_TRIS_C(0x00);
SET_TRIS_B(0xF0);
PORT_B_PULLUPS(0XF0);
SOTHU0=0X7F;
SOTHU1=0XFF;
OUTPUT_D(SOTHU0);
OUTPUT_C(SOTHU1);
WHILE(TRUE)
{
MP= KEY_4X4();
IF (MP!=0XFF)
{
SOTHU1=SOTHU0;
SOTHU0=MA7DOAN[MP];
OUTPUT_D(SOTHU0); OUTPUT_C(SOTHU1);
92
Nguyen nh Phu
}
}
}

Cc lnh khi to portB, C, D v in tr ko ln. Gn 2 bin s th 1 bng FFH, s th 0 bng
7FH khi gi ra portC v D th led th 1 tt, led th 0 sng du chm thp phn cho bit chng
trnh chy.
Gi chng trnh qut phm c chng di v kim tra m phm nu c nhn th tin hnh chuyn
m hin th ca led th 0 sang cho led th 1, gii m 7 on ca phm mi nhn, tin hnh gi 2 m ra
2 led.
Quay li lm tng t khi ta nhn cc phm khc.
Bi tp 5-9: Hy hiu chnh bi 5-13 sau cho chng trnh ch cho php nhn cc phm s thp
phn t 0 n 9. Cc bc thc hin bao gm: vit lu , vit chng trnh v m phng.
Bi tp 5-10: T bi tp 5-9 thm yu cu khi nhn phm C th c chc nng xo cc s ang
hin th v hin th li du chm thp phn. Cc bc thc hin bao gm: vit lu , vit chng trnh
v m phng.
Bi tp 5-11: T bi tp 5-10 thm yu cu khi nhn phm D th c chc nng xo b phm nhn
sau cng v hin th tr li 2 gi tr ca 2 led hin th trc . Cc bc thc hin bao gm: vit
lu , vit chng trnh v m phng.
Ch : ln u khi mi cp in th khng c hiu lc cho phm D.
Bi tp 5-12: Hy hiu chnh bi 5-13 sau cho chng trnh khi nhn cc phm s thp phn t 0
n 9 th hin th trn led th 0, khi nhn cc phm t A n F th hin th gi tr thp phn 2 led, v
d ta nhn phm F th khng hin th F m hin th 15. Cc bc thc hin bao gm: vit lu , vit
chng trnh v m phng.
IX. CC NG DNG IU KHIN LCD

1. GII THIU LCD
Giao tip vi led 7 on c hn ch v ch hin th c cc s t 0 n 9 hoc s hex t 0 n F
khng th no hin th c cc thng tin k t khc, nhng chng s c hin th y trn LCD.
LCD c rt nhiu dng phn bit theo kch thc t vi k t n hng chc k t, t 1 hng n
vi chc hng. LCD 162 c ngha l c 2 hng, mi hng c 16 k t. LCD 204 c ngha l c 4
hng, mi hng c 20 k t.
LCD 162 c hnh dng nh hnh 5-64:
Hnh 5-64. Hnh nh ca LCD.

2. S CHN CA LCD
LCD c nhiu loi v s chn ca chng cng khc nhau nhng c 2 loi ph bin l loi 14
chn v loi 16 chn, s khc nhau l cc chn ngun cung cp, cn cc chn iu khin th khng
thay i, khi s dng loi LCD no th phi tra datasheet ca chng bit r cc chn.
93
Nguyen nh Phu
Bng 5-2: Cc chn ca LCD:

Th t
Tn tn hiu
I/O
M t
VSS
Ngun
GND
VDD
Ngun
+5V
Vo
in p
iu khin nh sng nn
RS
INPUT
Register Select
R/W
INPUT
Read/Write
INPUT
Enable (strobe)
D0
I/O
DATA LSB
D1
I/O
DATA
D2
I/O
DATA
10
D3
I/O
DATA
11
D4
I/O
DATA
12
D5
I/O
DATA
13
D6
I/O
DATA
14
D7
I/O
DATA MSB
15
Ngun dng +5V
16
GND
Trong 16 chn ca LCD c chia ra lm 3 dng tn hiu nh sau:

Cc chn cp ngun: Chn s 1 l chn ni mass (0V), chn th 2 l Vdd ni vi ngun +5V.
Chn th 3 dng chnh contrast thng ni vi bin tr.
Cc chn iu khin: Chn s 4 l chn RS dng iu khin la chn thanh ghi. Chn R/W
dng iu khin qu trnh c v ghi. Chn E l chn cho php dng xung cht.
Cc chn d liu D7D0: Chn s 7 n chn s 14 l 8 chn dng trao i d liu gia thit
b iu khin v LCD.
3. S MCH GIAO TIP VI IU KHIN VI LCD
Trong phn ny s trnh by phn giao tip vi iu khin PIC 16F887 vi LCD nh hnh 5-65:
94
Nguyen nh Phu
Hnh 5-65. Giao tip vi iu khin PIC16F887 vi LCD.

Ch : chnh bin tr sao cho cc k t hin th trn LCD th dng li.
4. CC LNH IU KHIN LCD:
iu khin LCD th c cc IC chuyn dng c tch hp bn di LCD c m s 447801
n cc IC 447809. Trong IC ny c b nh RAM dng lu tr d liu cn hin th v thc hin
vic iu khin LCD hin th.
Bng 5-3: Cc lnh iu khin LCD:
LNH
RS
RW
D7
D6
D5
D4
D3
D2
D1
D0
M t
clock
NOP
No operation
Clear display
Clear display & sets address

counter to zero
165
Cursor home
Sets address counter to zero,

returns shifted display to
original position. DDRAM
contens remain unchanged.
Entry mode set
I/D
Sets cursor move direction,

and specifies automatic
shift.
Display control
Turns display (D), cursor

on/off (C) or cursor blinking
(B).
Cursor/display
shift
S/C
R/L
Move cursor and shift

display. DDRAM contents
remain unchanged.
Function set
DL
Sets interface data width

(DL), number of display
lines (N,M) and voltage
generator control (G).
Set CGRAM
addr
Sets CGRAM addres
Set DDRAM
addr
Sets DDRAM addres
Buzy flag &

Addr
BF
Address counter
Reads buzy flag & address

counter
Read data
Read data
Reads data from CCGRAM

or DDRAM
Read data
Write data
Write data to CCGRAM or

DDRAM
Character Generator RAM

Display data ram address
Lnh xo mn hnh Clear Display: khi thc hin lnh ny th LCD s b xo v b m a

ch c xo v 0.
Lnh di chuyn con tr v u mn hnh Cursor Home: khi thc hin lnh ny th b m
a ch c xo v 0, phn hin th tr v v tr gc b dch trc . Ni dung b nh RAM hin
th DDRAM khng b thay i.
Lnh thit lp li vo Entry mode set: lnh ny dng thit lp li vo cho cc k t hin
th, bit ID = 1 th con tr t ng tng ln 1 mi khi c 1 byte d liu ghi vo b hin th, khi ID = 0
th con tr s khng tng: d liu mi s ghi ln d liu c. Bit S = 1 th cho php dch chuyn d
liu mi khi nhn 1 byte hin th.
95
Nguyen nh Phu
Lnh iu khin con tr hin th Display Control: lnh ny dng iu khin con tr (cho
hin th th bit D = 1, tt hin th th bit D = 0), tt m con tr (m con tr th bit C = 1, tt con tr th
bit C = 0), v nhp nhy con tr (cho nhp nhy th bit B = 1, tt th bit B = 0).
Lnh di chuyn con tr Cursor /Display Shift: lnh ny dng iu khin di chuyn con tr
hin th dch chuyn (SC = 1 cho php dch chuyn, SC = 0 th khng cho php), hng dch chuyn
(RL = 1 th dch phi, RL = 0 th dch tri). Ni dung b nh DDRAM vn khng i.
Lnh thit lp a ch cho b nh RAM pht k t Set CGRAM Addr: lnh ny dng thit
lp a ch cho b nh RAM pht k t.
Lnh thit lp a ch cho b nh RAM hin th Set DDRAM Addr: lnh ny dng thit
lp a ch cho b nh RAM lu tr cc d liu hin th.
Hai lnh cui cng l lnh c v lnh ghi d liu LCD.
Dng sng cc tn hiu khi thc hin ghi d liu vo LCD nh hnh 5-66:
Hnh 5-66. Dng sng iu khin ca LCD.

Nhn vo dng sng ta c th thy c trnh t iu khin nh sau:
-
iu khin tn hiu RS.
iu khin tn hiu R/W xung mc thp.
iu khin tn hiu E ln mc cao cho php.
Xut d liu D7D0.
iu khin tn hiu E v mc thp.
iu khin tn hiu R/W ln mc cao tr li.

5. A CH CA TNG K T TRN LCD
LCD16x2 c 2 hng mi hng 16 k t.
Hng 1: k t tn cng bn tri c a ch l 0x80, k t k l 0x81, k t cui cng l 0x8F.
Hng 2: k t tn cng bn tri c a ch l 0xC0, k t k l 0xC1, k t cui cng l 0xCF.
Bng 5-4: a ch ca tng k t:
a ch
80 81 82 83 84 85 86 87 88 89 8A
K t hng 1
D H
S
P
K Y
T
K t hng 2
T P
H O
C H I
a ch
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA
6. CC CHNG TRNH HIN TH TRN LCD
8B
H
M
CB
8C
U
I
CC
8D
A
N
CD
8E 8F
T
H
CE CF
Bi 5-14: S dng mch giao tip vi iu khin PIC16F887 vi LCD 162 hnh 5-65, hy vit
chng trnh hin th 2 hng thng tin nh trong bng 5-4.
96
S mch: ging nh hnh 5-65.

Lu :
Nguyen nh Phu
BEGIN
KHI TO LCD
HIN TH HNG TH NHT
HIN TH HNG TH HAI
END
Hnh 5-67: Lu hin th thng tin trn 2 hng.
Chng trnh chnh:

#INCLUDE<TV_LCD.C>
UNSIGNED INT I;
const unsigned char HANG1[16]={" DH SP KY THUAT "};
const unsigned char HANG2[16]={" TP HO CHI MINH "};
VOID MAIN()
{
SET_TRIS_E(0x00);
LCD_SETUP();
SET_TRIS_D(0x00);
LCD_COMMAND(ADDR_LINE1); DELAY_US(10);
FOR (I=0;I<16;I++)
{ LCD_DATA(HANG1[I]);}
FOR (I=0;I<16;I++)
while(TRUE) {}
}

Khai bo 2 th vin: TV_16F887.C vit, TV_LCD.C vit bn di.
Khi to cc port, khi to LCD.
Khi to a ch hng 1 v tin hnh vng lp for cho hin th ln lt 16 k t ca hng 1.
Khi to a ch hng 2 v tin hnh vng lp for cho hin th ln lt 16 k t ca hng 2.
Thc hin vng lp while.
Chng trnh th vin TV_LCD.C:

#IFNDEF LCD_RS
#DEFINE LCD_RS
PIN_E0
#ENDIF
#IFNDEF LCD_RW
#DEFINE LCD_RW
#ENDIF
PIN_E1
#IFNDEF LCD_E
#DEFINE LCD_E
#ENDIF
PIN_E2
97
Nguyen nh Phu
#IFNDEF OUTPUT_LCD
#define OUTPUT_LCD
OUTPUT_D
#ENDIF
#DEFINE
#DEFINE
#DEFINE
#DEFINE
#DEFINE
#DEFINE
#DEFINE
#DEFINE
FUNCTION_SET
DISPLAY_CONTROL
CLEAR_DISPLAY
ENTRY_MODE
SHIFT_LEFT
SHIFT_RIGHT
ADDR_LINE1
ADDR_LINE2
0X38
0X0F
0X01
0X06
0X18
0X1C
0X80
0XC0
void LCD_COMMAND(UNSIGNED CHAR MDK)

{
OUTPUT_LOW(LCD_RS);
OUTPUT_LCD(MDK);
OUTPUT_HIGH(LCD_E);
DELAY_US(20);
OUTPUT_LOW(LCD_E);
DELAY_US(20);
}
void LCD_DATA(UNSIGNED CHAR MHT)
{
OUTPUT_HIGH(LCD_RS);
OUTPUT_LCD(MHT);
OUTPUT_HIGH(LCD_E);
DELAY_US(20);
OUTPUT_LOW(LCD_E);
DELAY_US(20);
}
VOID LCD_SETUP()
{
OUTPUT_LOW(LCD_E);
OUTPUT_LOW(LCD_RS);
OUTPUT_LOW(LCD_RW);
LCD_COMMAND(FUNCTION_SET);
DELAY_MS(1);
LCD_COMMAND(DISPLAY_CONTROL);
LCD_COMMAND(CLEAR_DISPLAY);
DELAY_MS(2);
LCD_COMMAND(ENTRY_MODE);
}
Gii thch chng trnh th vin LCD:

Ba lnh u tin c chc nng kim tra xem bin LCD_RS cha nh ngha (IFNDEF c vit
tt ca cc t if not define: nu cha nh ngha) th tin hnh nh ngha. Nu nh ngha ri th
khng nh ngha na.
Vi cch thc ny c chc nng: vi cc bi LCD ny th ta dng portD v cc bit ca portE
nhng sang cc ng dng khc, ta dng port khc vi portD v E, v d khng dng portD m dng
portC th ta ch cn nh ngha portC trong chng trnh chnh, khng cn thay i cc nh ngha
trong chng trnh con LCD vit.
Tng t cho cc nh ngha khc.
Chng trnh con LCD_COMMAND thc hin chc nng gi lnh ra LCD.
Chng trnh con LCD_DATA thc hin chc nng gi d liu ra LCD hin th.
Chng trnh con LCD_SETUP thc hin chc nng khi to LCD.
Bi 5-15: S dng mch giao tip vi iu khin PIC16F887 vi LCD 162 hnh 5-65, hy vit
chng trnh hin th 2 hng thng tin nh trong bng 5-7. Trong 2 cui ca hng 1 s hin th
thi gian m giy cha cn chnh xc.
Bng 5-7: Thng tin hin th 2 hng k t:
a ch
80 81 82 83 84 85 86
K t hng 1 D O N G
H O
98
87
:
88
89
8A
8B
8C
8D
8E
S
8F
S
Nguyen nh Phu
K t hng 2 *
T P
H O
C H I
M I
N
H *
a ch
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF
S mch: ging nh hnh 5-65.
Lu :
BEGIN
KHI TO LCD
HIN TH HNG 1, HNG 2
M GIY, GII M HIN TH TRN LCD, DELAY
Hnh 5-68: Lu hin th thng tin v m giy.
Chng trnh:
#INCLUDE<TV_LCD.C>
UNSIGNED CHAR I, GIAY;
const unsigned char HANG1[16]={"DONG HO:
"};
const unsigned char HANG2[16]={"*TP HO CHI MINH*"};
VOID LCD_HIENTHI()
{ LCD_COMMAND(0x8E); DELAY_US(10);
LCD_DATA((GIAY/10)+0X30);
LCD_DATA((GIAY%10)+0X30);
}
VOID MAIN()
{ SET_TRIS_E(0x00);
SET_TRIS_D(0x00);
LCD_SETUP();
LCD_COMMAND(ADDR_LINE1);
DELAY_US(10);
FOR (I=0;I<16;I++)
LCD_COMMAND(ADDR_LINE2);
DELAY_US(10);
FOR (I=0;I<16;I++)
while(TRUE)
{
FOR(GIAY=0;GIAY<60;GIAY++)
{
LCD_HIENTHI();
DELAY_MS(1000);
}
}
}
Cc thng tin hin th trn LCD l m ASCII, gi tr ca giy c tch ra thnh s BCD v
cng thm vi 0x30 s thnh m ASCII, khi mi hin th trn LCD.
99
Nguyen nh Phu
Bi tp 5-13: Hy vit chng trnh m pht giy hin th trn LCD. Pht hin th cng hng
vi giay, cch 1 .
Bi tp 5-14: Hy vit chng trnh m gi pht giy hin th trn LCD.
X.
1.
CU HI N TP
Cu s 5-1:
Hy nu cc chc nng portA, B, C, D v E ca vi iu khin PIC16F887.
Cu s 5-2:
Hy so snh port0 ca vi iu khin AT89S52 v portA ca PIC16F887.
Cu s 5-3:
Hy so snh port1 ca vi iu khin AT89S52 v portB ca PIC16F887.
2.
CU HI M RNG
Cu s 5-4:
3.
Hy tm hiu cc port ca vi iu khin PIC18F4550 v so snh vi PIC16F887.
CU HI TRC NGHIM
Cu 5-1:
Vi iu khin PIC 16F887 c my port:
(a) 3
(c) 5
Cu 5-2:
(b) 4
(d) 6
Port no ca PIC 16F887 c in tr ko ln bn trong:
(a) PortA
(c) PortC
Cu 5-3:
(b) PortB
(d) PortD
Port no ca PIC 16F887 c ng vo ngt ngoi INT:
(a) PortA
(c) PortC
Cu 5-4:
(b) PortB
(d) PortD
Thanh ghi TRISX ca PIC 16F887 c chc nng:
(a) nh hng cho ADC

(c) nh hng cho cc port
Cu 5-5:
(b) Lu d liu cho cc port

(d) Lu a ch ca cc port
Khai bo bin INT x th bin x l:
(a) 1 bit
(c) 16 bit
Cu 5-6:
(b) 8 bit
(d) 32 bit
Khai bo bin INT16 y th bin y l:
(a) 1 bit
(c) 16 bit
Cu 5-7:
(b) 8 bit
(d) 32 bit
Khai bo bin unsigned int y th bin y l s nguyn dng:
(a) C gi tr t 0 n 255
(c) C gi tr t -128 n 127
Cu 5-8:
(b) C gi tr t 0 n 25
(d) C gi tr t -128 n 255
Khai bo bin signed int y th bin y l s nguyn dng:
(a) C gi tr t 0 n 255
(c) C gi tr t -128 n 127
Cu 5-9:
K hiu x = y/z l lnh c chc nng:
(a) X bng y chia z ly s d

100
(b) C gi tr t 0 n 256
(d) C gi tr t -128 n 255
(b) X bng y chia z ly kt qu
Nguyen nh Phu
(c) X bng z chia y ly s d
(d) X bng z chia y ly kt qu
Cu 5-10: K hiu x = y%z l lnh c chc nng:

(a) X bng y chia z ly s d
(c) X bng z chia y ly s d
(b) X bng y chia z ly kt qu

(d) X bng z chia y ly kt qu
Cu 5-11: Khai bo no l khi bo k t:

(a) INT
(c) FLoat
(b) Char
(d) Long
Cu 5-12: Lnh no nh cu hnh cho portB:

(a) Output_b(value)
(c) Set_tris_b(value)
(b) Output_X(value)
(d) Input_X(value)
Cu 5-13: Lnh no xut gi tr 8 bit ra portB:

(a) Output_b(value)
(c) Set_tris_b(value)
(b) Output_high(value)
(d) Input_b(value)
Cu 5-14: Lnh no lm 1 tn hiu ca port xung mc thp:

(a) Output_low(pin)
(c) Output_toggle(pin)
(b) Output_high(pin)
(d) Output_pull(pin)
Cu 5-15: Vi iu khin PIC th cc port:

(a) Ch truy xut bit
(c) Truy xut byte
(b) Truy xut bit v byte

(d) Truy xut 16 bit
Cu 5-16: Trong mch qut 8 led th transistor c chc nng:

(a) Khuch i dng
(c) Khuch i dng, p
(b) Khuch i p
(d) iu khin led
Cu 5-17: Trong mch qut 8 led th mi thi im c:

(a) 2 led sng
(c) 3 led sng
(b) 1 led sng

(d) 8 led sng
Cu 5-18: Trong mch qut 8 led nu chng trnh khng qut th:
(a) 8 led vn sng
(c) 8 led tt
(b) 8 led sng m

(d) 1 led sng
Cu 5-19: Nu m rng mch qut 8 led thnh 16 led th dng tng cng:
(a) 16 ng I/O
(c) 8 ng I/O
(b) 32 ng I/O
(d) 24 ng I/O
Cu 5-20: Trong mch qut 8 led th thi gian led sng mi led l:
(a) 1/8 chu k
(c) 1/4 chu k
(b) 7/8 chu k

(d) 8/7 chu k
Cu 5-21: Trong mch qut 8 led th thi gian led tt mi led l:

(a) 1/8 chu k
(c) 1/4 chu k
(b) 7/8 chu k

(d) 8/7 chu k
Cu 5-22: M 7 on s 9 ca led anode chung l:

(a) 0xF9
(c) 0x80
(b) 0x90
(d) 0xF0
101
Nguyen nh Phu
Cu 5-23: M 7 on s hex F ca led anode chung l:

(a) 0x8E
(c) 0xF8
102
(b) 0xE8
(d) 0xFE
Chng 6
GII THIU
B CHIA TRC V CHIA SAU CA TIMER2

NG RA CA TMR2
CC LNH CA TIMER COUNTER TRONG NGN NG CCS-C
TIMER1 CH NH THI
TIMER1 CH M XUNG NGOI
HOT NG CA TIMER1 CH COUNTER NG B
HOT NG CA TIMER1 CH COUNTER BT NG B
C V GHI TIMER1 TRONG CH M KHNG NG B
B DAO NG CA TIMER1
RESET TIMER1 S DNG NG RA CCP TRIGGER
RESET CP THANH GHI TMR1H, TMR1L CA TIMER1
NGT CA TIMER0
TIMER0 M XUNG NGOI
B CHIA TRC
LNH SETUP_TIMER_0(MODE)
LNH SET_TIMERX(VALUE)
LNH GET_TIMERX()
LNH SETUP_WDT(MODE)
LNH RESTART_WDT()
CC NG DNG NH THI DNG TIMER

CC NG DN M XUNG NGOI DNG COUNTER
CU HI N TP
CU HI M RNG
CU HI TRC NGHIM
BI TP
Nguyen nh Phu
I. GII THIU
chng ny kho st cc timer/counter ca cc vi iu khin, cc timer/counter c chc nng
m xung ni c chu k bit nh thi iu khin thit b theo thi gian, c th m xung ngoi
m s kin nh m s vng dy qun, m sn phm, m tin,
Timer c nhiu tin ch trong iu khin nn hu ht cc vi iu khin u tch hp, chng
ny chng ta s kho st timer/counter v cc ng dng.
Vi iu khin PIC h 16F887 c 3 timer T0, T1 v T2. T0 l timer/counter 8 bit, T1 l
timer/counter 16 bit, c 2 u c b chia trc. T2 l timer 8 bit c b chia trc v chia sau phc v
cho cc ng dng c bit.
Sau khi kt thc chng ny bn c th s dng c timer/counter ca cc vi iu khin.
II. KHO ST TIMER0 CA PIC 16F887

B timer0/counter0 c nhng c im sau:
o
L timer/counter 8 bit.
C th c v ghi gi tr m ca timer/counter.
C b chia trc 8 bit cho php lp trnh la chn h s chia bng phn mm.
Cho php la chn ngun xung clock bn trong hoc bn ngoi.
Pht sinh ngt khi b trn t FFH v 00H.
Cho php la chn tc ng xung CK cnh ln hoc cnh xung.
S khi ca timer0 v b chia trc vi WDT nh hnh 6-1:
Hnh 6-1: S khi ca timer0 ca PIC16F887.

s dng timer0 th phi kho st chc nng ca thanh ghi iu khin timer l OPTION_REG.
Cu hnh thanh ghi v chc nng cc bit nh sau:
104
Chng 6.Timer counter.
Nguyen nh Phu
OPTION_REG
R/W(1)
R/W(1)
RBPU
INTEDG
Bit 7
R/W(1)
R/W(1)
T0CS
T0SE
R/W(1)
PSA
R/W(1)
PS2
R/W(1)
PS1
R/W(1)
PS0
Bit 0
Hnh 6-2: Thanh ghi OPTION_REG.

Bit 7
RBPU : bit iu khin in tr treo ca portb.
Bit 6
INTEDG
Bit 5
T0CS: bit la chn ngun xung cho TMR0 - TMR0 Clock Source Select bit.
1= s m xung ngoi a n chn T0CKI.
0= s m xung clock ni bn trong.
Bit 4
T0SE: bit la chn cnh tch cc T0SE - TMR0 Source Edge Select bit.
0= tch cc cnh ln chn T0CKI.
1= tch cc cnh xung chn T0CKI.
Bit 3
PSA: bit gn b chia trc - prescaler assigment.

1= gn b chia cho WDT.
0= gn b chia Timer0.
Bit 2-0
PS2:PS0: cc bit la chn t l b chia trc - prescaler rate select bits:
Bng 6-1. La chn h s chia ca Timer0.
Bit la chn
T l TMR0
T l WDT
000
1:2
1:1
001
1:4
1:2
010
1:8
1:4
011
1:16
1:8
100
1:32
1:16
101
1:64
1:32
110
1:128
1:64
111
1:256
1:128
Nu bit T0CS bng 1 th chn ch m xung ngoi Counter. Trong ch m xung ngoi
th xung m a n chn RA4/T0CKI. Bit T0SE = 0 th chn cnh ln, ngc li th chn cnh
xung.
B chia trc khng th c/ghi c mi quan h vi Timer0 v Watchdog Timer.
1.
NGT CA TIMER0
Khi gi tr m trong thanh ghi TMR0 trn t FFh v 00h th pht sinh ngt, c bo ngt
TMR0IF ln 1. Ngt c th ngn bng bit cho php ngt TMR0IE.
Trong chng trnh con phc v ngt Timer0 phi xa c bo ngt TMR0IF. Ngt ca TMR0
khng th kch CPU thot khi ch ng v b nh thi s ngng khi CPU ch ng.
Trong datasheet th bit cho php ngt c tn l T0IE v c bo ngt l T0IF. Hai bit ny nm
trong thanh ghi INTCON v tr th 5 v th 2.
Thanh ghi INTCON nm trong vng nh RAM c a ch l 0xB0.
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Nguyen nh Phu
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
GIE
PEIE
T0IE
INTE
RBIE
R/W(0)
T0IF
R/W(0)
INTF
R/W(X)
RBIF

2.
TIMER0 M XUNG NGOI
Mun m xung ngoi th xung c a n ng vo T0CKI, vic ng b tn hiu xung ng

vo T0CKI vi xung clock bn trong c thc hin bng cch ly mu ng ra b chia nhng chu k
Q2 v Q4 ca xung clock bn trong. iu ny rt cn thit cho T0CKI trng thi mc cao t nht 2
TOSC v trng thi mc thp t nht 2 T OSC.
3.
B CHIA TRC
B chia trc c th gn cho Timer0 hoc gn cho Watchdog Timer. Cc bit PSA v PS2:PS0
chn i tng gn v t l chia.
Khi c gn cho Timer0 th tt c cc lnh ghi cho thanh ghi TMR0 (v d CLRF 1, MOVWF
1, BSF 1, ) s xo b chia trc.
Khi c gn cho WDT th lnh CLRWDT s xo b chia trc cng vi Watchdog Timer.
Hnh 6-4: B chia trc c gn cho timer.
Hnh 6-5: B chia trc c gn cho WDT.
III. KHO ST TIMER1 CA PIC 16F887

106
Nguyen nh Phu
Timer1 l b nh thi/m 16 bit gm 2 thanh ghi 8 bit (TMR1H v TMR1L) c th c v

ghi. Hai thanh ghi ny tng t 0000h n FFFFh v quay tr li 0000h.
Khi b trn th Timer1 s pht sinh ngt, c bo ngt TMR1IF (PIR1<0>) ln mc 1. Timer1 c
bit cho php/cm ngt l TMR1IE (PIE1<0>).
Thanh ghi TMR1H
Bit 15
Thanh ghi TMR1L
Bit 8
Bit 7
Bit 0
Hnh 6-6: Thanh ghi lu kt qu ca T1.

Cu trc ca Timer1:
Hnh 6-7: Cu trc timer T1.

Kho st thanh ghi iu khin Timer1:
R/W(0)
T1CON
T1GINV
Bit 7
R/W(0)
R/W(0)
R/W(0)
R/W(0)
T1CKPS0 T1OSCEN
T1SYNC
TMR1CS TMR1ON
Bit 0
TMR1GE T1CKPS1
R/W(0)
R/W(0)
R/W(0)

Bit 7
T1GINV: bit o cng ca Timer1 - Timer1 Gate Invert bit

1= cng Timer1 tch cc mc 1 (Timer1 m khi cng mc 1).
0= cng Timer1 tch cc mc 0 (Timer1 m khi cng mc 0).
Bit 6
TMR1GE: bit cho php cng ca Timer1 - Timer1 Gate Enable bit
Nu TMR1ON = 0: bit ny s khng c tc dng.
Nu TMR1ON = 1:
1= Timer1 m nu cng ca Timer1 khng tch cc.
0= Timer1 m.
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Nguyen nh Phu
Bit 5-4
bits
T1CKPS1:T1CKPS0: cc bit la chn b chia - Timer1 input Clock Prescale Select

11=1:8 gi tr chia.
10=1:4 gi tr chia.
01=1:2 gi tr chia.
00=1:1 gi tr chia.
Bit 3
bit
T1OSCEN: bit K cho php b dao ng Timer1 - Timer1 Oscillator Enable Control
1= b dao ng c php.
0= Tt b dao ng.
Bit 2
T1SYNC: bit K ng b ng vo xung clock bn ngoi ca timer1

Khi TMR1CS = 1:
1= khng th ng b ng vo clock t bn ngoi.
0= ng b ng vo clock t bn ngoi.
Khi TMR1CS = 0:
Bit ny b b qua. Timer1 dng xung clock bn trong khi TMR1CS = 0.
Bit 1
TMR1CS: bit la chn ngun xung clock ca timer1

1= Chn ngun xung clock t bn ngoi chn RC0/T1OSO/T1CKI (cnh ln).
0= Chn xung ni bn trong (FOSC/4).
Bit 0
TMR1ON: bit iu khin Timer14

1= Cho php Timer1 m.
0= Timer1 ngng m.
1.
TIMER1 CH NH THI
Nu bit TMR1CS bng 0 th T1 hot ng nh thi m xung ni c tn s bng FOSC/4. Bit

iu khin ng b T1SYNC khng b nh hng do xung clock bn trong lun ng b.
Hnh 6-9: Timer1 hot ng nh thi.

2.
TIMER1 CH M XUNG NGOI
Nu bit TMR1CS bng 1 th T1 hot ng m xung ngoi. Xung ngoi c 2 ngun xung ph
thuc vo bit T1OSCEN:
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Nguyen nh Phu
Nu bit T1OSCEN bng 1 th T1 m xung ngoi t mch dao ng ca T1 - xem hnh 6-10.
Nu bit T1OSCEN bng 0 th T1 m xung ngoi a n ng vo T1CKI - xem hnh 6-11.
Hnh 6-10: T1 hot ng m xung ngoi t mch dao ng T1.
Hnh 6-11: T1 hot ng m xung ngoi a n ng vo T1CKI.

Timer1 tng gi tr khi c xung cnh ln. Counter ch tng gi tr m sau khi nhn 1 xung cnh
xung c minh ho hnh 6-12.
Hnh 6-12: Gin thi gian xung m ca Counter1.

Hnh trn th ng vo ang mc 1, counter s m khi c xung cnh ln.
Hnh di th ng vo ang mc thp, xung cnh ln th nht th mch vn cha m, xung
xung mc thp v khi c cnh ln th 2 th counter bt u m.
3.
HOT NG CA TIMER1 CH COUNTER NG B

Khi bit TMR1CS bng 1 th T1 hot ng ch Counter:
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Nguyen nh Phu
Nu bit T1OSCEN bng 1 th m xung t mch dao ng ca T1.

Nu bit T1OSCEN bng 1 th m xung cnh ln a n ng vo RC0/T1OSO/T1CKI.
Nu bit T1SYNC bng 0 th ng vo xung ngoi c ng b vi xung bn trong. ch
ng b, nu CPU ch ng th Timer1 s khng m v mch ng b ngng hot ng.
4.
HOT NG CA TIMER1 CH COUNTER BT NG B
Nu bit T1SYNC bng 1 th xung ng vo t bn ngoi khng c ng b. B m tip tc

tng bt ng b vi xung bn trong. B m vn m khi CPU trong ch ng v khi trn s pht
sinh ngt v nh thc CPU. Ngt T1 c th ngn c.
5.
C V GHI TIMER1 TRONG CH M KHNG NG B
Timer T1 cho php c gi tr cc thanh ghi TMR1H hoc TMR1L khi timer ang m xung bt
ng b bn ngoi.
Khi ghi th nn ngng timer li ri mi ghi gi tr mong mun vo cc thanh ghi. Nu ghi m
timer ang m vn c nhng c th to ra mt gi tr m khng d on c hay khng chnh
xc.
6.
B DAO NG CA TIMER1
Mch dao ng c tch hp bn trong v t thch anh ni gia 2 chn T1OSI v T1OSO
to dao ng - xem hnh 6-13. B dao ng c php hot ng khi bit T1OSCEN bng 1.
Hnh 6-13: Kt ni thch anh to dao ng.

B dao ng l dao ng cng sut thp, tc 200 kHz. B dao ng vn tip tc chy khi
CPU ch ng. B dao ng ch dng vi t thch anh 32 kHz. Bng sau trnh by cch la chn
t cho b dao ng Timer1.
Bng 6-2. La chn tn s v t tng ng ca Timer1.
7.
Loi dao ng
Tn s
T C1
T C2
LP
32kHz
33pF
33pF
100kHz
15pF
15pF
200kHz
15pF
15pF
RESET TIMER1 S DNG NG RA CCP TRIGGER
Nu khi CCP1 v CCP2 c nh cu hnh ch so snh to ra xung kch

(CCP1M3:CCP1M0 = 1011), tn hiu ny s reset Timer1.
Ch : xung kch t khi CCP1 v CCP2 s khng lm c ngt TMR1IF (PIR1<0>) bng 1.
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Nguyen nh Phu
Timer1 phi nh cu hnh ch nh thi hoc b m ng b to tin ch cho cu trc

ny. Nu Timer1 ang hot ng ch m bt ng b th hot ng Reset khng th thc hin
c.
8.
RESET CP THANH GHI TMR1H, TMR1L CA TIMER1
Hot ng reset lc cp ngun POR (Power On Reset) hoc bt k reset no khc khng nh
hng n hai thanh ghi TMR1H v TMR1L, ngoi tr khi xy ra xung kch ca CCP1 v CCP2 th
xa hai thanh ghi v 00H.
Thanh ghi T1CON c reset v 00h
Reset lc cp ngun POR hoc khi Brown-out Reset s xa thanh ghi T1CON v timer T1
trng thi ngng (OFF) v h s chia trc l 1:1. Cc reset khc th thanh ghi khng b nh hng.
IV. KHO ST TIMER2 CA PIC16F887

Timer2 l timer 8 bit c b chia trc (prescaler) v c b chia sau (postscaler).
Timer2 c s dng iu ch xung khi khi CCP hot ng ch PWM (pulse width
modulation). Thanh ghi TMR2 c th c/ghi v xo khi b reset.
Xung ni (FOSC/4) qua b chia trc c h s chia: 1:1, 1:4 hoc 1:16 c la chn
bng cc bit iu khin T2CKPS1:T2CKPS0 (T2CON<1:0>).
PR2 l thanh ghi chu k 8 bit dng so snh. Timer2 tng gi tr t 00h cho n khi bng gi
tr lu trong thanh ghi PR2 th reset v 00h ri lp li.
PR2 l thanh ghi c th c/ghi, khi h thng b reset th thanh ghi PR c khi to gi tr FFH.
Ng ra ca TMR2 i qua b chia sau (postscaler) 4 bit trc khi pht sinh yu cu ngt lm c
TMR2IF (PIR1<1>) ln 1. Khi bit TMR2ON bng 0 th tt Timer2 gim cng sut tiu th.
Hnh 6-14: S khi ca Timer2.

Thanh ghi iu khin timer2:
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Nguyen nh Phu
U(0)
T2CON
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Bit 0
U(0): cha dng

Bit 7
Bit 7
Cha s dng nu c s c gi tr 0.
Bit 6-3
TOUTPS3:TOUTPS0: cc bit la chn ng ra b chia sau (Postscaler) ca Timer2

0000=1:1
0001=1:2
0010=1:3
0011=1:4
0100=1:5
0101=1:6
0110=1:7
0111=1:8
1000=1:9
1001=1:10
1010=1:11
1011=1:12
1100=1:13
1101=1:14
1110=1:15
1111=1:16
TMR2ON: Bit iu khin cho php/cm Timer2
Bit 2
1= cho php timer2 m.

0= Timer2 ngng m.
Bit 1-0
T2CKPS1:T2CKPS0: bit la chn h s chia trc cho ngun xung clock ca timer2
00= h s chia l 1.
01= h s chia l 4.
1x= h s chia l 16.
1.
B CHIA TRC V CHIA SAU CA TIMER2

B m chia trc v b chia sau s b xa khi xy ra mt trong cc s kin sau:
Thc hin ghi d liu vo thanh ghi TMR2.
Thc hin ghi d liu vo thanh ghi T2CON.
Bt k Reset no tc ng.
TMR2 khng b xa khi ghi d liu vo thanh ghi T2CON.
2.
NG RA CA TMR2
Ng ra ca TMR2 c ni ti khi SSP khi ny c th ty chn to ra xung nhp.
CC LNH CA TIMER COUNTER TRONG NGN NG PIC-C
V.
Cc lnh ca ngn ng lp trnh C lin quan n timer/counter bao gm:

o Lnh SETUP_TIMER_X()
o Lnh SET_TIMER_X()
o Lnh SETUP_COUNTERS()
o Lnh SETUP_WDT()
o Lnh RESTART_WDT()
o Lnh GET_TIMER_X()
1.
C php:
setup_timer_0(mode)
Thng s:
mode c th l 1 hoc 2 hng s nh ngha trong file device.h. Cc thng s gm

RTCC_INTERNAL, RTCC_EXT_L_TO_H hoc RTCC_EXT_H_TO_L
RTCC_DIV_2, RTCC_DIV_4, RTCC_DIV_8, RTCC_DIV_16, RTCC_DIV_32,
RTCC_DIV_64, RTCC_DIV_128, RTCC_DIV_256.
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Nguyen nh Phu
Cc hng s t nhiu nhm khc nhau th c th or vi nhau.

Chc nng:
nh cu hnh cho TIMER0.

2.
C php:
setup_timer_1(mode)
Thng s:
mode c th l 1 hoc 2 hng s nh ngha trong file device.h. Cc thng s gm

T1_DISABLED, T1_INTERNAL, T1_EXTERNAL, T1_EXTERNAL_SYNC
TC_CLK_OUT, T1_DIV_BY_1, T1_DIV_BY_2, T1_DIV_BY_4, T1_DIV_BY_8.
Cc hng s t nhiu nhm khc nhau th c th or vi nhau.
Chc nng:
Khi to cho TIMER1.

Vi tn s thch anh l 20MHz v khi to T1_DIV_BY_8 th timer s tng gi tr sau
mi khong thi gian 1.6s. Timer s trn sau 104.8576 ms.
C hiu lc: Cho tt c cc vi iu khin PIC c timer 1.

3.
C php:
setup_timer_2(mode, period, postscale)
Thng s:
mode c th l 1 trong cc thng s: T2_DISABLED, T2_DIV_BY_1, T2_DIV_BY_4,

T2_DIV_BY_16
Period l s nguyn c gi tr t 0 n 255 dng xc nh khi no timer2 b reset hay
gi ny tr dng np cho thanh ghi PR2.
postscale l s nguyn c gi tr t 1 n 16 dng xc nh timer trn bao nhiu ln
trc khi pht sinh tn hiu ngt chn t l chia ca b chia sau.
Chc nng:
khi to cho TIMER2.

Mode ch nh kiu b chia ca timer t tn s ca mch dao ng.
Gi tr ca timer c th c hoc ghi dng lnh GET_TIMER2() v SET_TIMER2().
TIMER2 l timer 8 bit.
C hiu lc: cho tt c cc vi iu khin PIC c timer 2.

4.
LNH SET_TIMERx(value)
C php:
set_timerX(value)
; x l 0, 1, 2
Thng s:
value l hng s nguyn 8 hoc 16 bit dng thit lp gi tr mi cho timer.
Chc nng:
thit lp gi tr bt u cho TIMER.
C hiu lc: cho tt c cc vi iu khin PIC c timer.

5.
LNH GET_TIMERx()
C php:
value = get_timerX() ; x l 0, 1, 2
Thng s:
khng c.
Chc nng:
c gi tr ca TIMER/COUNTER.

6.
LNH SETUP_WDT()
C php:
Thng s:
setup_wdt (mode)
For PCB/PCM parts: WDT_18MS, WDT_36MS, WDT_72MS,
113
Nguyen nh Phu
Chc nng:
C hiu lc:
Yu cu:
WDT_144MS,WDT_288MS, WDT_576MS, WDT_1152MS, WDT_2304MS

For PIC18 parts: WDT_ON, WDT_OFF
Thit lp cho b nh thi watchdog.
B nh thi watchdog c s dng reset phn cng nu phn mm lp trnh b sa
ly nhng vng lp v tn hoc mt s kin no ch chng xy ra nhng chng
li khng bao gi xy ra, chm dt vic ch i ny th ta phi s dng b nh thi
watchdog.
Trc khi tin hnh vo vng lp th ta phi cho php b nh thi watchdog m vi
khong thi gian lp trnh trc v nu s kin khng xy ra th b nh thi
watchdog s ht thi gian lp trnh s reset phn cng thot khi vng lp.
PCB/PCM
PCH
Enable/Dis ble
#fuses
setup_wdt()
Ti eo t time
setup_wd ()
#f ses
Restart
restart_wdt()
restart_wdt()
Cho tt c cc thit b
#fuses, hng s c nh ngha trong file devices.h
LNH RESTART_WDT()
7.
C php:
Thng s:
Chc nng:
C hiu lc:
Yu cu:
restart_wdt()
Khng c
Khi to li b nh thi watchdog. Nu b nh thi watchdog c cho php th
lnh ny s khi to li gi tr nh thi ngn chn khng cho b nh thi reset
CPU v s kin ch i xy ra.
PCB/PCM
PCH
Enable/Di able #fuses
setup_wdt()
Tim out time setup_ dt()
fuses
restart
restart_wdt() restart_wdt()
Cho tt c cc thit b
#fuses, hng s c nh ngha trong file devices .h
VI. CC NG DNG NH THI DNG TIMER

Bi 6-1: Dng vi iu khin PIC 16F887 iu khin 8 led n sng tt dng timer T1 vi chu k
delay l 210ms.
S mch:
Hnh 6-15: PIC iu khin 8 led sng tt.

114
Nguyen nh Phu
S dng portD iu khin 8 led n, thch anh s dng l 20Mhz.
Lu :
BEGIN
KHI TO TIMER1 M XUNG NI
H S CHIA BNG 8, PORTD XUT
TIMER1=0
TIMER1 TRN
S
O TRNG THI 8 LED, XA C TRN
Hnh 6-16: Lu iu khin 8 led sng tt nh thi 210ms.
Chng trnh:
#BIT
TMR1IF = 0x0C.0
UNSIGNED INT8 X;
VOID MAIN()
{
SET_TRIS_D(0x00);
X=0X00; OUTPUT_D(X);
SETUP_TIMER_1(T1_INTERNAL | T1_DIV_BY_8);
SET_TIMER1(0);
WHILE(TRUE)
{
IF (TMR1IF==1)
{
X=~X;
OUTPUT_D(X); TMR1IF=0;
}
}
}
Gii thch chng trnh v tnh ton thi gian delay:

Khi to timer1 m xung ni c tn s 20MHz qua b chia 4 cn 5MHz. S dng b chia trc
vi t l chia l 8 nn xung vo b m vi tn s cn li l 5MHz/8 = 0,625MHz hay bng 625kHz,
chu k l 1,6s.
Khi to bin X bng 00 v gi bin m ra portD s lm cc led tt.
Lnh if kim tra c trn TMR1IF ca timer1: nu cha trn th ch cho n khi trn th TMR1IF
bng 1, lnh o bin X, gi tr ny gi ra port s lm cc led sng, xa c trn bo hiu trn cho ln
sau.
Nu trn ln tip theo th lnh X = ~ X s nghch o bin X bng 0x00, gi tr ny gi ra port s
lm cc led tt,
Timer T1 m 65536, thi gian m bng s xung m nhn vi chu k mi xung: xungTxung
= 655361,6s = 104857,6 s 105ms nn thi gian sng v tt ca 8 led u bng 105ms hay chu k
bng 210ms.
Trong chng trnh ny s dng bit TMR1IF kim tra nhng th vin <16F887.H > khng
nh ngha bit ny, nn c thm hng lnh #bit tmr1if = 0x0C.0 nh ngha bit c trn.
C trn nm bit th 0, trong thanh ghi PIR1 c a ch 0x0C.
Thi gian nh thi ln nht c th c ca Timer1 l 105ms vi tn s thch anh l 20MHz, bn
ch c th nh thi nh hn nu ch dng timer, mun nh thi ln hn th phi dng thm bin.
115
Nguyen nh Phu
delay l 200ms.
S mch: ging bi 6-1.

Lu :
BEGIN
TIMER1=3036
TIMER1 TRN
S
Hnh 6-17: Lu iu khin 8 led sng tt dng ngt nh thi 200ms.
Chng trnh:
#BIT
TMR1IF = 0x0C.0
UNSIGNED INT8 X;
VOID MAIN()
{
SET_TRIS_D(0x00); X=0X00; OUTPUT_D(X);
SET_TIMER1(3036);
WHILE(TRUE)
{
IF (TMR1IF==1)
{
X=~X;
OUTPUT_D(X); SET_TIMER1(3036);
TMR1IF=0;
}
}
}
Gii thch chng trnh:

Chng trnh ny khi to gi tr bt u m cho timer T1 l 3036, timer m thm 62500 xung
na th trn, s lng xung m l 62500 xung, mi xung l 1,6s nn thi gian sng bng thi gian
tt bng 625001,6s = 1.000.000s = 100ms, chu k bng 200ms.
Bn c th tnh nh sau: thi gian delay l 100ms hay 100,000 s, mi chu k xung l 1,6s. Khi
s xung m bng thi gian chia cho chu k xung s c 62500 xung ph hp vi gi tr 16 bit
ca Timer1.
Nu s lng xung tnh ln hn s bit ca timer th gim thi gian m.
delay l 2s, 1 giy sng, 1 giy tt.
116
S mch: ging bi 6-1.

Nguyen nh Phu
Lu :
BEGIN
BIN M TRN BDT=0
TIMER1=3036
TIMER1 TRN
BDT = BDT +1, XA C TRN
BDT = 10 (1S)
O TRNG THI 8 LED
Hnh 6-18: Lu iu khin 8 led sng tt nh thi 1s.
Chng trnh:
#BIT
TMR1IF = 0x0C.0
UNSIGNED INT8 X, BDT;
VOID MAIN()
{
SET_TRIS_D(0x00); X=0; BDT=0; OUTPUT_D(X);
SET_TIMER1(3036);
WHILE(TRUE)
{
IF (TMR1IF==1)
{
TMR1IF=0;
SET_TIMER1(3036); BDT++;
IF (BDT ==10)
{
OUTPUT_D(X); X=~X; BDT = 0;
}
}
}
}
Gii thch chng trnh:

Chng trnh chnh kim tra c trn, nu trn th khi to li v tng bin m trn BDT ln 1,
kim tra bin m trn BDT bng 10 hay cha, nu cha bng th thot ch bo trn tip theo, nu
bng th o trng thi ca led v xa bin trn.
117
Nguyen nh Phu
Thi gian sng bng thi gian tt v bng 100ms10=1000ms = 1s.

Bi tp 6-1: Hy vit chng trnh iu khin 8 led n ni vi portD sng 2 giy, tt 1 giy,
dng Timer1 nh thi.
Bi tp 6-2: Hy vit chng trnh m giy chnh xc hin th trn 2 led 7 on kt ni trc tip
dng portB v C, dng Timer1 nh thi.
Bi 6-4: Dng vi iu khin 16F887 iu khin 8 led n sng tt dng timer T0 vi chu k
delay l 26ms, 13ms sng, 13ms tt.
S mch: ging bi 6-1.

Lu :
BEGIN
TIMER0=0
TIMER0 TRN
S
Chng trnh:
#BIT
TMR0IF = 0x0B.2
UNSIGNED INT8 X;
VOID MAIN()
{
SET_TRIS_D(0x00);
X=0; OUTPUT_D(X);
SETUP_TIMER_0(T0_INTERNAL | T0_DIV_256);
SET_TIMER0(0);
WHILE(TRUE)
{
IF (TMR0IF==1)
{
TMR0IF=0;
SET_TIMER0(0);
X=~X;
OUTPUT_D(X);
}
}
}
Gii thch chng trnh:

Khi to timer0 m xung ni c tn s 20MHz qua b chia 4 cn 5MHz. S dng b chia trc
vi t l chia l 256 nn xung vo b m vi tn s cn li l 5MHz/256 = 0,01953125MHz hay bng
19,53125kHz, chu k l 51,2s.
118
Nguyen nh Phu
Timer T0 m 256 xung, thi gian m bng s xung m nhn vi chu k mi xung:
xungTxung = 25651,2s = 13107,2s, thi gian sng v tt ca 8 led u bng 13,107 ms hay chu
k bng 26,214ms.
nh ngha bit ny, nn c thm hng lnh #bit tmr0if = 0x0B.2 nh ngha bit c trn.
C trn nm bit th 2, trong thanh ghi INTCON c a ch 0x0B.
Thi gian nh thi ln nht c th c ca Timer0 l 13,107ms vi tn s thch anh l 20MHz,
bn ch c th nh thi nh hn nu ch dng timer, mun nh thi ln hn th phi dng thm bin.
delay l 2s, 1s sng, 1s tt.
S mch: ging bi 6-1.

Lu :
BEGIN
BIN M TRN BDT=0
TIMER0=61
TIMER0 TRN
BDT = BDT +1, XA C TRN
BDT = 100 (1S)
O TRNG THI 8 LED
Hnh 6-20: Lu iu khin 8 led sng tt, nh thi 1s dng T0.
Chng trnh:
#BIT TMR0IF = 0x0B.2
UNSIGNED INT8 X, BDT;
VOID MAIN()
{
SET_TRIS_D(0x00);
X=0;
BDT=0; OUTPUT_D(X);
SETUP_TIMER_0(T0_INTERNAL | T0_DIV_256);
SET_TIMER0(61);
WHILE(TRUE)
{
IF (TMR0IF==1)
119
Nguyen nh Phu
}
}
TMR0IF=0;
SET_TIMER0(61);
BDT++;
if (BDT==100)
{
BDT=0;
X=~X; OUTPUT_D(X);
}
Gii thch chng trnh:

Timer T0 m 195 xung, thi gian m bng s xung m nhn vi chu k mi xung:
xungTxung = 19551,2s = 9984s 10ms.
Sau 100 ln ngt th tin hnh o bin X v gi ra port nn thi gian sng v tt ca 8 led u
bng 1s.
Trong chng trnh ny c sai s: thiu 16 s cho khong thi gian 10ms, thiu 1600 s cho
khong thi gian 1s.
delay l 26ms, 13ms sng, 13ms tt.
S mch: ging bi 6-1.

Lu :
BEGIN
KHI TO TIMER2: H S CHIA TRC 16, H S CHU K

255, H S CHIA SAU 16, PORTD XUT
TIMER2 TRN
S
Chng trnh:
#BIT TMR2IF = 0x0C.1
UNSIGNED INT8 X;
VOID MAIN()
{
SET_TRIS_D(0x00);
X=0;
OUTPUT_D(X);
SETUP_TIMER_2(T2_DIV_BY_16, 255,16);
WHILE(TRUE)
{
120
Nguyen nh Phu
IF (TMR2IF==1)
{
TMR2IF=0;
}
X=~X; OUTPUT_D(X);
}
}
Gii thch chng trnh:

Khi to Timer2 m xung ni c tn s 20MHz qua b chia 4 cn 5MHz. S dng b chia
trc vi t l chia l 16 nn xung vo b m vi tn s cn li l 5MHz/16 = 0,3125MHz hay bng
312,5kHz, chu k l 3,2s.
Timer T2 m 256 xung v so snh vi gi tr ca thanh ghi PR2 bng 255, thi gian m bng
s xung m nhn vi chu k mi xung: xungTxung = 2563,2s = 819,2s.
B chia sau l 16 nn sau 16 ln th bo ngt, thi gian sng v tt ca 8 led u bng 819,2s
16 ms = 13107,2 s hay chu k bng 26,214ms.
nh ngha bit ny, nn c thm hng lnh #bit tmr2if = 0x0C.1 nh ngha bit c trn.
C trn nm bit th 1, trong thanh ghi PIR1 c a ch 0x0C.
Bi tp 6-3: Hy vit chng trnh m giy hin th trn 2 led 7 on kt ni trc tip dng
portB v C, dng Timer2 nh thi.
VII. CC NG DNG M XUNG NGOI DNG COUNTER

Bi 6-7: Dng vi iu khin 16F887 m xung ngoi dng T0, kt qu m hin th trn 3 led
kt ni trc tip vi 3 port, gii hn m t 000 n 255, khi bng 255 th quay v 0.
S mch:
Gii thch nguyn l hot ng ca mch:

Mch to xung dng led thu v led pht, khi khng c vt che gia led thu v led pht th
transistor c phn cc dn bo ho, ng ra cc C mc 0. Khi c sn phm che gia led pht v
transistor th transistor khng c phn cc, tt nn ng ra cc C mc 1. Khi sn phm i qua th
tn hiu v li mc 0, vy mi sn phm i qua s to ra 1 xung.
Xung c a n ng vo RA4/T0CKI, 3 port B, C v D iu khin 3 led 7 on.
121
Nguyen nh Phu
Lu : hnh 6-23.
Lu khi to 10 m 7 on, timer hot ng m xung ngoi, xung m tch cc cnh ln, t
l chia l 1:1 c ngha l khng chia, cho gi tr m bt u t 0. Vng lp thc hin cng vic c
gi tr ca counter m c em chuyn thnh s BCD, gii m v gi ra port hin th ra led.
Chng trnh:
UNSIGNED INT8 T0;
VOID MAIN()
{
SET_TRIS_B(0x00); SET_TRIS_C(0x00); SET_TRIS_D(0x00);
SETUP_TIMER_0(T0_EXT_L_TO_H | T0_DIV_1);
SET_TIMER0(0);
WHILE(TRUE)
{
T0=GET_TIMER0();
OUTPUT_B(MA7DOAN[T0%10]);
OUTPUT_C(MA7DOAN[T0/10%10]);
OUTPUT_D(MA7DOAN[T0/100]);
}
}
BEGIN
KHI TO COUNTER T0: M XUNG NGOI,

CHN CNH, T L CHIA L 1
GI TR BT U M TIMER0=0
C GI TR TIMER0
GII M HIN TH RA LED
Gii thch chng trnh:

Chng trnh khi to 3 port xut d liu, timer hot ng ch m xung ngoi, h s chia
bng 1, cho gi tr m ban u bng 0.
Vng lp while tin hnh c gi tr ca timer0 gn cho bin T0, tin hnh chia tch tng s
n v, chc, trm, gii m 7 on v gi ra port iu khin led sng.
Do counter T0 ch m 8 bit nn gii hn m t 0 n 255, mun m gi tr ln hn th phi
x l hoc dng counter T1 m 16 bit.
Trong chng trnh trn th mi bt u hin th c 3 s 0, chng trnh sau s c chc nng tt 2
s 0 v ngha ca hng trm v hng chc.
UNSIGNED INT8 T0, MATRAM, MACHUC;
VOID MAIN()
{
SET_TRIS_B(0x00); SET_TRIS_C(0x00); SET_TRIS_D(0x00);
122
Nguyen nh Phu
SETUP_TIMER_0(T0_EXT_L_TO_H | T0_DIV_1);
SET_TIMER0(0);
WHILE(TRUE)
{
T0=GET_TIMER0();
MATRAM=MA7DOAN[T0/100];
MACHUC=MA7DOAN[T0/10%10];
IF (MATRAM==0XC0)
{
MATRAM=0XFF;
IF (MACHUC==0XC0) MACHUC=0XFF;
}
OUTPUT_C(MACHUC);
OUTPUT_D(MATRAM);
}
}
Gii thch chng trnh:

Tch hng trm, hng chc ri tin hnh gii m 7 on, sau so snh hng trm c bng 0 hay
khng, nu bng 0 th tin hnh gn m FFH cho m hng trm, khi gi ra port iu khin led 7 on
th lm led 7 on tt. Tip theo kim tra hng chc cng thc hin tng t.
Trong chng trnh ta kim tra hng trm trc ri mi kim tra hng chc, ti sao ta khng
kim tra hng chc ri n hng trm?
Bi tp 6-4: Hy vit chng trnh m xung ngoi dng T0 hin th kt qu m t 0 n 999
trn 3 led 7 on kt ni trc tip.
trn LCD.
kt ni trc tip vi 2 port, gii hn m t 00 n 99, khi bng 100 th quay v 0.
S mch:

123
Nguyen nh Phu
Gii thch mch:

Mch to xung ging nh trn. Xung by gi a n chn T1CKI/RC0 nn portC khng th
dng iu khin led 7 on v ch cn 2 port y l B v D nn ch kt ni 2 led 7 on trc tip.
Lu : hnh 6-25.
Lu khi to 10 m 7 on, timer hot ng m xung ngoi, xung m tch cc cnh ln, t
l chia l 1:1 c ngha l khng chia, cho gi tr m bt u t 0. Vng lp thc hin cng vic c
gi tr ca counter m c em chuyn thnh s BCD, gii m v gi ra port hin th ra led.
Chng trnh:
UNSIGNED INT16 T1;
VOID MAIN()
{
SET_TRIS_B(0x00); SET_TRIS_D(0x00);
SETUP_TIMER_1(T1_EXTERNAL | T1_DIV_BY_1 );
SET_TIMER1(0);
WHILE(TRUE)
{
T1=GET_TIMER1();
IF (T1/10==0) OUTPUT_D(0XFF);
ELSE
OUTPUT_D(MA7DOAN[T1/10]);
IF(T1==100) SET_TIMER1(0);
}
}
BEGIN

T L CHIA L 1
GI TR BT U M TIMER1=0
C GI TR TIMER1
GII M HIN TH RA LED,
SO SNH GII HN LP LI
Gii thch chng trnh:

Chng trnh khi to 3 port xut d liu, timer hot ng ch m xung ngoi, h s chia
Vng lp while tin hnh c gi tr ca timer1 gn cho bin T1, tin hnh chia tch tng s
n v, chc, gii m 7 on v gi ra port iu khin led sng.
qut ni vi 2 port, gii hn m t 0 n 999, khi bng 1000 th quay v 0.
124
S mch:
Nguyen nh Phu
Hnh 6-26: m xung ngoi dng counter T1 hin th trn 3 led qut.
Gii thch nguyn l hot ng ca mch:

Mch to xung ging nh bi trnh by, xung ng ra ca mch a n ng vo T1CKI port
RC0, dng port B v 3 bit ca portD iu khin 3 led 7 on.
Lu : hnh 6-22.
Lu khi to 10 m 7 on, timer 1 hot ng m xung ngoi, t l chia l 1 c ngha l
khng chia, cho gi tr m bt u t 0. Vng lp thc hin cng vic c gi tr ca counter m
c em chuyn thnh s BCD, gii m v qut led hin th.
BEGIN

T L CHIA L 1:1, KHI TO PORTB, D XUT
TIMER1=0
C GI TR TIMER1
GII M HIN TH RA LED,
SO SNH GII HN LP LI
Hnh 6-22: Lu chng trnh m dng counter T1 ca PIC 16F887.
Chng trnh:
UNSIGNED INT16 T1;
UNSIGNED CHAR MADONVI,MACHUC,MATRAM;
VOID GIAIMA ()
{
MATRAM = MA7DOAN[T1 /100];
MACHUC = MA7DOAN[T1/10 % 10];
MADONVI= MA7DOAN[T1 % 10];
IF (MATRAM == 0XC0)
125
Nguyen nh Phu
{
MATRAM=0XFF;
IF (MACHUC == 0XC0 )
{
MACHUC=0XFF;
}
}
}
VOID HIENTHI()
{
OUTPUT_B(MADONVI);
DELAY_MS(1);
OUTPUT_LOW(PIN_D0);
OUTPUT_B(MACHUC);
DELAY_MS(1);
OUTPUT_LOW(PIN_D1);
OUTPUT_B(MATRAM);
DELAY_MS(1);
OUTPUT_LOW(PIN_D2);
}
VOID MAIN()
{
SETUP_TIMER_1(T1_EXTERNAL | T1_DIV_BY_1);
SET_TIMER1(0);
WHILE(TRUE)
{
T1=GET_TIMER1();
GIAIMA();
HIENTHI();
IF (T1==1000) SET_TIMER1(0);
}
}
Gii thch chng trnh:

Chng trnh khi to 2 port xut d liu, timer 1 hot ng ch m xung ngoi, h s chia
Vng lp while tin hnh c gi tr ca timer1 gn cho bin T1, gi chng trnh chia tch
tng s n v, chc, trm, gii m 7 on v qut led hin th kt qu m.
Chng trnh ny khi thc hin chng trnh con qut hin th 3 led th thi gian delay cho mi
led l 1ms, 3 led mt 3ms, nu xung m c chu k nh hn 3ms th khng hin th theo ng gi tr
m.
trn LCD.
Bi tp 6-7: Hy vit chng trnh m xung ngoi 2 knh dng T0 v T1 hin th kt qu m
t 0 n 9999 trn LCD. T0 hin th hng 1, T1 hin th hng 2.
VIII. CU HI N TP TRC NGHIM

1.
CU HI N TP
Cu s 6-1:
Hy cho bit tn cc thanh ghi lin quan n timer T0 ca vi iu khin PIC16F887.
Cu s 6-2:
Hy cho bit chc nng cc bit trong thanh ghi OPTION_REG ca PIC16F887.
126
Nguyen nh Phu
Cu s 6-3:
Hy cho bit tn cc thanh ghi lin quan n timer T1 ca vi iu khin PIC16F887.
Cu s 6-4:
Hy cho bit chc nng cc bit trong thanh ghi T1CON ca vi iu khin PIC16F887.
Cu s 6-5:
Hy cho bit tn cc c bo ngt v cc bit cho php ngt ca T0 v T1 ca PIC16F887.
Cu s 6-6:
Hy cho bit chc nng cc bit trong thanh ghi T2CON ca vi iu khin PIC16F887.
Cu s 6-7:
Hy cho bit tn c bo ngt v bit cho php ngt timer T2 ca PIC16F887.
2.
CU HI M RNG
Cu s 6-8:
3.
Hy tm hiu cc timer ca vi iu khin PIC18F4550 v so snh vi PIC16F887.
CU HI TRC NGHIM
Cu 6-1:
Vi iu khin PIC 16F887 c my timer:
(a) 3
Cu 6-2:
(b) 4
(b) 4
(b) 12 bit
(b) T2
(b) T2
(c) 16 bit
(d) 8 bit
(c) T0, T1
(d) T0, T2
(c) T0, T1
(d) T0, T2
(b) Gi tr m t FFFFH sang 0000H

(d) Gi tr timer bng vi gi tr PR2
Timer1 ca PIC 16F887 pht sinh yu cu ngt khi:
(a) Gi tr m t FFH sang 00H

(c) Gi tr m t 00H sang FFH
Cu 6-9:
(d) 8 bit

Cu 6-8:
(c) 16 bit
Timer no ca PIC 16F887 ch c b chia trc:
(a) T0, T1, T2

Cu 6-7:
(b) 12 bit
Timer no ca PIC 16F887 c b chia trc vo b chia sau:
(a) T0, T1, T2

Cu 6-6:
(d) 5
Timer T1 ca PIC 16F887 l:
(a) 10 bit
Cu 6-5:
(c) 2
Timer T0 ca PIC 16F887 l:
(a) 10 bit
Cu 6-4:
(d) 6
Vi iu khin PIC 16F887 c my Counter:
(a) 3
Cu 6-3:
(c) 5



Cu 6-10: Timer no ca PIC 16F887 cho php m xung ngoi:

(a) T0, T1, T2
(b) T2
(c) T0, T1
(d) T0, T2
Cu 6-11: Timer no ca PIC 16F887 c ch hot ng ON /OFF:

(a) T0, T1, T2
(b) T2, T1
(c) T0, T1
(d) T1
Cu 6-12: Timer0 ca PIC 16F887 th bit no gn b chia trc cho timer0 hay watchdog timer:
(a) PSA
(b) PS<2 :0>
(c) T0SE
(d) T0SE
Cu 6-13: Timer0 ca PIC 16F887 th bit no la chn xung ni hay xung ngoi:
(a) PSA
(b) PS<2 :0>
(c) T0SE
(d) T0SE
127
Chng 7
GII THIU
ADC CA VI IU KHIN PIC 16F887
KHO ST ADC CA PIC 16F887

KHO ST CC THANH GHI CA PIC 16F887
TRNH T THC HIN CHUYN I ADC
LA CHN NGUN XUNG CHO CHUYN I ADC
CC LNH CA ADC TRONG NGN NG CCS-C
LNH SETUP_ADC(MODE)
LNH SETUP_ADC_PORT(VALUE)
LNH SET_ADC_CHANNEL(CHAN)
LNH VALUE = READ_ ADC(MODE)
CC NG DNG ADC CA PIC 16F887
CU HI N TP
CU HI M RNG
CU HI TRC NGHIM
BI TP
Nguyen nh Phu
I. GII THIU
chng ny kho st vi iu khin giao tip vi vi mch chuyn i tng t sang s (ADC)
v vi iu khin c tch hp ADC thc hin cc ng dng trong o lng v iu khin.
Sau khi kt thc chng ny bn c th kt ni vi iu khin khng c tch hp b chuyn i
ADC vi cc vi mch ADC, s dng c vi iu khin c tch hp ADC, bit trnh t thc hin qu
trnh chuyn i ADC, bit tnh ton phn gii, chuyn i v tnh trung bnh kt qu.
II. ADC CA VI IU KHIN PIC 16F887

Vi iu khin PIC 16F877A c b chuyn i tn hiu tng t sang tn hiu s ADC 10 bit a
hp 8 knh v PIC 16F887 c 14 knh. Mch ADC dng cho cc ng dng giao tip vi tn hiu tng
t c th nhn t cc cm bin nh cm bin nhit LM35, cm bin p sut, cm bin m, cm
bin khong cch,
Phn ny s kho st chi tit khi ADC ca PIC, cc thanh ghi ca khi ADC, trnh t thc hin
chuyn i, tp lnh lp trnh C cho ADC v ng dng ADC o nhit .
1.
KHO ST ADC CA PIC 16F887

ADC ca PIC16F887 c s khi nh hnh 7-1:
Hnh 7-1: S khi ca ADC PIC 16F887.

Chc nng cc thnh phn:
130
AN0 n AN13 (analog) l 14 ng vo ca 14 knh tng t c a n mch a hp.
CHS<3:0> l cc ng vo chn knh ca b a hp tng t.
Tn hiu knh tng t chn s c a n b chuyn i ADC.

Chng 7. ADC.
Nguyen nh Phu
in p tham chiu dng Vref+ c th lp trnh ni vi ngun cung cp dng AV DD

hoc in p tham chiu bn ngoi ni vi ng vo Vref+ ca chn AN3, bit la chn l
VCFG0.
in p tham chiu m Vref- c th lp trnh ni vi ngun cung cp AVSS hoc in p

tham chiu bn ngoi ni vi ng vo Vref- ca chn AN2, bit la chn l VCFG1.
Hai ng vo Vref+ v Vref- c chc nng thit lp phn gii cho ADC.
Bit ADON c chc nng cho php ADC hot ng hoc tt b ADC khi khng hot
ng gim cng sut tiu tn, ADON bng 1 th cho php, bng 0 tt.
Kt qu chuyn i l s nh phn 10 bit s lu vo cp thanh ghi 16 bit c tn l

ADRESH v ADRESL, 10 bit kt qu lu vo thanh ghi 16 bit nn c dng lu l canh
l tri v canh l phi ty thuc vo bit la chn c tn ADFM.
ADC c 14 knh nhng mi thi im ch chuyn i 1 knh v chuyn i knh no th ph

thuc vo 4 bit chn knh CHS4:CHS0. Hai ng vo in p tham chiu dng v m c th lp trnh
ni vi ngun VDD v VSS hoc nhn in p tham chiu t bn ngoi qua 2 chn RA3 v RA2.
Khi ADC c lp vi CPU nn c th hot ng khi CPU ang ch ng do xung cung cp
cho ADC ly t dao ng RC bn trong ca khi ADC.
KHO ST CC THANH GHI CA PIC 16F887
2.
Khi ADC c 4 thanh ghi:

Thanh ghi lu kt qu byte cao: ADRESH (A/D Result High Register)
Thanh ghi lu kt qu byte thp: ADRESL (A/D Result Low Register)
Thanh ghi iu khin ADC th 0: ADCON0 (A/D Control Register 0)
Thanh ghi iu khin ADC th 1: ADCON1 (A/D Control Register 1)
a. Thanh ghi ADCON0 (ADC Control register)cha cc bit iu khin khi ADC nh sau
R/W(0)
R/W(0)
R/W(0)
ADCS1
ADCS0
CHS3
Bit 7
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
CHS2
CHS1
CHS0
GO/DONE
ADON
Bit 0

Bit 7-6 ADCS<1:0>: Cc bit la chn xung chuyn i AD (AD Conversion Clock Select bits)
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (xung clock ly t b dao ng ni bn trong c tn s ln nht l 500 kHz)
Bit 5-3 CHS<3:0>: Cc bit la chn knh tng t (Analog Channel Select bits) nh sau:
CHS<3:0>
Knh
CHS<3:0>
Knh
CHS<3:0>
Knh
CHS<3:0>
Knh
0000
0100
1000
1100
12
0001
0101
1001
1101
13
0010
0110
1010
10
1110
CVREF
0011
0111
1011
11
1111
in p tham chiu
c nh bng 0,6V
Bit 2
GO/ DONE : bit bo trng thi chuyn i ADC (A/D Conversion status bit)
Chng 7. ADC.
131
Nguyen nh Phu
Khi cho GO / DONE 1 bt u thc hin qu trnh chuyn i.

Sau khi chuyn i xong th mch chuyn i lm bit GO/ DONE xung mc 0.
ADON: bit m ngun cho ADC hot ng (AD ON bit):
Bit 0
ADON = 1 c chc nng m ngun cho khi chuyn i ADC hot ng.
ADON = 0 s tt ngun khi chuyn i ADC gim cng sut tiu th.
b. Thanh ghi ADCON1 thit lp cc chn ca port l tng t hoc xut nhp s IO.
R/W(0)
U(0)
ADFM
R/W(0)
R/W(0)
VCFG0
VCFG1
U(0)
U(0)
U(0)
U(0)
U(0): cha dng
Bit 7
Bit 0

ADFM: bit la chn nh dng kt qu ADC (AD Result Format Select bit):
Bit 7
ADFM = 1: c chc nng canh l phi, 6 bit MSB ca ADRESH c gi tr l 0.

ADFM = 0: c chc nng canh l tri, 6 bit LSB ca ADRESL c gi tr l 0.
VCFG1: bit la chn in p tham chiu (Voltage reference bit)
Bit 5
VCFG1 = 1: c chc nng ni in p tham chiu Vref- vi ng vo AN3.

VCFG1 = 0: c chc nng ni in p tham chiu Vref- vi VSS.
VCFG0: bit la chn in p tham chiu (Voltage reference bit)
Bit 4
VCFG0 = 1: c chc nng ni in p tham chiu Vref+ vi ng vo AN3.

VCFG0 = 0: c chc nng ni in p tham chiu Vref+ vi VDD.
Bit 6, 3-0: cha dng nu c s c gi tr l 0
c. Thanh ghi ADRESH v ADRESL
Cp thanh ghi 16 bit ADRESH: ADRESL dng lu kt qu chuyn i 10 bit ca ADC sau
khi chuyn i xong. Do kt qu ch c 10 bit nhng lu trong cp thanh ghi 16 bit nn c 2 kiu nh
dng ty thuc vo bit ADFM (ADC Format).
Hnh sau trnh by 2 kiu nh dng ca cp thanh ghi kt qu:
ADRESH
ADRESL
KT QU 10 BIT, CANH L PHI ADFM = 1

ADRESH
ADRESL
KT QU 10 BIT, CANH L TRI ADFM = 0
Hnh 7-4: nh dng cp thanh ghi lu kt qu.

Chc nng ca canh l phc v cho 2 kh nng x l kt qu: nu ly kt qu 10 bit x l th
nn chn ch canh l phi, cn nu ly kt qu 8 bit th chn ch canh l tri v ch ly kt qu
ca thanh ghi byte cao ADRESH, b i 2 bit c trng s thp nht ca thanh ghi ADRESL v ch
132
Chng 7. ADC.
Nguyen nh Phu
n tnh ton gi tr, trong chng trnh C nu khng khai bo thuc tnh ADC 10 bit th phn mm t
ng ly gi tr 8 bit cao.
3.
TRNH T THC HIN CHUYN I ADC

thc hin chuyn i ADC th phi thc hin cc bc sau:
Bc 1: Cu hnh cho port:
Cu hnh cho cc port ch ng vo tng t.
Khng c nh cu hnh cho cc port ch xut d liu.
Bc 2: Cu hnh cho module ADC:
Chn xung clock cho chuyn i ADC.
nh cu hnh cho in p chun.
Chn knh ng vo tng t cn chuyn i.
Chn nh dng cho 2 thanh ghi lu kt qu.
M ngun cho ADC.
Bc 3: Thit lp cu hnh ngt ADC nu s dng:
Xa c bo ngt ADIF ca ADC.
Cho bit ADIE bng 1 cho php ADC ngt.
Cho bit PEIE bng 1 cho php ngt ngoi vi.
Cho bit GIE bng 1 cho php ngt ton cc.
Bc 4: Ch ht thi gian n nh theo yu cu.
Bc 5: Bt u chuyn i bng cch cho bit GO/ DONE ln 1
Bc 6: Kim tra chuyn i ADC kt thc bng cch:
Kim tra lin tc bit GO/ DONE nu v 0 th qu trnh chuyn i kt thc.
Nu dng ngt th ch ngt ADC xy ra.
Bc 7: c cp thanh ghi kt qu (ADRESH: ADRESL), xa bit ADIF nu dng ngt.
Bc 8: Thc hin chuyn i k tip.
4.
LA CHN NGUN XUNG CHO CHUYN I ADC
Tn s xung clock cho b chuyn i ADC c la chn bng phn mm bi cc bit ADCS
nm trong thanh ghi ADCON0. C 4 la chn cho ngun xung clock nh sau:
FOSC/2
FOSC/8
FOSC/32
FRC ly t b dao ng bn trong.
Bng 7-1: Tn s xung clock ty chn ph thuc vo tn s b dao ng:
Chu k xung clock ca ADC (TAD)
Tn s thit b (FOSC)
Xung clock cho ADC
ADCS<1:0>
20MHz
8MHz
4MHz
1MHz
FOSC/2
00
100ns
250ns
500ns
2s
FOSC/8
01
400ns
1s
2s
8s
FOSC/32
10
1.6s
4s
8s
32s
Chng 7. ADC.
133
Nguyen nh Phu
FRC
11
2-6s
2-6s
2-6s
2-6s
Thi gian chuyn i ADC cho mi bit c xc nh bi chu k TAD. chuyn i hon tt
10 bit s dng ti thiu 11 chu k TAD nh hnh 7-5.
Hnh 7-5: Thi gian chuyn i 10 bit.
III. CC LNH CA ADC TRONG NGN NG CCS-C

Cc lnh ca ngn ng lp trnh C lin quan n ADC bao gm:
Lnh SETUP_ADC(MODE)
Lnh SETUP_ADC_PORT(VALUE)
Lnh SET_ADC_CHANNEL(CHAN)
Lnh VALUE=READ_ADC(MODE)
1.
LNH SETUP_ADC(MODE) - LNH NH CU HNH CHO ADC
C php:
Thng s:
Chc nng:
C hiu lc:
setup_adc (mode);
mode- Analog to digital mode. Xem trong file device.
nh cu hnh cho ADC
Cho cc PIC c tch hp ADC.
V d 7-1:
setup_adc(ADC_CLOCK_INTERNAL );
2.
LNH SETUP_ADC_PORT(VALUE) - LNH NH CU HNH CHO PORT
C php:
Hng s:
Chc nng:
Hiu lc:
V d 7-2:
3.
LNH SET_ADC_CHANNEL(chan) - LNH CHN KNH ADC
C php:
Thng s:
Chc
nng:
V d 7-3:
4.
Set_adc_channel (chan) - chn knh cn chuyn i khi o nhiu hn 1 knh, nu ch

o 1 knh th khng cn.
Chan l th t knh cn chuyn i. Knh bt u t s 0.
Chn knh cn chuyn i ADC
Phi ch 1 khong thi gian ngn khi chuyn knh, thng th thi gian ch khong
10s.
SET_ADC_CHANNEL(2);
DELAY_US(10);
VALUE = READ_ADC();
LNH value=READ_ADC(mode) - LNH C KT QU CHUYN I ADC
C php:
134
setup_adc_ports (value)
value - l hng s nh ngha trong file devices .h
Thit lp chn ca ADC l tng t, s hoc t hp c 2.
Cho cc PIC c ADC.
setup_adc_ports( ALL_ANALOG ); // s dng tt c cc knh tng t
value = read_adc ([mode]) - c kt qu sau khi chuyn i xong

Chng 7. ADC.
Nguyen nh Phu
Hng s:
Tr v:
Chc nng:
V d 7-4:
mode l 1 trong cc hng s sau:

ADC_START_AND_READ (thc hin c lin tc, mc nhin l mode ny)
ADC_START_ONLY (bt u chuyn i)
ADC_READ_ONLY (c kt qu ca ln chuyn i sau cng)
Kt qu 8 bit hay 16 bit ty thuc v khai bo #DEVICE ADC= directive.
Lnh ny s c gi tr s sau khi chuyn i xong
Khai bo #DEVICE ADC= directive nh sau:
#DEVICE
8 bit
10 bit
11 bit
16 bit
setup_adc( ADC_CLOCK_INTERNAL );
setup_adc_ports( ALL_ANALOG );
set_adc_channel(1);
read_adc(ADC_START_ONLY);
sleep();
value=read_adc(ADC_READ_ONLY);
IV. NG DNG ADC CA PIC 16F887

Bi 7-1: Dng ADC ca vi iu khin PIC 16F887 v cm bin LM35 o nhit hin th
trn 3 led 7 on anode chung dng 3 port, ch hin th n v, chc v trm. S dng ngun in p
tham chiu VREF+ ni vi VDD bng 5V v VREF- ni vi ngun VSS bng 0V.
S mch:
Hnh 7-6: S mch o nhit dng PIC16F887 hin th trn 3 led trc tip.
Tnh ton phn gii
Theo yu cu th cc ng vo in p tham chiu l V REF 0V ,V REF VDD 5V

V
V
5000mV
4,887mV
Nn phn gii (step size) l SS REF 10 REF
2 1
1023
Thng s 210 l do ADC 10 bit.
FS SS 1023 4,887mV 1023 5,000mV 5V
in p ton giai full scale = FS:
phn gii ADC l 4,887mV khng tng thch vi phn gii ca cm bin LM35 bng
10mV, t l chnh lch l:
10mV
2,046
4,887mV
c kt qu hin th ng th ly kt qu chuyn i chia cho t l chnh lch.
Chng 7. ADC.
135
Nguyen nh Phu
Lu :
BEGIN
LU 10 M VO BN, KHI TO ADC: CHN XUNG

CLOCK, CHN KNH, KHI TO PORT, KHI TO
CC BIN
THC HIN CHUYN I 200 LN

CHIA LY TRUNG BNH.
X L NG H S CHUYN I.
GII M, HIN TH
Chng trnh:
UNSIGNED INT16 KQADC;
UNSIGNED INT J,MATRAM;
VOID HIEN_THI()
{
MATRAM = MA7DOAN[KQADC/100];
IF (MATRAM == 0XC0)
MATRAM=0XFF;
OUTPUT_B(MA7DOAN[KQADC%10]);
OUTPUT_C(MA7DOAN[KQADC/10%10]);
OUTPUT_D(MA_TRAM);
}
VOID MAIN()
{
SET_TRIS_C(0x00); SET_TRIS_A(0xFF);
SETUP_ADC(ADC_CLOCK_DIV_2);
SETUP_ADC_PORTS(SAN0);
SET_ADC_CHANNEL(0);
WHILE(TRUE)
{
KQADC=0;
FOR (J=0; J<200; J++)
{
KQADC=KQADC+READ_ADC();
DELAY_MS(1);
}
KQADC= KQADC /2.046;
KQADC=KQADC/200;
HIEN_THI();
}
}
136
Gii thch chng trnh:

Chng 7. ADC.
Nguyen nh Phu
Trong vng lp while ta cho bin KQADC bng 0, vng lp for thc hin 200 ln o, kt qu
cng dn vo bin KQADC.
Kt qu ng ca 200 ln o s chia cho 200 ln c kt qu o trung bnh v chia cho h s
2.046 c kt qu ng h s phn gii, sau tin hnh gii m hin th v xo s 0 v ngha.
Bi 7-2: Thm vo bi 7-1 yu cu: khi nhit tng nhng nh hn 40 th relay ng, khi
ln hn 40 th relay ngt, khi nhit gim thp hn 35 th relay ng tr li.
S mch:
Hnh 7-8: S mch giao tip iu khin relay, triac, buzzer.
Gii thch s mch:

S mch gm 3 i tng iu khin:
Buzzer to m thanh bip dng 1 buzzer v mch khuch i dng transistor, transistor vi
dng lm vic ln hn dng ca buzzer khong 120mA. Mc 1 lm buzzer ku, mc 0 tt buzzer.
Mch iu khin ti ac dng triac v opto cch ly. Mc 1 lm triac dn, mc 0 lm triac tt.
Mch iu khin ti cng sut dng relay v opto cch ly. Mc 1 lm opto dn, transistor dn,
relay dn, mc 0 lm opto tt, transistor tt, relay tt.
Khi s dng i tng no th ta ch cn kt ni 1 port ca vi iu khin vi 1 trong cc mch
trn.
Lu :
Chng 7. ADC.
137
Nguyen nh Phu
BEGIN

CC BIN
THC HIN CHUYN I V HIN TH 200 LN

CHIA LY TRUNG BNH,
X L NG H S CHUYN I,
CHIA TCH TNG S GII M, HIN TH
SO SNH NHIT IU KHIN TT M RELAY
Chng trnh:
#DEFINE RELAY
PIN_A3
IF (KQADC>40)
ELSE
(KQADC<35)
OUTPUT_LOW(RELAY);
OUTPUT_HIGH(RELAY);
Gii thch chng trnh:

Chng trnh ny ging nh bi 7-1, ch thm phn khai bo nh ngha bit iu khin RELAY
l RA3 (chn port no cha dng l c). Trong chng trnh chnh th thm hng lnh trn c chc
nng so snh nu nhit ln hn 40 th relay tt, nh hn 35 th m.
Bi 7-3: Dng ADC ca vi iu khin PIC 16F887 v cm bin LM35 o nhit hin th
trn 3 led 7 on anode chung kt ni thep phng php qut, s dng ngun in p tham chiu
VREF+ ni vi VDD bng 5V v VREF- ni vi ngun VSS bng 0V.
S mch:
Hnh 7-10: S mch o nhit dng PIC16F887, hin th 3 led qut.
138
Gii thch s mch:

Chng 7. ADC.
Nguyen nh Phu
Mch dng 3 led 7 on hin th kt qu nhit kt ni theo phng php qut s dng port
B v 3 bit ca port D iu khin 3 transistor.
Cm bin LM35 ni vi ng vo knh tng t th 0 (SAN0).
Mch reset v cc chn kt ni mch np, t thch anh 20MHz.
Lu :
BEGIN

CC BIN
THC HIN CHUYN I V HIN TH 100 LN

CHIA LY NHIT TRUNG BNH.
X L NG H S CHUYN I.
GII M.
Hnh 7-11: Lu chuyn i ADC o nhit hin th led qut.
Chng trnh:
UNSIGNED INT16 KQADC;
UNSIGNED INT
J, MADONVI, MACHUC, MATRAM;
VOID GIAIMA ()
{
MATRAM = MA7DOAN[KQADC /100];
MACHUC = MA7DOAN[KQADC /10 % 10];
MADONVI= MA7DOAN[KQADC % 10];
IF (MATRAM == 0XC0) MATRAM=0XFF;
}
VOID HIENTHI ()
{
OUTPUT_B(MADONVI);
OUTPUT_LOW(PIN_D0);
DELAY_MS(1);
OUTPUT_B(MACHUC);
OUTPUT_LOW(PIN_D1);
DELAY_MS(1);
OUTPUT_B(MATRAM);
OUTPUT_LOW(PIN_D2);
DELAY_MS(1);
}
VOID MAIN()
{
SET_TRIS_A(0x01);
SET_ADC_CHANNEL(0);
WHILE(TRUE)
{
KQADC=0;
FOR (J=0; J<100; J++)
{
Chng 7. ADC.
139
Nguyen nh Phu
KQADC=KQADC+READ_ADC();
HIENTHI();
}
KQADC=KQADC/100;
GIAIMA();
}
}
Gii thch chng trnh:

Trong vng lp while ta cho bin KQADC bng 0, vng lp for thc hin 100 ln o, kt qu
cng dn vo bin KQADC.
Chng trnh ny ging nh cc bi trc, s khc nhau l trong qu trnh chuyn i th thc
hin hin th 3 led 7 on sng lin tc v v thi gian qut 3 led di nn ta gim bt s ln o trung
bnh xung cn 100 tng nhanh p ng thi gian.
cc bi ny th cng vic chnh l chuyn i ADC v hin th, nu cc chng trnh ng dng
ln thc hin nhiu cng vic th ta phi gim s ln o trung bnh xung cho ph hp vi p ng
thi gian.
V.
1.
CU HI N TP
Cu 7-1: Hy trnh by cu trc khi ADC ca PIC16F887.
Cu 7-2: Hy cho bit chc nng ca cc tn hiu VREF+ v VREF-.
Cu 7-3: Hy cho bit trnh t chuyn i ADC ca IC16F887.
Cu 7-4: Hy so snh ADC ca IC16F887 v PIC 16F877A.
2.
CU HI M RNG
Cu 7-6: Hy kho st cu trc ADC ca PIC18F4550 v PIC16F887.
3.
CU HI TRC NGHIM
Cu 7-1:
Cng thc tnh phn gii ADC ca PIC16F887 l:
VREF VREF
210 1
V VREF
(c) SS I
(210 1)
VREF VREF
(a) SS
Cu 7-2:
(a) 8
Cu 7-3:
(a) 8
Cu 7-4:
(a) 8
Cu 7-5:
(a) 2
Cu 7-6:
PIC 16F877A c b ADC bao nhiu bit:

(b) 10
(c) 12
(d) 16
(c) 12
(d) 14
(c) 12
(d) 14
(c) 4
(d) 5
PIC 16F877A c b ADC bao nhiu knh:

(b) 10
PIC 16F887 c b ADC bao nhiu knh:
(b) 10
ADC ca PIC 16F887 c bao nhiu thanh ghi:
(b) 3
Cc thanh ghi lu kt qu ADC ca PIC 16F887 c tn l:
(a) ADCON1 v ADCON0

(c) ADRESH v ADRESL
140
VI VREF
VI VREF
V VREF
(d) SS I
(210 )
VREF VREF
(b) SS
(b) ADRES1 v ADRES0

(d) ADCONH v ADCONL
Chng 7. ADC.
Nguyen nh Phu
Cu 7-7:
Cc thanh ghi iu khin ADC ca PIC 16F887 c tn l:
(a) ADCON1 v ADCON0

(c) ADRESH v ADRESL
Cu 7-8:
Cc bit la chn knh ADC ca PIC 16F887 c tn l:
(a) ADCS2: ADCS0

Cu 7-9:
(b) ADRES1 v ADRES0

(d) ADCONH v ADCONL
(b) CHS2: CHS0
(c) PCFG2: PCFG0
(d) CHS3: CHS0
C bao nhiu bit la chn knh ADC ca PIC 16F887:
(a) 2
(b) 4
(c) 3
(d) 8
Cu 7-10: C bao nhiu bit la chn cu hnh port cho ADC ca PIC 16F887:
(a) 2
(b) 4
(c) 3
(d) 8
Cu 7-11: Cc bit la chn cu hnh cho ADC ca PIC 16F887 c tn l:

(a) ADCS2: ADCS0
(b) PCFG3: PCFG0
(c) PCFG2: PCFG0
(d) CHS3: CHS0
Cu 7-12: C bao nhiu bit la chn ngun xung clock cho ADC ca PIC 16F887:
(a) 2
(b) 4
(c) 3
Cu 7-13: Cc bit la chn xung clock cho ADC ca PIC 16F887 c tn l:
(a) ADCS2: ADCS0
(b) PCFG3: PCFG0
(c) PCFG2: PCFG0
(d) 8
(d) CHS3: CHS0
Cu 7-14: Lnh SETUP_ADC(MODE) ca PIC 16F887 c chc nng l:

(a) Chn knh
(b) Chn phn gii
(c) c gi tr
(d) nh cu hnh
Cu 7-15: Bit ra lnh chuyn i ADC ca PIC 16F887 c tn l:

(a) ADCS2: ADCS0
(b) GO/DONE
(c) ADON
(d) ADFM
Cu 7-16: Bit chn nh dng kt qu ADC canh tri hoc phi ca PIC16F887 c tn l:
(a) ADCS2: ADCS0
(b) GO/DONE
(c) ADON
(d) ADFM
Cu 7-17: Lnh SETUP_ADC_PORT(VALUE) ca PIC 16F887 c chc nng l:

(a) Thit lp cc knh
(b) Chn phn gii
(c) c gi tr
(d) Chn tc
Cu 7-18:
Lnh SET_ADC_CHANNEL(CHAN) ca PIC 16F887 c chc nng l:
(a) Thit lp cc knh
(b) Chn phn gii
(c) c gi tr
(d) Chn knh
Cu 7-19: Lnh VALUE=READ_ADC(MODE) ca PIC 16F887 c chc nng l:
(a) Thit lp cc knh
(b) Chn phn gii
(c) c gi tr
(d) Chn tc
Cu 7-20: Cng thc tnh gi tr s nh phn sau khi chuyn i ADC ca PIC16F887 l:
VREF VREF
210 1
V VREF
(c) N I
SS
(a) N
4.
VI VREF
SS
VI VREF 10
(2 )
(d) N
SS
(b) N
BI TP
Bi tp 7-1:
Bi tp 7-2:
Mch o nhit 2 knh dng cm bin LM35, vi iu khin PIC16F887 v 3 led 7

on.
Hy v mch, vit lu v chng trnh o nhit 2 knh ln lt hin th trn 3 led,
mi knh o trong khong thi gian 1s, nh thi 1 giy chuyn knh dng Timer T1.
Mch o nhit 8 knh dng cm bin LM35, vi iu khin PIC16F887 v 3 led 7
on.
Hy v mch, vit lu v chng trnh o nhit 8 knh ln lt hin th trn 3 led,
mi knh o trong khong thi gian 1s, nh thi 1 giy chuyn knh dng Timer T1.
Chng 7. ADC.
141
Nguyen nh Phu
Bi tp 7-3:
Mch o nhit dng cm bin LM35, vi iu khin PIC16F887 v LCD 16x2.

Hy v mch, vit lu v chng trnh o nhit ni vi knh AN0 v hin th kt
qu trn LCD.
Bi tp 7-4:
Mch o nhit 2 knh dng 2 cm bin LM35 v vi iu khin PIC16F887 hin th

kt qu o knh 1 hng 1, knh 2 hng 2 ca LCD 16x2.
Hy v mch, vit lu v chng trnh.
Bi tp 7-5:
Mch o nhit 1 knh dng cm bin LM35 v m sn phm dng vi iu khin

PIC16F887 hin th kt qu o hng 1 v kt qu m hng 2 ca LCD 16x2.
Hy v mch, vit lu v chng trnh.
142
Chng 7. ADC.
Chng 8
GII THIU
TNG QUAN V NGT
NGT CA VI IU KHIN PIC16F887
CC LNH NGT CA PIC16F887 TRONG NGN NG CCS-C
CC NGUN NGT CA PIC16F887

CC THANH GHI NGT CA PIC16F887
o Thanh ghi INTCON (Interrupt CONTROL)
o Thanh ghi PIE1 (Peripheral Interrupt Enable) v PIR1 (Peripheral Interrupt Request)
o Thanh ghi PIE2 (Peripheral Interrupt Enable) v PIR2 (Peripheral Interrupt Request)
LNH ENABLE_INTERRUPT(LEVEL)
LNH DISABLE_INTERRUPT(LEVEL)

CU HI N TP
CU HI M RNG
CU HI TRC NGHIM
Vi x ly
Nguyen nh Phu
I. GII THIU
Ngt c nhiu tin ch trong iu khin nn hu ht cc vi iu khin u tch hp, chng ny
chng ta s kho st nguyn l hot ng ca ngt, cc ngun ngt, vector a ch ngt, vit chng
trnh con phc v ngt cho cc ng dng.
Sau khi kt thc chng ny bn c th s dng c ngt ca cc vi iu khin.
II. TNG QUAN V NGT

Ngt s dng trong vi x l hay vi iu khin hot ng nh sau: vi x l hay vi iu khin lun
thc hin mt chng trnh thng gi l chng trnh chnh, khi c tc ng t bn ngoi bng phn
cng hay tc ng bn trong lm cho vi x l ngng thc hin chng trnh chnh thc hin mt
chng trnh khc (cn gi l chng trnh phc v ngt ISR) v sau khi thc hin xong vi x l tr li
thc hin tip chng trnh chnh. Qu trnh lm gin on vi x l thc hin chng trnh chnh xem
nh l ngt.
C nhiu tc ng lm ngng chng trnh chnh gi l cc ngun ngt, v d khi timer/counter
m trn s pht sinh yu cu ngt.
Ngt ng mt vai tr quan trng trong lp trnh iu khin, vi x l hay vi iu khin s dng
ngt p ng nhiu s kin quan trng khc trong m vn m bo thc hin c chng trnh
chnh.
V d trong khi vi iu khin ang thc hin chng trnh chnh th c d liu t h thng khc
gi n, khi vi iu khin ngng chng trnh chnh thc hin chng trnh phc v ngt nhn
d liu xong ri tr li tip tc thc hin chng trnh chnh, hoc c mt tn hiu bo ngt t bn
ngoi th vi iu khin s ngng thc hin chng trnh chnh thc hin chng trnh ngt ri tip
tc thc hin chng trnh chnh.
C th s dng ngt yu cu vi iu khin thc hin nhiu chng trnh cng mt lc c
ngha l cc chng trnh c thc hin xoay vng.
CPU thc hin chng trnh trong trng hp c ngt v khng c ngt nh hnh 8-1.
Time
CHNG TRNH CHNH (MP: MAIN PROGRAM)

(a) Chng trnh chnh c thc hin lin tc, khng b gin on.
Time
ISP
MP
ISP
MP
ISP
MP
MP
(b) Chng trnh chnh b gin on thc hin chng trnh con phc v ngt.
Hnh 8-1: Vi iu khin thc hin chng trnh chnh trong 2 trng hp khng v c ngt.
III. NGT CA VI IU KHIN PIC16F887

1.
CC NGUN NGT CA PIC16F887
Vi iu khin PIC 16F887 c nhiu ngun ngt:

Ngt ngoi RB0/INT.
Ngt ca timer T0 khi m trn.
144
Chng 8. Ngat.
Nguyen nh Phu
2.
Ngt ca timer T1 khi m trn.

Ngt ca timer T2 khi gi tr m bng gi tr ca thanh ghi PR2.
Ngt portB thay i.
Ngt ca 2 b so snh in p tng t.
Ngt ca b chuyn i ADC.
Ngt khi ghi d liu vo Eeprom.
Ngt khi b gim st pht hin ngun xung clock b hng.
Ngt ca khi CCP tng cng.
Ngt truyn v nhn d liu EUSART.
Ngt nh thc CPU vi ngun cng sut cc thp.
Ngt ca khi truyn d liu ng b MSSP.
CC THANH GHI NGT CA PIC16F887
Trong vi iu khin PIC16F887 c 5 thanh ghi phc v cho ngt l INTCON, PIE1, PIE2, PIR1,
PIR2. T chc ca tng thanh ghi nh sau:
a.
Thanh ghi INTCON (Interrupt CONTROL)
T chc ca thanh ghi nh hnh sau:
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
GIE
PEIE
T0IE
INTE
RBIE
R/W(0)
T0IF
R/W(0)
INTF
R/W(X)
RBIF

Bng 8-1: Tm tt chc nng cc bit trong thanh ghi cho php ngt INTCON c a ch 0x0B:
Bit
INTCON.7
INTCON.6
INTCON.5
INTCON.4
INTCON.3
INTCON.2
INTCON.1
INTCON.0
K hiu
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
Chc nng (cho php = 1; cm = 0)

Bit cho php/cm ton b cc ngun ngt.
Bit cho php ngt ngoi vi
Bit cho php ngt timer T0.
Bit cho php ngt ngoi.
Bit cho php ngt portB thay i.
C bo ngt ca timer T0.
C bo ngt ca ngt ngoi.
C bo ngt portB thay i.
Trong thanh ghi trn th bit GIE l bit cho php/cm ngt ton b cc ngun ngt, bit PEIE cho
php/cm cc ngun ngt ngoi vi.
Cc bit cn li l bit cho php/cm ngt v c bo ngt ca ngt cng INT, ngt portB thay i
v ngt ca timer0.
V d 8-1: Mun cho php timer0 ngt th lp trnh cho cc bit nh sau: GIE = 1, T0IE = 1.
b.
Thanh ghi PIE1 (Peripheral Interrupt Enable) v PIR1 (Peripheral Interrupt Request)
Chng 8. Ngat.
145
Vi x ly
R/W(0)
-
ADIE
RCIE
R/W(0)
-
R/W(0)
ADIF
R/W(0)
RCIF
Nguyen nh Phu
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF

Bng 8-2: Tm tt chc nng cc bit trong thanh ghi cho php ngt PIE1 c a ch 0x8C:
Bit
PIE1.7
PIE1.6
PIE1.5
PIE1.4
PIE1.3
PIE1.2
PIE1.1
PIE1.0
K hiu
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE

Bit cha c chc nng.
Bit cho php ADC ngt.
Bit cho php ngt nhn d liu.
Bit cho php ngt pht d liu.
Bit cho php ngt truyn d liu ng b.
Bit cho php ngt khi CCP1.
Bit cho php ngt ca timer T2.
Bit cho php ngt ca timer T1.
Bng 8-3: Tm tt chc nng cc bit trong thanh ghi cho php ngt PIR1 c a ch 0x0C:
Bit
PIR1.7
PIR1.6
PIR1.5
PIR1.4
PIR1.3
PIR1.2
PIR1.1
PIR1.0
K hiu
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
Chc nng (ngt xy ra = 1; cha xy ra = 0)

Bit cha c chc nng.
C bo ngt ca ADC.
C bo ngt nhn d liu.
C bo ngt pht d liu.
C bo ngt truyn d liu ng b.
C bo ngt khi CCP1.
Hai thanh ghi cha cc bit cho php ngt v c bo ngt tng ng ca 7 ngt ngoi vi.
V d 8-2: Mun cho php timer2 ngt th lp trnh cho cc bit nh sau: GIE = 1, TMR2IE = 1
v bit cho php ngt ngoi vi PEIE = 1.
c.
Thanh ghi PIE2 (Peripheral Interrupt Enable) v PIR2 (Peripheral Interrupt Request)
R/W(0)
OSFIE
R/W(0)
OSFIF
R/W(0)
R/W(0)
C2IE
C1IE
R/W(0)
R/W(0)
C2IF
C1IF
R/W(0)
R/W(0)
EEIE
BCLIE
R/W(0)
R/W(0)
EEIF
BCLIF
R/W(0)
ULPWUIE
R/W(0)
-
R/W(0)
ULPWUIF
CCP2IE
R/W(0)
CCP2IF

146
Chng 8. Ngat.
Nguyen nh Phu
Bng 8-4: Tm tt chc nng cc bit trong thanh ghi cho php ngt PIE2 c a ch 0x8D:
Bit
PIE2.7
PIE2.6
PIE2.5
PIE2.4
PIE2.3
PIE2.2
PIE2.1
PIE2.0
K hiu
OSFIE
C2IE
C1IE
EEIE
BCLIE
ULWUIE
CCP2IE

Bit cho php ngt ca b dao ng hng.
Bit cho php ngt ca khi so snh 2.
Bit cho php ngt ca khi so snh 1.
Bit cho php ngt ca b nh eeprom.
Bit cho php ngt xung t truyn d liu I2C.
Bit cho php ngt ca b nh thc CPU vi cng sut cc thp.
Bit cha c chc nng.
Bit cho php ngt ca CCP2.
Bng 8-5: Tm tt chc nng cc bit trong thanh ghi cho php ngt PIR2 c a ch 0x0D:
Bit
PIR2.7
PIR2.6
PIR2.5
PIR2.4
PIR2.3
PIR2.2
PIR2.1
PIR2.0
K hiu
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULWUIF
CCP2IF

C bo ngt ca b dao ng hng.
C bo ngt ca khi so snh 2.
C bo ngt ca khi so snh 1.
C bo ngt ca b nh eeprom.
C bo ngt xung t truyn d liu I2C.
C bo ngt ca b nh thc CPU vi cng sut cc thp.
Bit cha c chc nng.
C bo ngt ca CCP2.
Cu trc mch in ngt ca PIC16F877 nh hnh 8-5:

Trong mch in chng ta c th nhn thy CPU thc hin ngt ca timer0 th phi hi cc
iu kin sau: bit cho php ngt T0IE = 1, timer0 m v trn lm c bo ngt T0IF = 1 v bit cho
php ngt ton cc GIE = 1.
Khi mt ngt c p ng th bit GIE b xa khng cho php bt k ngt no khc xy ra
na, a ch tr v c ct vo trong ngn xp v thanh ghi PC c np a ch 0004h.
Do ch c 1 vector a ch ngt l 0004H th lm sao bit ngt no ang thc hin?
Nu trong chng trnh ch s dng c 1 ngt th khi ngt xy ra th chng trnh con phc ngt
s c thc hin.
Nu trong chng trnh s dng nhiu ngun ngt th chng trnh ngt vit ti a ch 0004H s
kim tra xem c bo ngt no ln 1, nu bng 0 th kim tra tip c khc, nu bng 1 th thc hin
chng trnh ngt tng ng.
Qu trnh kim tra c bo ngt no bng 1 v thc hin chng trnh phc v ngt tng ng
trc cng xc nh lun th t u tin ngt.
Th t ngt v u tin ngt ca PIC16F887 khc vi vi iu khin AT89S52.
Chng 8. Ngat.
147
Vi x ly
Nguyen nh Phu
Hnh 8-5: Mch in ngt ca PIC16F887.
IV. CC LNH NGT CA PIC16F887 TRONG NGN NG PIC-C

Cc lnh ca ngn ng lp trnh C lin quan n ngt bao gm:
1.
LNH
ENABLE_INTERRUPTS(LEVEL): c chc nng cho php ngt.
2.
LNH
DISABLE_INTERRUPTS(LEVEL): c chc nng cm ngt.
V.
Phn ny trnh by cc ng dng ngt n gin ca PIC16F887, qua cc ng dng ny gip bn

bit vit lu cho nhng ng dng c dng ngt, bit vit chng trnh c s dng ngt v c bit l
bit thm cch tnh ton thi gian delay cho cc timer. T cc kin thc c bn ny s gip bn hiu v
vit c cc ng dng khc.
Bi 8-1:
148
Dng vi iu khin PIC16F887 iu khin 8 led n sng tt s dng ngt timer T1

vi chu k delay l 262ms.
S mch:
Chng 8. Ngat.
Nguyen nh Phu
Hnh 8-6: iu khin 8 led sng tt.

S dng portB iu khin 8 led n, thch anh s dng l 20Mhz.
Lu :
BEGIN

H S CHIA BNG 8, PORTB XUT, T1 = 0, CHO
PHP T1 NGT
NGT T1
O TRNG THI CA CC LED
QUAY V
END
Hnh 8-7: Lu iu khin 8 led sng tt nh thi 262ms dng ngt.
Chng trnh:
UNSIGNED INT8 X;
#int_timer1
void interrupt_timer1()
{
X=~X;
OUTPUT_D(X);
}
VOID MAIN()
{
SET_TRIS_D(0x00);
X=0X00; OUTPUT_D(X);
SET_TIMER1(0);
ENABLE_INTERRUPTS(GLOBAL); ENABLE_INTERRUPTS(INT_TIMER1);
WHILE(TRUE)
{
}
}
Gii thch chng trnh v tnh ton thi gian delay:

Chng trnh ny v c bn ging chng trnh vit chng 6 phn timer. Bi ny s dng
ngt khi timer m b trn, chng trnh chnh thc hin cho php ngt ton cc v cho php Timer1
ngt. Sau khi Timer1 m v trn th chng trnh chnh s ngng v thc hin chng trnh phc v
Chng 8. Ngat.
149
Vi x ly
Nguyen nh Phu
ngt ca Timer1 bao gm 2 lnh: o gi tr ca bin X v xut d liu ra portD v kt thc tr li

chng trnh chnh cho n khi trn ln tip theo.
Thi gian tnh ton ging nh bi 6-1, thi gian sng bng thi gian tt l 105ms, chu k 210ms.
Chng trnh chnh sau khi thc hin khi to xong th khng lm g c nn ta cha thy r u
im ca ngt.
Khai bo nhn ca chng trnh ngt cng nh cc tn cho trong file th vin ca vi iu khin,
khng c t tn khc tr khi bn nh ngha li.
Bi 8-2:
Chng trnh m giy chnh xc hin th trn 2 led 7 on qut dng vi iu khin PIC
16F887 dng Timer v ngt.
S mch:
Hnh 8-8: Mch giao tip 2 led 7 on qut hin th m giy.
Lu :
BEGIN
NGT TIMER1
TNG BIN M NGT BDT
KHI TO LI TIMER1 M TIP
KHI TO TIMER NH THI

100MS, BO NGT
RETI
GIY = 0
GII M GIY, HIN TH
BDN = 10 (1S)
S
X L TNG GIY
Hnh 8-9: Lu m giy dng Timer nh thi bo ngt.

150
Chng 8. Ngat.
Nguyen nh Phu
Chng trnh:
UNSIGNED INT8 GIAY, BDT;
#int_timer1
{
SET_TIMER1(3036);
BDT++;
}
VOID HIENTHI()
{
OUTPUT_B(MA7DOAN[GIAY %10]); OUTPUT_LOW(PIN_D0);
DELAY_MS(1);
OUTPUT_B(MA7DOAN[GIAY/10]);
OUTPUT_LOW(PIN_D1);
DELAY_MS(1);
}
VOID MAIN()
{
SET_TIMER1(3036);
ENABLE_INTERRUPTS(GLOBAL); ENABLE_INTERRUPTS(INT_TIMER1);
GIAY = 0; BDT=0;
WHILE(TRUE)
{
IF (BDT >=10)
{
BDT = 0;
IF (GIAY == 59) GIAY = 0;
ELSE
GIAY++;
}
ELSE HIENTHI();
}
}
Gii thch chng trnh:

Chng trnh chnh thc hin khi to Timer1 nh thi m 100ms (xem li bi 6-2 v 6-3).
Gn gi tr GIAY bng 0, bin m trn BDT bng 0, cho php Timer1 ngt khi trn cn c gi l
bin m ngt v mi ln trn th pht sinh ngt.
Vng lp while thc hin kim tra xem nu bin m trn nh hn 10 th tin hnh gi hm hin
th, thi gian thc hin chng trnh con hin th ln hn 2ms v nh hn nhiu so vi thi gian nh
thi 100ms ca Timer.
Khi bin m trn BDT bng 10 hoc ln hn 10 th tng ng 1 giy nn reset li bin m
trn, kim tra v tng gi tr ca giy.
bi ny th chng trnh lun thc hin cng vic thng xuyn l qut 2 led hin th, trong
khi Timer1 vn m: c 2 hot ng song song cho n khi Timer trn th ngng chng trnh
chnh i thc hin chng trnh con phc v ngt l tng gi tr bin m trn v khi to li gi tr
bt u chu k mi cho Timer, sau khi lm xong th tr li chng trnh chnh thc hin tip cng vic
b gin on lc ngt.
Trong chng trnh ny mch m thi gian chnh xc v timer m chnh xc v khi ngt xy ra
th ch thc hin hin 2 lnh c nh nn thi gian lun l hng s.
Chng 8. Ngat.
151
Vi x ly
Nguyen nh Phu
Bi tp 8-1:
Hy v mch, vit lu v chng trnh mch m pht giy hin th trn 4 led 7
on kt ni theo phng php qut.
Bi tp 8-2:
Hy v mch, vit lu v chng trnh mch m gi pht giy hin th trn 6 led 7
on kt ni theo phng php qut.
Bi 8-3:
Chng trnh o nhit dng cm bin LM35, dng ADC ca vi iu khin PIC
16F887 bo ngt sau khi chuyn i xong, hin th kt qu o trn 3 led on kt ni
theo phng php qut, s dng in p tham chiu VDD v VSS.
S mch: ging nh mch trnh by chng 7.
Hnh 8-10: Mch o nhit dng cm bin LM35.
Lu :
BEGIN
NGT ADC
KHI TO ADC CHN KNH,

CHO PHP ADC NGT
TNG BIN M SOLANDO

C KT QU O
CNG DN KT QU O
SOLANDO=0, KQADC=0
RETI
HIN TH NHIT O, RA LNH CHUYN I ADC
SOLANDO = 100
S
X L KT QU O KQADC, GII M
152
Chng 8. Ngat.
Nguyen nh Phu
Hnh 8-11: Lu chuyn i ADC c bo ngt.
Chng trnh:
UNSIGNED INT16 KQADC=0;
UNSIGNED INT SOLANDO, MADONVI, MACHUC, MATRAM;
#INT_AD
void interrupt_ADC()
{
SOLANDO++;
KQADC=KQADC+READ_ADC(ADC_READ_ONLY);
}
VOID GIAIMA()
{
MACHUC = MA7DOAN[KQADC/10 % 10];
}
VOID HIENTHI ()
{
OUTPUT_B(MADONVI);
OUTPUT_LOW(PIN_D0);
DELAY_MS(1);
OUTPUT_B(MACHUC);
OUTPUT_LOW(PIN_D1);
DELAY_MS(1);
OUTPUT_B(MATRAM);
OUTPUT_LOW(PIN_D2);
DELAY_MS(1);
}
VOID MAIN()
{
SET_TRIS_A(0x01);
SET_ADC_CHANNEL(0);
SOLANDO=0;
ENABLE_INTERRUPTS(GLOBAL);
ENABLE_INTERRUPTS(INT_AD);
WHILE(TRUE)
{
IF (SOLANDO<100)
{
HIENTHI();
READ_ADC(ADC_START_ONLY);
}
ELSE
{
SOLANDO=0;
KQADC=KQADC/100;
GIAIMA();
KQADC=0;
}
}
}
Gii thch chng trnh:
Chng 8. Ngat.
153
Vi x ly
Nguyen nh Phu
Chng trnh chnh thc hin khi to ADC (xem li cc ca chng 7). Khi to cho php
ADC ngt.
Vng lp while thc hin kim tra xem nu bin m s ln o nu nh hn 100 th ch thc hin
chng trnh con hin th nhit o ln trc v ra lnh chuyn i ADC. Khi s ln o bng 100 th
tin hnh x l kt qu o, gii m v xo kt qu m v 0 thc hin chu k o trung bnh ln tip
theo.
Lnh READ_ADC(ADC_START_ONLY); c chc nng l ra lnh chuyn i.
Khi ra lnh chuyn i th ch ADC chuyn i xong s bo ngt, chng trnh con phc v
ngt ca ADC s tin hnh tng bin s ln o v cng dn kt qu o.
Lnh READ_ADC(ADC_READ_ONLY); c chc nng l c kt qu chuyn i.
Bi 8-4:
Chng trnh o nhit v m giy. m giy dng timer nh thi bo ngt hin
th giy trn led 7 on qut, o nhit dng cm bin LM35, dng ADC ca vi iu
khin PIC 16F887 bo ngt sau khi chuyn i xong, hin th kt qu o trn 3 led
on kt ni theo phng php qut, s dng in p tham chiu VDD v VSS.
S mch: 2 led hin th giy v 3 led hin th nhit nn tng s led l 5.
Hnh 8-12: o nhit dng cm bin LM35 v m giy.
154
Lu :
Chng 8. Ngat.
Nguyen nh Phu
BEGIN
NGT ADC
KHI TO TIMER, ADC CHN

KNH, CHO PHP ADC, TIMER
NGT
TNG BIN M SOLANDO

C KT QU O
CNG DN KT QU O
SOLANDO=0, KQADC=0, BDT=0
RETI
HIN TH GIY, NHIT O.

RA LNH CHUYN I ADC
NGT TIMER
SOLANDO = 100
KHI TO LI TIMER.
X L GIY
S
X L KT QU O KQADC, GII M
RETI
Hnh 8-13: Lu chuyn i ADC c bo ngt v m giy dng timer bo ngt.
Gii thch lu :
H thng thc hin 2 chc nng m giy v o nhit . C 2 u x dng ngt, bi ny tng
hp ca bi 8-2 v 8-3 cho thy c th mt ng dng c th s dng nhiu ngt.
Khi timer m trn th tin hnh x l ngt ca timer thc hin vic x l giy.
Khi ADC chuyn i xong th tin hnh cng dn kt qu ADC.
Chng trnh:
UNSIGNED INT16 KQADC=0;
UNSIGNED INT GIAY,BDT,SOLANDO, MADONVI, MACHUC, MATRAM;
#int_timer1
{
SET_TIMER1(3036);
BDT++;
IF(BDT>=10)
{
BDT = 0;
IF (GIAY == 59) GIAY = 0;
ELSE
GIAY++;
}
}
#INT_AD
void interrupt_ADC()
{
SOLANDO++;
KQADC=KQADC+READ_ADC(ADC_READ_ONLY);
}
Chng 8. Ngat.
155
Vi x ly
Nguyen nh Phu
VOID GIAIMA()
{
MACHUC = MA7DOAN[KQADC/10 % 10];
}
VOID HIENTHI ()
{
OUTPUT_B(MADONVI);
OUTPUT_LOW(PIN_D0);
DELAY_MS(1);
OUTPUT_B(MACHUC);
OUTPUT_LOW(PIN_D1);
DELAY_MS(1);
OUTPUT_B(MATRAM);
OUTPUT_LOW(PIN_D2);
DELAY_MS(1);
OUTPUT_B(MA7DOAN[GIAY %10]);
DELAY_MS(1);
OUTPUT_B(MA7DOAN[GIAY/10]);
DELAY_MS(1);
OUTPUT_LOW(PIN_D3);
OUTPUT_LOW(PIN_D4);
}
VOID MAIN()
{
SET_TRIS_A(0x01);
SET_ADC_CHANNEL(0);
SOLANDO=0; GIAY = 0; BDT=0;
ENABLE_INTERRUPTS(GLOBAL); ENABLE_INTERRUPTS(INT_AD);
SET_TIMER1(0);
ENABLE_INTERRUPTS(INT_TIMER1);
WHILE(TRUE)
{
IF (SOLANDO<100)
{
HIENTHI();
READ_ADC(ADC_START_ONLY);
}
ELSE
{
SOLANDO=0;
KQADC=KQADC/100;
GIAIMA();
KQADC=0;
}
}
}
Gii thch chng trnh:

Chng trnh chnh thc hin khi to ADC ging nh bi 8-3 v khi to Timer1 ging nh bi
8-2.
Vng lp while thc hin cc lnh ging bi 8-3.
156
Chng 8. Ngat.
Nguyen nh Phu
Chng trnh con hin th c chc nng hin th nhit v giy.

Khi timer m trn th pht sinh ngt v chng trnh phc v ngt thc hin tng bin m trn,
kim tra nu ng 1 giy th tin hnh x l giy.
Phn ADC ging nh gii thch bi 8-3.
Trong chng trnh phc v ngt khng phi l hng s c nh v cc lnh kim tra bin m
trn s c 2 trng hp: khng tho th thot thi gian thc hin ngn hn, khi tho iu kin th
thc hin nhiu lnh hn v thi gian di hn, hin tng ny trong 1 s chng trnh s gy ra sai s
nhng bi ny do timer m c lp v bo ngt nn khng gy nh hng v ta khi to li timer
ngay t lc bt u chng trnh phc v ngt nn timer s t ng m chu k tip theo v khng ph
thuc vo cc lnh cn li ca chng trnh con phc v ngt.
Bi tp 8-3:
Hy v mch, vit lu v chng trnh mch m gi pht giy hin th trn 6 led 7
on kt ni theo phng php qut v o nhit hin th trn 3 led 7 on. C 2 u
dng ngt.
Bi tp 8-4:
Ging bi 8-3 nhng ADC khng dng ngt.
Bi tp 8-5:
Mt vi iu khin PIC16F887 giao tip vi 3 led 7 on loi anode chung, 2 cm bin

nhit LM35 ni vi knh AN0, AN1.
Hy vit lu v chng trnh chuyn i nhit dng ngt ca ADC bit qu
trnh chuyn i xong, mi knh chuyn i trong thi gian 5 giy, dng timer1 m
thi gian v bo ngt chuyn knh.
Bi tp 8-6:
Mt vi iu khin PIC16F887 giao tip vi 4 led 7 on loi anode chung, 1 led hin
th s th t knh, 3 led cn li hin th nhit , 4 cm bin nhit LM35 ni vi 4
knh t AN0 n AN3, c 3 nt nhn: 1 nt chn ch t ng hay bng tay, 2 nt
cn li l UP v DW, nhn UP l tng ln chn knh ADC cao hn, DW th gim.
Hy vit lu v chng trnh chuyn i nhit ch t ng dng ngt ca
ADC bit qu trnh chuyn i xong, mi knh chuyn i trong thi gian 5 giy,
dng timer1 m thi gian v bo ngt chuyn knh.
ch bng tay th chuyn knh khi nhn UP hoc DW.
VI. CU HI N TP TRC NGHIM

1.
CU HI N TP
Cu 8-1:
Hy cho bit tn cc thanh ghi lin quan n ngt ca vi iu khin PIC16F887.
Cu 8-2:
Hy cho bit chc nng cc bit trong cc thanh ghi ngt ca vi iu khin PIC16F887.
Cu 8-3:
Hy cho bit vector a ch ngt ca vi iu khin PIC16F887.
Cu 8-4:
Hy cho bit cch x l u tin ngt ca vi iu khin PIC16F887.
2.
CU HI M RNG
Cu 8-5:
Hy so snh ngt ca vi iu khin AT89S52 vi PIC16F887.
Cu 8-6:
Hy so snh ngt ca vi iu khin PIC18F4550 vi PIC16F887.
3.
CU HI TRC NGHIM
Cu 8-1:
Vi iu khin PIC 16F887 c my ngun ngt:
(a) 17
Cu 8-2:
(b) 14
(c) 15
(d) 16
Vi iu khin PIC 16F887 c my thanh ghi lin quan n ngt:
Chng 8. Ngat.
157
Vi x ly
(a) 3
Cu 8-3:
(b) 4
(b) 4
(d) 6
(c) 5
(d) 6
Ngt no ca PIC 16F887 c xem l ngt trong:
(a) Timer0
Cu 8-5:
(c) 5
Thanh ghi OPTION_REG cha my ngun ngt:
(a) 3
Cu 8-4:
Nguyen nh Phu
(b) Timer1
(c) Timer2
(d) ADC
Ngt no ca PIC 16F887 c xem l ngt trong:
(a) RCIE
(b) Timer1
(c) Timer2
(d) INT
Cu 8-16: Bit no ca PIC 16F887 l bit cho php ngt ngoi vi:
(a) PEIE
Cu 8-7:
(d) ADIE
(b) Timer0
(c) INT
(d) Khng c
Bit no ca PIC 16F887 l bit cho php/cm ngt ton b:
(a) PEIE
Cu 8-9:
(c) T0IE
Ngt no ca PIC 16F887 c mc u tin cao nht:
(a) ADC
Cu 8-8:
(b) GIE
(b) GIE
(c) T0IE
(d) ADIE
Mch in x l ngt ca PIC16F887 gm cc cng:
(a) AND, NOR
(b) AND
(c) AND, OR
(d) AND, OR, NOT
Cu 8-10: Vector a ngt ca PIC16F887 l:

(a) 0000H
(b) 0003H
(c) 000BH
(d) 0004H
Cu 8-11: Ngt ngoi th 1 ca AT89S52 c s th t trong lp trnh C l:

(a) Th 0
(b) Th 1
(c) Th 2
(d) Th 3
Cu 8-12: Ngt truyn d liu ca AT89S52 c s th t trong lp trnh C l:

(a) Th 5
158
(b) Th 6
(c) Th 4
(d) Th 3
Chng 8. Ngat.
Chng 9
GII THIU
TNG QUAN V CC KIU TRUYN D LIU
TRUYN D LIU NI TIP NG B V KHNG NG B
TRUYN D LIU CA VI IU KHIN PIC 16F887
CC LNH TRUYN D LIU EUSART
TRUYN D LIU EUSART

CC THANH GHI PHC V CHO KHI ESUART CA PIC16F887
o Thanh ghi iu khin v trng thi ca khi pht TXSTA
o Thanh ghi iu khin v trng thi ca khi nhn RCSTA
o Thanh ghi iu khin tc truyn - BAUDCTL
LNH SETUP_UART(BAUD,STREAM)
LNH PUTS(STRING)
LNH VALUE = GETC(), VALUE = FGETC(STREAM), VALUE = GETCH()
LNH VALUE = KBHIT()
NG DNG TRUYN D LIU EUSART

CU HI N TP
CU HI M RNG
CU HI TRC NGHIM
Nguyen nh Phu
I. GII THIU
Truyn d liu ni tip c nhiu tin ch trong iu khin nn hu ht cc vi iu khin u tch
hp, chng ny chng ta s kho st nguyn l hot ng truyn d liu ng b v khng ng b,
cch vit chng trnh truyn d liu cho cc ng dng.
Sau khi kt thc chng ny bn c th s dng c truyn d liu ni tip ca cc vi iu
khin.
II. TNG QUAN V CC KIU TRUYN D LIU

C nhiu kiu truyn d liu ph bin tch hp trong cc h vi iu khin bao gm:
Truyn d liu ni tip ng b v bt ng b (UART synchronous asynchronous

receiver and transmitter).
Truyn d liu gia cc vi iu khin vi cc thit b ngoi vi (SPI serial peripheral

interface).
Truyn d liu 2 dy (I2C: inter-integrated circuit).
kiu truyn ni tip ng b th c 1 ng d liu v 1 ng xung clock, thit b no cp

xung clock th thit b ng vai tr l ch, thit b nhn xung clock ng vai tr l t, tc truyn d
liu ph thuc vo tn s xung clock.
kiu truyn ni tip bt ng b th c 1 ng pht d liu v 1 ng nhn d liu, khng
cn tn hiu xung clock nn gi l bt ng b. truyn c d liu th c bn pht v bn nhn
phi t to xung clock c cng tn s v thng gi l tc truyn d liu (baud), v d 2400baud,
4800baud, , 2400baud c ngha l truyn 2400 bit trn 1 giy.
Hai kiu truyn SPI v I2C s c trnh by chng tip theo.
III. TRUYN D LIU NI TIP NG B V KHNG NG B

Truyn d liu ng b gm cc ng truyn d liu (DT) v tn hiu xung clock (CK) chc
nng ca CK dng dch chuyn d liu, mi 1 xung ck l 1 bit d liu c truyn i.
Trong h thng truyn d liu ng b, h thng no cung cp xung CK th ng vai tr l
master (ch) nhng h thng cn li nhn xung ck ng vai tr l slave (t).
Tc truyn d liu chnh l tc ca xung ck chnh l tn s xung ck.
V d tn s xung ck l 1MHz th tc truyn d liu l 1MBPS 1M baud.
TD
TD
CK
CK
GND
GND
HT1
MASTER
HT2
SLAVE
Hnh 9-1: H thng truyn ng b.
TxD
RxD
RxD
TxD
CK
CK
GND
HT1
GND
HT2
Hnh 9-2: H thng truyn bt ng b.
Truyn d liu khng ng b ging nh h thng truyn d liu ng b nhng khng c xung
CK. Khng cn phn bit ch v t cc h thng l ngang cp.
160
Chng 9. Truyen d lieu uart.
Nguyen nh Phu
Mi 1 xung ck l 1 bit d liu c truyn i by gi khng cn xung Ck th lm sao

truyn d liu?
truyn d liu th mi h thng phi c 1 mch dao ng to xung CK hai h thng s c 2
mch dao ng c lp nhng phi cng tn s hay cng tc .
IV. TRUYN D LIU CA VI IU KHIN PIC 16F887

TRUYN D LIU EUSART
1.
Vi iu khin PIC16F887 c khi truyn d liu ng b, bt ng b a nng ci tin. Khi

truyn d liu ni tip a nng bao gm b pht xung clock to tc truyn, cc thanh ghi dch v b
m d liu rt cn thit thc hin truyn hoc nhn d liu ni tip mt cch c lp. Khi
EUSART cng c th xem l giao tip truyn d liu ni tip SCI (Serial Communication Interface),
c th nh cu hnh cho truyn d liu bt ng b song cng hoc ng b bn song cng.
Truyn d liu song cng c s dng truyn d liu gia cc h thng ngoi vi nh thit b
u cui CRT v my tnh.
Truyn d liu ng b bn song cng c s dng truyn d liu gia cc h thng ngoi
vi nh cc b ADC, DAC, b nh ni tip Eeprom hoc cc b vi iu khin. Cc thit b ny thng
khng c ngun xung clock bn trong to tc baud nn cn phi s dng ngun xung clock t
bn ngoi.
Khi truyn d liu ca PIC16F887 c kh nng:
Hot ng truyn v d liu song cng bt ng b.
B m nhn cha c 2 k t.
B m pht cha 1 k t.
C th lp trnh chiu di d liu 8 bit hoc 9 bit.
C khi pht hin a ch 9 bit
C khi pht hin b m nhn b trn
C khi pht hin li khung ca k t nhn v.
C th hot ng ch ch kiu truyn d liu ng b bn song cng.
C th hot ng ch t kiu truyn d liu ng b bn song cng.
C th lp trnh chn cc cho xung clock ch truyn ng b.
Khi EUSART c s dng cho cc cu trc m rng theo sau, thch hp cho h thng bus
mng kt ni cc b (LIN: Local Interconnect Network):
2.
T ng pht hin v thit lp tc baud.
C khi nh thc PIC khi ch ng.
Pht k t ngng 13 bit.
CC THANH GHI PHC V CHO KHI ESUART CA PIC16F887

Hot ng ca khi ESUART c iu khin thng qua 3 thanh ghi nh sau:
Thanh ghi iu khin v trng thi ca khi pht (TXSTA transmit Status and Control).
Thanh ghi iu khin v trng thi ca khi nhn (RCSTA transmit Status and
Control).
Thanh ghi iu khin tc baud (BAUDCTL Baud Rate Control)
a.
Thanh ghi iu khin v trng thi ca khi pht TXSTA
161
Nguyen nh Phu
R/W(0)
CSRS
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R(1)
R/W(0)
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Hnh 9-3: Thanh ghi TXSTA.

Bng 9-1: Tm tt chc nng cc bit trong thanh ghi TXSTA:
Bit
TXSTA.7
K hiu
CSRS
TXSTA.6
TX9
TXSTA.5
TXEN
TXSTA.4
SYNC
TXSTA.3
SENDB
TXSTA.2
BRGH
TXSTA.1
TRMT
TXSTA.0
TX9D

Clock Source Select bit:
ch bt ng b th khng c tc dng.
ch bt ng b th c chc nng:
CSRS = 1: Hot ng ch ch - pht xung clock.
CSRS = 0: Hot ng ch t - nhn xung clock.
9 bit Transmit Enable bit.
TX9 = 1: th truyn d liu 9 bit.
TX9 = 0: th truyn d liu 8 bit.
Transmit Enable bit:
TXEN = 1: cho php pht d liu.
TXEN = 0: cm pht d liu.
EUSART mode select bit:
SYNC = 1: Cho php truyn ng b.
SYNC = 0: Cho php truyn bt ng b.
Send Break Character bit
ch khng ng b:
SENDB = 1: gi ngt ng b cho truyn d liu tip theo
SENDB = 0: bo hiu truyn ngt ng b hon tt.
ch ng b: khng c tc dng.
High Baud Rate Select bit:
BRGH=1: ch tc cao.
BRGH=0: ch tc thp.
Bit xc nh trng thi ca thanh ghi TSR.
TRMT xung mc 0 khi ang truyn d liu.
TRMT ln 1 khi truyn xong.
Bit lu d liu pht th 9.
S khi ca khi pht nh hnh sau:

Thit lp truyn d liu bt ng b
162
Thit lp gi tr cho cp thanh ghi SPBRGH v SPBRG v BRGH v bit BRG16 c

tc baud mong mun.
Cho php truyn d liu bt ng b bng cch xa bit SYNC lm bit SPEN ln 1.
Nu truyn d liu 9 bit th thit lp bit cho php TX9 ln 1.
Lm bit TXEN ln 1 cho php truyn d liu.
Nu mun s dng ngt th cho bit TXIE ln 1, cho php ngt ngoi vi v cho php ngt
ton cc.
Nu truyn d liu 9 bit th phi gn gi tr bit th 9 cho bit TX9D
Tin hnh np gi tr cn truyn vo thanh ghi TXREG, khi qu trnh truyn d liu s
bt u.
Nguyen nh Phu
Hnh 9-4: S khi ca khi pht d liu ca PIC16F887.

Dng sng truyn d liu bt ng b nh hnh sau:
Hnh 9-5: Dng sng truyn d liu.

Gii thch dng sng:
Dng sng tn hiu th hai l BRG: l tn hiu to xung clock dch d liu c pht lin tc.
Dng sng tn hiu th nht: l khi thc hin lnh ghi d liu cn truyn byte th nht vo thanh
ghi TXREG.
Dng sng th t cho bit trng thi ca c bo ngt TXIF: tn hiu t 1 xung 0 ri ln 1 tr li
cho bit trng thi thanh ghi b m cn rng, thi gian xung mc 0 ch tn ti 1 chu k.
Dng sng th nm cho bit trng thi ca bit TRMT: tn hiu t 1 xung 0 cho bit qu trnh
dch d liu bt u v tr li mc 0 khi dch xong d liu.
Dng sng th ba l ng xut d liu ni tip ra ngoi: bit u tin c pht l bit Start, tip
theo l bit d liu th 0, 1, , n bit d liu cui cng l bit th 7 nu truyn 8 bit, l bit th 8 nu
truyn 9 bit, bit cui cng l bit Stop.
Dng truyn th 2 nh hnh sau, kiu ny th truyn 2 byte:
163
Nguyen nh Phu
Hnh 9-6: Dng sng truyn 2 byte d liu.

Gii thch dng sng:
Dng sng tn hiu th nht: l khi thc hin lnh ghi d liu cn truyn byte th nht vo thanh
ghi TXREG, sau thc hin tip byte th 2. B m c th cha 2 byte truyn i.
Dng sng th t cho bit trng thi ca c bo ngt TXIF: tn hiu t 1 xung 0 ri ln 1 tr li
cho bit trng thi thanh ghi b m cn rng 1 byte, sau nhn tip byte th 2 th tn hiu ny xung
li mc 0 v lun mc 0 v b m y. Sau khi truyn xong 1 byte th b m rng nn tn hiu ny
ln 1 tr li, ta c th ghi d liu pht tip.
Dng sng th ba l ng xut d liu ni tip ra ngoi: s pht ln lt tng byte.
b.
Thanh ghi iu khin v trng thi ca khi nhn RCSTA
R/W(0)
SPEN
R/W(0)
R/W(0)
R/W(0)
R/W(0)
R(0)
R(0)
R(x)
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D

Bng 9-2: Tm tt chc nng cc bit trong thanh ghi RCSTA:
Bit
RCSTA.7
K hiu
SPEN
RCSTA.6
RX9
RCSTA.5
SREN
RCSTA.4
CREN
164

Serial Port Enable bit:
SPEN = 1: cho php port ni tip (cu hnh cc chn RX/TD v TX/CK l cc
chn cho truyn d liu ni tip).
SPEN = 0: th cm.
9 bit Receive Enable bit.
RX9 = 1: th cho php nhn d liu 9 bit.
RX9 = 0: th cho php nhn d liu 8 bit.
Single Receive Enable bit:
ch khng ng b: khng c tc dng.
ch ng b - ch
SREN = 1: cho php nhn n.
SREN = 0: cm nhn n. Bit SREN b xa sau khi qu trnh nhn hon tt.
ch ng b - t: khng c tc dng.
Continuous Receive Enable bit:
ch khng ng b:
CREN = 1: Cho php nhn.
CREN = 0: Cm nhn.
ch ng b:
CREN = 1: Cho php nhn lin tc cho n khi bit CREN b xa.
CREN = 0: Cm nhn lin tc.
Nguyen nh Phu
RCSTA.3
ADDEN
RCSTA.2
FERR
RCSTA.1
OERR
RCSTA.0
RX9D
Address Detect Enable bit

ch khng ng b 9 bit:
ADDEN = 1: Cho php pht hin a ch, cho php ngt v np b m nhn
khi bit RSR<8> ln 1.
ADDEN = 0: cm b pht hin a ch, tt c cc byte c nhn v bit th 9
c th dng lm bit kim tra chn l.
ch khng ng b 8 bit: khng c tc dng.
Framing Error bit:
FERR =1: xy ra li khung d liu.
FERR =0: khng c li khung xy ra.
Overrun Error bit
OERR = 1: xy ra li trn.
OERR = 0: khng xy ra li trn.
Ninth bit of Receive Data.
Bit ny dng lu d liu nhn v ca bit th 9 hoc c th l bit kim tra
chn l.
Khi nhn d liu EUASRT

S khi nhn ca khi EUASRT nh hnh 9-6.
D liu nhn vo chn RX/DT v iu khin khi khi phc d liu. Khi khi phc d liu l
khi dch tc cao hot ng gp 16 ln tc baud, trong khi thanh ghi nhn d liu (RSR:
Receive Shift Register) hot ng dch d liu cng vi tc baud.
Khi tt c 8 bit hoc 9 bit d liu c dch vo th ngay lp tc s c truyn cho b m cha
c 2 k t dng FIFO, nu c thm mt k t na m phn mm cha c 2 byte nhn th s pht
sinh li trn. Phn mm khng th truy xut b m FIFO v thanh ghi RSR m ch c php truy
xut thanh ghi RCREG.
Khi to qu trnh nhn d liu:

tc baud mong mun.
Nu nhn d liu 9 bit th thit lp bit cho php RX9 ln 1.
Lm bit CREN ln 1 cho php nhn d liu.
Nu mun s dng ngt th cho bit RCIE ln 1, cho php ngt ngoi vi v cho php ngt
ton cc.
C bo ngt RCIF s ln 1 khi mt k t chuyn t RSR sang b m, ngt s pht sinh

nu c php.
c thanh ghi trng thi nhn RCSTA kim tra cc c bo li.
Nhn d liu 8 bit t thanh ghi RCREG.
Nu c li trn xy ra th xa bit cho php nhn CREN
Khi to qu trnh nhn d liu ch pht hin 9 bit a ch: ch ny thng c dng
trong h thng truyn theo chun RS-485.

tc baud mong mun.
Nu mun s dng ngt th cho bit RCIE ln 1, cho php ngt ngoi vi v cho php ngt
ton cc.
165
Nguyen nh Phu
Hnh 9-8: S khi ca khi nhn d liu ca PIC16F887.
Nu nhn d liu 9 bit th thit lp bit cho php RX9 ln 1.
Cho php pht hin a ch 9 bit bng cch cho bit ADDEN ln 1.
Lm bit CREN ln 1 cho php nhn d liu.
C bo ngt RCIF s ln 1 khi mt k t chuyn t RSR sang b m, ngt s pht sinh

nu c php.
c thanh ghi trng thi nhn RCSTA kim tra cc c bo li. Bit th 9 lun l 1.
Nhn d liu 8 bit t thanh ghi RCREG, phn mm s tin hnh kim tra a ch ca thit
b.
Nu c li trn xy ra th xa bit cho php nhn CREN.
Nu ng a ch ca thit b th tin hnh xa bit ADDEN cho php nhn d liu vo

b m v pht sinh ngt.
Dng sng nhn d liu nh hnh 9-7:
Hnh 9-9: Dng sng nhn d liu.

Dng sng tn hiu th nht: l d liu nhn v chn RX/DT, c 3 k t c nhn lin tc.
Dng sng tn hiu th hai: cho bit sau khi nhn xong 1 k t (nhn xong bit stop) th np lu
vo thanh ghi b m.
166
Nguyen nh Phu
Dng sng tn hiu th ba: cho bit tn hiu RCIDL xung mc 0 khi pht hin bit start v ln 1
khi pht hin bit stop.
Dng sng tn hiu th nm: cho bit c nhn RCIF ln mc 1 khi nhn c 1 k t v xung
mc 0 khi tin hnh c xong cc k t nhn.
Dng sng tn hiu th su: cho bit bit bo li trn OERR ln mc 1 khi nhn ti 3 k t.
Dng sng tn hiu th by: cho bit khi xa bit CREN th xa lun bit bo li trn OERR.
Dng sng tn hiu th t: cho bit tin hnh c 2 byte d liu ( mt 1 byte), khi c xong th
xa lun c bo ngt.
c.
Thanh ghi iu khin tc truyn - BAUDCTL
T chc ca thanh ghi nh hnh 9-8:
R(0)
ABDOVF
R(1)
RCIDL
R/W(0)
R/W(0)
SCKP
BRG16
R/W(0)
R/W(0)
WUE
ABDEN

Bng 9-3: Tm tt chc nng cc bit trong thanh ghi BAUDCTL:
Bit
BAUDCTL.7
K hiu
ABDOVF
BAUDCTL.6
RCIDL
BAUDCTL.4
SCKP
BAUDCTL.3
BRG16
BAUDCTL.1
WUE
BAUDCTL.0
ABDEN

Auto Baud detect Overflow bit: bit t ng pht hin trn tc baud
ch khng ng b:
ABDOVF = 1: cho bit timer to tc baud t ng b trn.
ABDOVF = 1: cho bit timer to tc baud t ng khng b trn.
Receive Idle Flag bit: bit c ngng nhn
ch khng ng b:
RCIDL = 1: cho bit b nhn ang ngng ln 1 khi pht hin bit stop.
RCIDL = 0: cho bit bt u nhn bit start cho n bit d liu cui cng.
Synchronous Clock Polarity bit:
ch khng ng b:
SCKP = 1: pht d liu o n chn TX/CK.
SCKP = 0: pht d liu khng o n chn TX/CK.
ch ng b:
SCKP = 1: d liu c dch khi c cnh ln ca xung clock.
SCKP = 0: d liu c dch khi c cnh xung ca xung clock.
16 bit Baud Rate generator bit
BRG16 = 1: s dng b to tc baud 16 bit.
BRG16 = 0: s dng b to tc baud 8 bit.
Wake up Enable bit: bit cho php nh thc CPU
ch khng ng b:
WUE = 1: cho php b nhn ch cho n khi c xung cnh xung. S
khng c k t no c nhn nu bit RCIF thit lp mc 1. WUE s
t ng xa sau khi bit RCIF ln 1.
WUE = 0: B nhn hot ng bnh thng.
ch ng b: khng c chc nng.
Auto-Baud Detect Enable bit: bit cho php pht hin tc baud t
ng.
ABDEN = 1: cho php hot ng tc baud t ng.
ABDEN = 0: khng cho php hot ng tc baud t ng
167
Nguyen nh Phu
B pht tc baud (Baud Rate Generator) l timer 8 bit hoc 16 bit to tc cho hot ng
truyn d liu ESUART ng b v bt ng b.
Mc nhin th khi to tc baud BRG hot ng ch 8 bit, nu cho bit BRG16 bng 1 th
hot ng ch 16 bit.
Cp thanh ghi SPBRGH v SPBRG xc nh chu k to tc baud ca timer.
Trong ch truyn ng b th b nhn chu k tc baud c xc nh bi c 2 bit BRGH
trong thanh ghi TXSTA v bit BRG16 trong thanh ghi BAUDCTL.
Trong ch truyn bt ng b th b nhn chu k tc baud ch c xc nh bi bit
BRGH.
Bng 9-4: Tm tt cc cng thc tnh tc baud:
ng vi tng trng thi ca 3 bit SYNC, BRG16 v BRGH m c cc cng thc tnh tc
baud tng ng. Trong cng thc tnh tc baud th n l gi tr ca cp thanh ghi SPBRGH v
SPBRG.
V d 9-1:
Hy tnh gi tr n ca cp thanh ghi tc truyn l 9600BAUD, s dng thch anh

c tn s 16MHz, hot ng bt ng b, b pht tc BRG 8 bit.
Cng thc tnh tc baud: TDTDL TDBAUD
FOSC
FOSC
64(n 1) 64([SPBGRH : SPBRG ] 1)
FOSC
16000000
1
1 25,041
64 TDBAUD
64 9600
Gi tr np cho cp thanh ghi l 25, khi tc thc l:
FOSC
16000000
TDBAUDTINH
9615
64([SPBGRH : SPBRG ] 1) 64(25 1)
Tnh gi tr ca cp thanh ghi: SPBGRH : SPBRG
Sai s so vi tc 9600 l: SAISO
TDBAUDTINH TDBAUD 9615 9600
0,16%
TDBAUD
9600
CC LNH TRUYN D LIU EUSART CA PIC16F887
V.
Cc lnh ca ngn ng lp trnh C lin quan n ngt bao gm:

1.
LNH SETUP_UART(BAUD, STREAM)
C php:
setup_uart(baud, stream), setup_uart(baud), set_uart_speed(baud,[stream])
Thng s:
baud, stream c th l 1 hoc 2 hng s: hng s th nht l tc , hng s th 2 l tn

ca cng giao tip nu h thng c nhiu cng giao tip EUART phn bit. Nu ch
c 1 th khng cn thng s th 2.
Chc nng:
thit lp tc baud cho EUART.

V d 9-2:
168
thit lp tc 9600 baud: setup_uart(9600);

Nguyen nh Phu
2.
LNH PUTS(STRING)
C php:
puts(string)
Thng s:
string l chui k t gi i.
Chc nng:
c chc nng gi tng k t ra port ni tip, sau khi gi xong chui k t th t ng gi

thm k t RETURN (c m l 13) v k t xung hng (LINE-FEED c m l 10).

V d 9-3:
3.
puts( | HELLO| );
LNH Value = Getc(),Value = Fgetc(Stream), Value = Getch(), Value = Getchar()
C php:
value = getc(),value = fgetc(stream), value = getch(), value = getchar()
Thng s:
stream l tn ca cng EUART nu c.
Chc nng:
c chc nng ch cho n khi c k t gi n th nhn.

V d 9-4:
4.
kitu = getch();
LNH value = KBHIT()
C php:
value = KBHIT()
Thng s:
khng c
Chc nng:
c chc nng tr v kt qu ng nu c k t nhn v tr v kt qu sai nu khng

c k t.

V d 9-5:
if (KBHIT) kitu = getch();
// nu c k t th nhn
VI. NG DNG TRUYN D LIU EUSART CA PIC16F887

Phn ny trnh by cc ng dng truyn d liu n gin ca PIC16F887, qua cc ng dng ny
gip bn bit s dng chc nng truyn d liu ca PIC16F887.
Bi 9-1:
Mt h thng truyn d liu gia my tnh v iu khin PIC 16F887: my tnh s gi

d liu xung vi iu khin, vi iu khin s nhn d liu v gi ra portD ni vi 8
led. My tnh s dng phn mm Terminal.
Tc truyn l 9600 baud.
S mch:
Trong s mch c dng IC2 c tn l MAX232 dng chuyn i tn hiu RS232 ca cng
COM ca my tnh thnh chun TTL tng thch vi vi iu khin.
IC MAX232 c tch hp 2 b chuyn i, trong mch ny ch dng 1 b chuyn i. Cc t in
trong mch theo s tay ca IC do nh ch to cung cp.
Truyn d liu UART thng dng cng giao tip l 9 chn c tn l COM1 (trc dng cng
25 chn nhng b). Ch khi v mch in (PCB) th bn phi chn cng COM 9 chn loi hn vo
mch in v khi chn linh kin bn phi chn ng loi ci. Cc dy cp kt ni s dng u jack c
nn s gip bn kt ni ng.
S dng portD iu khin 8 led n, thch anh s dng l 20Mhz.
169
Nguyen nh Phu
Hnh 9-11: H thng truyn d liu gia my tnh v vi iu khin.
Lu :
BEGIN - PC
BEGIN - VK
KHI TO PHN MM
TERMINAL
CHN CNG, CHN TC
KHI TO TRUYN D LIU,

PORT
C D LIU
GI D LIU
NHN D LIU GI RA PORT0
Hnh 9-12: Lu iu khin truyn d liu.
Chng trnh: cho vi iu khin nhn d liu

#USE
rs232(baud=9600,xmit=pin_c6,rcv=pin_c7)
UNSIGNED INT8 RDATA=0;
VOID MAIN()
{
SET_TRIS_D(0x00); OUTPUT_D(RDATA);
WHILE(TRUE)
{
IF(KBHIT())
{
RDATA = GETCH();
OUTPUT_D(RDATA);
}
}
}
170
Nguyen nh Phu
Gii thch chng trnh:

Hng th 1 l khai bo th vin s dng ging cc bi vit.
Hng th 2 khai bo thit lp truyn d liu gm 3 thng s: chn tc truyn l 9600 baud,
chn port pht d liu l chn th 6 ca portC, chn port nhn d liu l chn th 7 ca portC.
Theo s chn th 2 chn RC6 v RC7 l TD v RD nhng bn cng c th chn chn khc
kt ni cng c, khi bn phi hiu chnh mch in v c chng trnh.
Trong vng lp while th tin hnh kim tra xem nu c d liu th tin hnh nhn v xut ra
portD.
Giao din phn mm Terminal:
Hnh 9-13: Giao din phn mm Terminal gi d liu.

Bn phi xem trong Device Manager xem cng COM ang s dng l COM th bao nhiu
v tin hnh chn cho ng cng COM port, trong ti liu ny my tnh s dng cng COM5.
Tc mc nhin ca phn mm l 9600 baud.
Bn tin hnh chn mc Connect, sau khi kt ni thnh cng th tn ca nt nhn tr thnh
Disconnect.
Hng trng bn di bn nh k t cn gi v nhn enter th phn mm s gi xung my tnh.
Trong hnh th gi k t s 2.
Phn mm Terminal gi k t dng m ASCII. Khi gi s 2 th my tnh s gi m ASCII ca
s 2 l 0x32, d liu iu khin portD s l 00110010.
Mc ch ca bi ny cho cc bn thy cch vit chng trnh truyn d liu kh n gin, cc
bi tip theo s hin th c nhiu k t v r rang hn v d bn gi s 2 trn my tnh th bn c th
nhn thy c s 2 hin th trn LCD bn vi iu khin, bn c th gi 1 chui nhiu k t.
171
Nguyen nh Phu
Bi 9-2:

d liu xung vi iu khin, vi iu khin s nhn d liu v hin th trn LCD. My
tnh s dng phn mm Terminal.
S mch:
Hnh 9-14: H thng truyn d liu gia my tnh v vi iu khin, hin th LCD.
S mch dng LCD hin th c m ASCII tng thch vi my tnh.
Lu :
BEGIN - PC
BEGIN - VK
KHI TO PHN MM
TERMINAL
CHN CNG, CHN TC
KHI TO TRUYN D LIU,

KHI TO PORT, LCD
C D LIU
GI D LIU
NHN D LIU HIN TH TRN LCD
Hnh 9-15: Lu iu khin truyn d liu, hin th trn LCD.
Chng trnh: cho vi iu khin nhn d liu

#INCLUDE <TV_LCD.C>
#USE
UNSIGNED INT8 RDATA=0,I;
const unsigned char HANG1[16]={"GIAO TIEP MAY TINH"};
VOID MAIN()
172
Nguyen nh Phu
{
SET_TRIS_E(0x00);
SET_TRIS_D(0x00);
LCD_SETUP();
FOR (I=0;I<16;I++)
WHILE(TRUE)
{
IF(KBHIT())
{
RDATA = GETCH();
LCD_DATA(RDATA);
}
}
}
Gii thch chng trnh:

V c bn th chng trnh ny ch khc l dng LCD hin th c cc k t t my tnh gi
xung v LCD hin th k t m ASCII.
Do LCD s dng l 16x2 c th hin th c 16 k t nn bn c th gi c 16 k t hin th
trn LCD cng 1 lc, nu gi nhiu hn th cc k t th 17 s khng nhn thy.
bi minh ho ny ta gi d liu t my tnh xung hin th trn LCD nhng cha thc hin
gi d liu t vi iu khin ln my tnh. Bi tip theo ta s minh ho cho c 2 chiu.
Bi 9-3:

d liu xung vi iu khin, vi iu khin s nhn d liu v hin th trn LCD. Khi
nhn 1 phm bt k ca bn phm ma trn 4x4 th m phm hin th trn LCD
hng 1, ng thi gi v my tnh.
My tnh s dng phn mm Terminal.
S mch:
Hnh 9-16: H thng truyn d liu gia my tnh v vi iu khin, c LCD, bn phm.
173
Nguyen nh Phu
S mch them phn giao tip bn phm ma trn 4x4 thc hin chc nng khi nhn phm
no th m phm s hin th trn LCD ng thi gi v my tnh.
Lu :
BEGIN - PC
M PHN MM TERMINAL
CHN CNG, CHN TC
BEGIN - VK
KHI TO TRUYN D
LIU, KHI TO PORT,
LCD
C D LIU
NHN PHM
S
GI D LIU
NHN D LIU HIN TH TRN LCD
X L, HIN TH TRN LCD, GI I
Hnh 9-17: Lu iu khin truyn d liu, c thm LCD v bn phm.
Chng trnh:
#INCLUDE <TV_LCD.C>
#INCLUDE <TV_KEY4X4.C>
#USE
UNSIGNED INT8 RDATA=0, MP, I, TDATA, VITRI_H1=0, VITRI_H2=0;
const unsigned char HANG1[16]={"GIAO TIEP MAY TINH"};
VOID MAIN()
{
SET_TRIS_E(0x00);
SET_TRIS_D(0x00);
SET_TRIS_B(0xF0);
PORT_B_PULLUPS(0XF0);
LCD_SETUP();
FOR (I=0;I<16;I++)
WHILE(TRUE)
{
IF(KBHIT())
{
LCD_COMMAND(ADDR_LINE2+VITRI_H2); DELAY_US(10);
RDATA = GETCH();
LCD_DATA(RDATA);
IF (VITRI_H2==16) VITRI_H2=0;
ELSE
VITRI_H2++;
}
MP= KEY_4X4();
IF (MP!=0XFF)
{
LCD_COMMAND(ADDR_LINE1+VITRI_H1); DELAY_US(10);
IF (MP<10)
TDATA = MP+0X30;
ELSE
TDATA = MP+0X37;
PUTC(TDATA);
LCD_DATA(TDATA);
IF (VITRI_H1==16) VITRI_H1=0;
ELSE
VITRI_H1++;
}
}
}
174
Gii thch chng trnh:

Nguyen nh Phu
Chng trnh chnh thc hin 2 yu cu:

Yu cu th 1: Kim tra nu c d liu t my tnh gi xung th tin hnh hin th hng 2.
Yu cu th 2: Gi chng trnh con qut ma trn phm, nu c phm nhn th tin hnh kim tra
nu cc phm s c m t 0 n 9 th chuyn sang m ASCII bng cch cng them 0x30 ri hin th v
gi v my tnh, nu l cc phm c m t 0x0A n 0x0F th cng thm 0x37 chuyn thnh cc k
t tng ng t A n F hin th trn LCD v gi v my tnh.
Do mi hng ch hin th c 16 k t v 2 hng c lp v a ch nn phi thit lp a ch
trc khi gi d liu, khi gi 1 k t ra LCD th a ch tng ln 1, khi bng 16 th cho a ch v 0
v li u hng.
Bi tp 9-1:
Hy hiu chnh chng trnh bi 9-3 dng ngt nhn d liu.
Bi tp 9-2:
Mt h thng iu khin dng 2 vi iu khin PIC 16F887: vi iu khin A c portD

ni vi 8 led n, vi iu khin B cng c portD ni vi 8 led. D liu 8 bit t vi iu
khin A iu khin portD ng thi gi sang vi iu khin B hin th ra 8 led.
Hai vi iu khin giao tip bt ng b tc 9600 baud.
Hy v s mch, vit lu v chng trnh.
Bi tp 9-3:
Mt h thng iu khin dng 2 vi iu khin PIC16F887: vi iu khin A kt ni vi

2 nt nhn ON v OFF, vi iu khin B ni vi 8 led. Khi nhn ON th vi iu khin A
gi d liu sang vi iu khin B lm 8 led n sng, khi nhn OFF th gi m lm 8
led tt.
Hai vi iu khin giao tip bt ng b tc 9600 baud.
Hy v s mch, vit lu v chng trnh.
VII. CU HI N TP TRC NGHIM

1.
CU HI N TP
Cu 9-1:
Hy cho bit tn cc thanh ghi lin quan n truyn d liu ca vi iu khin PIC16F887.
Cu 9-2:
Hy cho bit chc nng ca cc bit trong thanh ghi TXSTA ca vi iu khin PIC16F887.
Cu 9-3:
Hy cho bit chc nng ca cc bit trong thanh ghi RCSTA ca vi iu khin PIC16F887.
Cu 9-4: Hy cho bit chc nng ca cc bit trong thanh ghi BAUDCTL ca vi iu khin
PIC16F887.
2.
CU HI M RNG
Cu 9-5:
3.
Hy tm hiu truyn d liu ca vi iu khin PIC18F4550 v so snh vi PIC16F887.
CU HI TRC NGHIM
Cu 9-1:
Vi iu khin PIC 16F887 c my ch truyn d liu ESUART:
(a) 2
Cu 9-2:
(b) 3
(b) RxD, CK
(c) TD, CK
(d) TD, TK
Vi iu khin PIC 16F887 khi truyn bt ng b th cc tn hiu c tn l:
(a) RxD, TxD

Cu 9-4:
(d) 5
Vi iu khin PIC 16F887 khi truyn ng b th cc tn hiu c tn l:
(a) RxD, TxD

Cu 9-3:
(c) 4
(b) RxD, CK
(c) TD, CK
(d) TD, TK
Vi iu khin PIC 16F887 th thanh ghi no thit lp tc truyn d liu:
(a) TXSTA
(b) RCSTA
(c) BAUDCTL
(d) TMOD
175
Nguyen nh Phu
Cu 9-5:
Trong cng thc tnh tc ca PIC16F887 th bin FOSC l:
(a) Tn s dao ng ca timer T1

(c) Tn s dao ng ca timer T0
(b) Tn s dao ng ca t thch anh

(d) Tn s dao ng ca ADC
Cu 9-21: Cp thanh ghi no ca PIC16F887 lu gi tr to tc baud:

(a) TXSTA, RCSTA
(c) TSPBGRH, SPBRGL
(b) BAUDCTL, RCSTA

(d) TSPBGRH, SPBRG
Cu 9-22: Vi iu khin PIC 16F887 s dng timer no thit lp tc truyn d liu:

(a) T0
(c) T2
(b) T1
(d) Khng dng timer
Cu 9-23: Bit cho php ngt v c ngt nhn d liu ca PIC 16F887:
(a) RCIF, TXIF
(c) RCIE, RCIF
(b) TXIE, TXIF

(d) TXIE, RCIE
Cu 9-24: Bit cho php ngt v c ngt pht d liu ca PIC 16F887:
(a) RCIF, TXIF
(c) RCIE, RCIF
176
(b) TXIE, TXIF

(d) TXIE, RCIE
Chng 10
GII THIU
KHO ST PWM
CC LNH IU KHIN PWM
NGUYN L IU CH RNG XUNG PWM

CU TRC KHI IU CH RNG XUNG PWM
TNH CHU K XUNG PWM
TNH H S CHU K PWM
LNH NH CU HNH KHI CCP SETUP_CCP(MODE)
LNH THIT LP H S CHU K SET_PMWX_DUTY(VALUE)
LNH NH CU HNH CHO TIMER_2 SETUP_TIMER_2 (MODE,PERIOD,PASTSCALE)
LNH THIT LP GI TR BT U CHO TIMER SET_TIMERx(value)
CC CHNG TRNH NG DNG PWM

CC CU HI N TP TRC NGHIM
Nguyen nh Phu
I. GII THIU
Vi iu khin PIC h 16F887 c 2 b PWM (Pulse Width Modulation) c bn dng iu khin
tc ng c DC.
Phn ny s kho st chi tit khi PWM ca PIC v tp lnh lp trnh C cho PWM, cc ng dng
dng PWM.
II. KHO ST PWM

1.
NGUYN L IU CH RNG XUNG PWM
Nguyn l iu ch rng xung l mch to ra xung vung c chu k l hng s nhng h s cng
tc (cn gi l h s chu k - duty cycle) c th thay i c. S thay i ca h s chu k lm thay i
in p trung bnh hoc dng in trung bnh.
S thay i in p hoc dng trung bnh dng iu khin cc ti nh ng c DC th lm thay
i tc ng c, iu khin bng n th lm thay i cng sng ca bng n,
Cc ng sng iu ch rng xung vi cc h s chu k khc nhau nh hnh 10-1.
0
1
2
3
4
5
6
7
1ms
10ms
Hnh 10-1: Dng sng iu ch rng xung.
Cho chu k 10ms, cp tc 0 th tn hiu bng 0. in p hay dng trung bnh s bng 0, nu tn
hiu ny iu khin n led th n led s tt.
cp tc 1 th tn hiu iu khin mc 1 ch c 1ms, mc 0 l 9ms. Gi s dng to ra l 10
mA khi mc 1, khi dng trung bnh l (10*1)/10 = 1mA. Led sng m vi dng l 1mA.
mA khi mc 1, khi dng trung bnh l (10*2)/10 = 2mA. Led sng hn vi dng l 2mA.
mA khi mc 1, khi dng trung bnh l (10*5)/10 = 5mA.
cp tc 10 th tn hiu iu khin mc 1 l 10ms, mc 0 l 0ms. Gi s dng to ra l 10
mA khi mc 1, khi dng trung bnh l (10*10)/10 = 10mA. Led sng cc i vi dng l 10mA.
Khi thay i h s chu k th ch thay i thi gian xung mc 1, cn chu k th khng i.
178
Chng 10. ieu che o rong xung pwm.
Nguyen nh Phu
Qua phn gii thiu ny cho chng ta bit r khi nim iu ch rng xung, phn tip theo
chng ta s kho st mch in c chc nng to ra dng sng PWM v cc phng trnh tnh ton to
ra chu k tn hiu v h s chu k.
2.
CU TRC KHI IU CH RNG XUNG PWM

PWM ca PIC16F887 c s khi nh hnh 10-2:
Hnh 10-2: S khi ca PWM PIC 16F887.

Khi PWM gm c 2 mch so snh: mch so snh 2 d liu 8 bit nm bn di v mch so snh 2
d liu 10 bit nm bn trn.
Mch so snh 8 bit s so snh gi tr m ca Timer2 vi gi tr ca thanh ghi PR2 (Period
Register), gi tr trong Timer2 tng t gi tr t trc cho n khi bng gi tr ca PR2 th mch so snh
s kch flip flop RS lm ng ra RC2/CCP1 ln mc 1. ng thi np gi tr 10 bit t thanh ghi CCPR1L
sang thanh ghi CCPR1H.
Timer2 b reset v bt u m li cho n khi gi tr ca Timer2 bng gi tr ca CCPR2H th
mch so snh s reset flip flop RS lm ng ra RC2/CCP1 v mc 0.
Qu trnh ny lp li lien tc to ra dng sng PWM lien tc.
Dng sng iu ch PWM nh hnh 10-3:
179
Nguyen nh Phu
Hnh 10-3: Dng sng PWM.

Chu k khng thay i, mun thay i thi gian xung mc 1 th ta thay i h s chu k (Duty
Cycle). Khi h s chu k thay i th in p hay dng trung bnh thay i.
H s chu k cng ln th dng trung bnh cng ln, nu iu khin ng c s lm thay i tc .
Ch 1: xut tn hiu Q ca flip flop ra chn RC2/CCP1 th phi khi to RC2 l port xut.
Ch 2: PIC 16F887 c 2 khi PWM nn cc tn nh CCPx, thanh ghi CCPRxL, CCPRxH vi x
c th l 1 hoc 2.
3.
TNH CHU K XUNG PWM

Chu k PWM ca PIC16F887 c tnh theo cng thc:
PERIODPWM [( PR 2) 1] * 4 * TOSC * PVTMR2
(10-1)
Trong : TOSC l chu k ca t thch anh to dao ng

PVTMR2 (Prescale Value) gi tr chia trc ca timer2
Khi gi tr ca timer 2 (TMR2) bng gi tr ca thanh ghi PR2 th 3 s kin theo sau s xy ra:
4.
Thanh ghi TMR2 b xa

Tn hiu ng ra CCPx ln mc 1, ngoi tr h s chu k bng 0% th CCPx vn mc 0.
H s chu k PWM c chuyn t thanh ghi CCPRxL sang thanh ghi CCPRxH.
TNH H S CHU K XUNG PWM
H s chu k c thit lp bi gi tr lu trong thanh ghi 10 bit gm thanh ghi 8 bit CCPRxL v 2
bit cn li l bit th 4 v th 5 lu trong thanh ghi CCPxCON k hiu l CCPxCON<5:4>.
Gi tr ca h s chu k l 10 bit nn c th thay i t 0 n 1023 to ra 1024 cp gi tr iu
khin.
Gi tr 10 bit th 8 bit c trng s ln lu trong thanh ghi CCPRxL v 2 bit cn li c trng s thp
th CCPxCON<5:4>.
H s chu k ca PIC16F887 c tnh theo cng thc:
DUTY _ CYCLEPWM (CCPRxL : CCPxCON 5 : 4 ) * TOSC * PVTMR2
Ch : k hiu <5:4> cho bit v tr bit th 5 v th 4.
III. CC LNH IU KHIN

1.
LNH NH CU HNH KHI CCP
C php:
Thng s:
setup_ccp1 (mode) or setup_ccp1 (mode, pwm)

mode l hng s. Gi tr ca mode xem trong file thit b, mt vi thng s:
Disable the CCP: CCP_OFF
Set CCP to PWM mode: CCP_PWM Enable Pulse Width Modulator
Chc nng: Khi to khi CCP.
Hiu lc:
Cho tt c cc vi iu khin PIC tch hp phn cng CCP
V d 10-1: setup_ccp1(CCP_PWM); khi to khi CCP1 c chc nng PWM
2.
LNH THIT LP H S CHU K
C php:
Thng s:
180
set_pwm1_duty (value)
value c th l hng s 8 bit hoc 16 bit.
Nguyen nh Phu
Chc nng:
3.
Ghi gi tr 10 bit vo PWM thit lp h s chu k.

Gi tr 10 bit c dng xc nh lng thi gian ca tn hiu PWM mc 1 trong mt
chu k nh sau
LNH SETUP_TIMER_2 - LNH NH CU HNH CHO TIMER_2
C php:
Setup_timer_2(mode, period, postscale)
Thng s:
mode c th l 1 trong cc thng s: T2_DISABLED, T2_DIV_BY_1, T2_DIV_BY_4,

T2_DIV_BY_16
Period l s nguyn c gi tr t 0 n 255 dng xc nh khi no gi tr timer b reset.
postscale l s nguyn c gi tr t 1 n 16 dng xc nh timer trn bao nhiu ln
trc khi pht sinh tn hiu ngt.
Chc nng:
Khi to cho TIMER2.

Mode ch nh kiu b chia ca timer t tn s ca mch dao ng.
Gi tr ca timer c th c hoc ghi dng lnh GET_TIMER2() v SET_TIMER2().
TIMER2 l timer 8 bit.
C hiu lc: Cho tt c cc vi iu khin PIC c timer 2.

4.
LNH SET_TIMERx(value) - LNH THIT LP GI TR BT U CHO TIMER
C php:
set_timerX(value)
; x l 0, 1, 2
Thng s:
value l hng s nguyn 8 hoc 16 bit dng thit lp gi tr mi cho timer.
Chc nng:
thit lp gi tr bt u cho TIMER.

V d 10-2:
SET_TIMER2 (0);
//reset timer2
IV. CC CHNG TRNH NG DNG PWM BI TP

Bi 10-1:
S dng PWM ca PIC 16F887 iu khin 1 n led. Cho tn s t thch anh l

20MHz. Cho chu k PWM l 0,8ms.
Hy tnh ton cc thng s v vit chng trnh iu khin led sng vi cp 1 bng
1 phn 10 sng cc i.
Tnh ton:
Tn s thch anh: fOSC 20MHz nn chu k l:
Chu k PWM:
Ch bit c
TOSC
1
1
0,05S 50ns
FOSC 20MHz
PERIODPWM [( PR 2) 1] * 4 * TOSC * PVTMR2 0,8mS 800,000ns
TOSC 50ns cn cc thng s PR 2, PVTMR2 th cha bit.
Phi chn 1 thng s v tnh thng s cn li: ch PR 2 c gi tr 8 bit t 0 n 255, cn

PVTMR2 c 3 gi tr l chia 1, chia 4 v chia 16.
Chn h s chia ln nht l 16 hay PVTMR2 16
Khi tm gi tr cn li PR 2 :
[( PR 2) 1]
PERIODPWM
800,000ns
250
4 * TOSC * PVTMR2 4 * 50ns *16
181
Nguyen nh Phu
Vy PR 2 249 .
Lnh khi to cho timer2 l: setup_timer_2(T2_DIV_BY_16, 249, 1)
Tnh h s chu k:
H s chu k thay i s lm gi tr trung bnh ca tn hiu thay i, h s chu k nh nht l bng 0
khi tn hiu ra CCPx mc 0, h s chu k tng lm tn hiu xut hin v gi tr trung bnh tng, h s
chu k ln nht bng chu k ca PWM.
Cho h s chu k bng chu k tnh ton gii hn h s chu k:
DUTY _ CYCLEPWM PERIODPWM _ MAX
Ta c cng thc:
DUTY _ CYCLEPWM (CCPRxL : CCPxCON 5 : 4 ) * TOSC * PVTMR2
Ta tm gi tr ln nht ca CCPRxL : CCPxCON 5 : 4 .

Suy ra:
(CCPRxL : CCPxCON 5 : 4 )
DUTY _ CYCLE PWM _ MAX
(CCPRxL : CCPxCON 5 : 4 )
PERIODPWM 800,000ns
1000
TOSC * PVTMR2 50ns *16
TOSC * PVTMR2
PERIODPWM
TOSC * PVTMR2
Gi tr iu khin theo yu cu l 100.

Cp 0 l 0, cp 1 l 100, cp 2 l 200, cp cc i l 1000.
Mch iu khin:
Hnh 10-4: Mch iu khin thay i cng sng ca n dng PWM.

Lu :
182
Nguyen nh Phu
BEGIN
KHI TO PWM, PORT
THIT LP TC CP 1 CHO PWM

IU KHIN LED SNG
END
Hnh 10-5: Lu iu khin n sng dng PWM.

Chng trnh:
UNSIGNED INT16 BIEN_TOC_DO;
VOID MAIN()
{
SET_TRIS_C(0X00);
SETUP_CCP1(CCP_PWM);
SETUP_TIMER_2(T2_DIV_BY_16,249,1);
BIEN_TOC_DO=100;
SET_PWM1_DUTY(BIEN_TOC_DO);
WHILE(TRUE){}
}
Gii thch chng trnh:
Chng trnh chnh thc hin cc yu cu:
Khi to portC l xut, chn ch PWM, khi to Timer2 hot ng m xung ni vi cc thng
s tnh bao gm: chn b chia trc l 16, hng s np cho thanh ghi PR2 l 249, chn b chia sau l 1.
Gn bin tc bng 100, tng ng cp tc l 1. Khi to h s cng tc to xung cp tc
1, thc hin while.
Bi 10-2:
S dng PWM ca PIC 16F887 iu khin 1 n led. Cho tn s t thch anh l

20MHz. Cho chu k PWM l 0,8ms.
Hy tnh ton cc thng s v vit chng trnh iu khin led thay i sng 10 cp
bng 2 nt nhn UP v DW. Khng tnh cp 0.
Hin th cp dng s nh phn cc led n ni vi portD.
Gi tr thay i cho 1 cp l 10.
Tnh ton: ging bi 10-1

Theo tnh ton th thng s thay i h s chu k t 0 n 1000.
Theo yu cu ca bi th gi tr thay i mi cp l 10, khi : cp 0 l 0, cp 1 l 10, cp 2
l 20, cp 10 l 100. Cc gi tr t 100 n 1000 th khng s dng. L do khi chy thc nghim th
t 0 n 100 ta nhn thy cng sng ca led thay i, cn t 110 n 1000 th khng cn quan st
c bng mt thng na.
Mch iu khin:
183
Nguyen nh Phu
Hnh 10-6: Mch thay i cng sng ca n dng PWM v 2 nt nhn.

Lu :
BEGIN
KHI TO PWM, PORT

IU KHIN LED
NHN UP?
KIM TRA GII HN CHO PHP

TNG 1 CP (CC I BNG 10)
NHN DW?
S

GIM 1 CP (CC TIU BNG 0)
Hnh 10-7: Lu iu khin n sng dng PWM v 2 nt nhn.

Chng trnh:
#INCLUDE
#DEFINE
#DEFINE
UNSIGNED
<TV_16F887.C>
UP
PIN_A3
DW
PIN_A4
INT
CAPDO=0;
VOID PHIM_UP ()
{
IF (!INPUT(UP))
{
DELAY_MS (20);
184
Nguyen nh Phu
IF(!INPUT(UP))
{
IF (CAPDO<10)
{
CAPDO++;
DO {}
}
}
SET_PWM1_DUTY(CAPDO*10); OUTPUT_D(CAPDO);
WHILE (!INPUT(UP));
}
}
VOID PHIM_DW ()
{
IF (!INPUT(DW))
{
DELAY_MS (20);
IF(!INPUT(DW))
{
IF (CAPDO>0)
{
CAPDO--;
SET_PWM1_DUTY(CAPDO*10); OUTPUT_D(CAPDO);
DO {}
WHILE (!INPUT(DW));
}
}
}
}
VOID MAIN()
{
SET_TRIS_C(0X00); SET_TRIS_A(0xFF);
SET_TRIS_D(0X00); OUTPUT_D(CAPDO);
SET_PWM1_DUTY(CAPDO*10);
WHILE(TRUE)
{
PHIM_UP();
PHIM_DW();
}
}
Gii thch chng trnh:
Khi to cc port, PWM, Timer2 v tc theo s cp ban u l 0.
Vng lp while thc hin kim tra nhn phm UP v DW.
Chng trnh con phm UP kim tra nu c nhn th tin hnh chng di v kim tra nu cha bng
cp 10 th tng cp ln 1, cp nht tc mi, xut ra port bit cp tc ang thc hin.
Chng trnh con phm DW kim tra nu c nhn th tin hnh chng di v kim tra nu cha bng
cp 0 th gim bt 1 cp , cp nht tc mi, xut ra port bit cp tc ang thc hin.
Bi tp 10-1:
Hy thit k mch v vit chng trnh ging bi 10-2 nhng khng hin th cp tc
led n m hin th 2 led 7 on v c thm 1 nt Stop khi nhn th tt led.
185
Bi 10-3:
Nguyen nh Phu
S dng PWM ca PIC 16F887 iu khin thay i tc ng c DC. Cho tn s t

thch anh l 20MHz. Cho chu k PWM l 0,8ms. ng c dng ngun 24V DC, dng
3A.
Hy tnh ton cc thng s v vit chng trnh iu khin led thay i sng 10 cp
bng 2 nt nhn UP v DW. Nt Stop khi nhn th ng c ngng, khng tnh cp 0.
Hin th cp trn LCD.
Gi tr thay i cho 1 cp l 100.
Tnh ton: ging bi 10-1

Mch iu khin:
Hnh 10-8: Mch iu khin thay i tc ng c dng PWM.

bi yu cu iu khin ng c DC dng ngun 24V DC v dng l 3A th ta phi dng them
mch giao tip cng sut mi dng v p iu khin ng c.
C rt nhiu IC giao tip nhng trong ti liu ny chn 1 IC kh ph bin l L298 c th iu khin
p ln n 48V DC v dng tng ln n 4A theo datasheet.
Bn trong L298 c 2 mch iu khin nn c th iu khin c 2 ng c, mi ng c 2A.
Trong s mch trn th 2 mch iu khin mc song song nn mi c kh nng cp dng 3A
cho ng c.
C 5 tn hiu iu khin nhng do mc song song 2 mch cng sut nn ch cn 3.
Tn hiu cho php ENA: khi mc 0 th khng cho php bt chp 2 tn hiu cn li, mc 1 th cho
php ng c quay tu thuc vo 2 tn hiu cn li.
Bng 10-1: Cc trng thi iu khin ng c DC:
TT ENA CCP1 CCP2 TRNG THI NG C
1
0
X
X
NGNG
2
1
0
0
NGNG
3
1
1
1
NGNG
4
1
1
0
QUAY THUN
5
1
0
1
QUAY NGHCH
C 2 led mc song song vi ng c bo hiu chiu quay ca ng c.
Hai tn hiu CCP1 v CCP2 iu khin 2 tn hiu IN ca IC L298 vi mc ch c th iu khin
ng c quay thun, quay ngc v c th thay i c tc c 2 ch quay thun v ngc.
186
Nguyen nh Phu
Lu :
BEGIN
KHI TO PWM, PORT,
LCD
IU KHIN NG C
HIN TH LCD HNG 1
NHN UP?
NHN DW?
S

TNG 1 CP (CC I BNG 10)
HIN TH TC TRN LCD

GIM 1 CP (CC TIU BNG 0)
HIN TH TC TRN LCD
NHN STOP?
S
CP TC = 0, NG C NGNG
HIN TH TC TRN LCD = 0
Hnh 10-9: Lu iu khin thay i tc ng c dng PWM.

Chng trnh:
#INCLUDE <TV_LCD.C>
#DEFINE UP
PIN_A3
#DEFINE DW
PIN_A4
#DEFINE STOP
PIN_A5
#DEFINE MOTOR_ENA
PIN_C0
const unsigned char HANG1[16]={"DK TOC DO DONGCO"};
SIGNED INT CAPDO=0, I;
VOID HIENTHI_CAP_TOCDO ()
{
LCD_COMMAND(ADDR_LINE2+14); DELAY_US(10);
LCD_DATA(CAPDO/10+0X30);
LCD_DATA(CAPDO%10+0X30);
}
VOID PHIM_UP()
{
IF (!INPUT(UP))
{
DELAY_MS (20);
IF(!INPUT(UP))
{
IF (CAPDO<10)
{
CAPDO++;
HIENTHI_CAP_TOCDO ();
DO {}
WHILE (!INPUT(UP));
}
}
}
}
VOID PHIM_DW()
{
187
Nguyen nh Phu
IF (!INPUT(DW))
{
DELAY_MS (20);
IF(!INPUT(DW))
{
IF (CAPDO>0)
{
CAPDO--;
DO {}
WHILE (!INPUT(DW));
}
}
}
}
VOID PHIM_STOP()
{
IF (!INPUT(STOP))
{
CAPDO=0;
}
}
VOID MAIN()
{
SET_TRIS_C(0X00);
SET_TRIS_D(0X00); SET_TRIS_E(0X00);
LCD_SETUP();
FOR (I=0;I<16;I++)
OUTPUT_HIGH(MOTOR_ENA);
WHILE(TRUE)
{
PHIM_UP();
PHIM_DW();
PHIM_STOP();
}
}
Gii thch chng trnh:
Khi to cc port, PWM, Timer2 v tc theo s cp ban u l 0.
Khi to LCD, hin th thng tin cho hng 1.
Cho php motor sn sng hot ng v hin th cp ban u l 0.
Vng lp while thc hin kim tra nhn phm UP, DW v STOP.
Chng trnh con phm UP kim tra nu c nhn th tin hnh chng di v kim tra nu cha bng
cp 10 th tng cp ln 1, cp nht tc mi, hin th ra LCD cp tc ang thc hin.
188
Nguyen nh Phu
Chng trnh con phm DW kim tra nu c nhn th tin hnh chng di v kim tra nu cha bng
cp 0 th gim bt 1 cp , cp nht tc mi, hin th ra LCD cp tc ang thc hin.
Chng trnh con phm STOP kim tra nu c nhn th tin hnh cho cp tc bng 0, cho ng
c ngng, hin th LCD cp tc bng 0.
Bi tp 10-2:
Hy hiu chnh bi 10-3 sao cho khi nhn nt STOP th ng c ngng ng thi o
chiu ng c.
Khi ng c quay thun th hin th FOR trn LCD 3 k t u hng 2.
Khi ng c quay ngc th hin th REV trn LCD 3 k t u hng 2.
Bi tp 10-3:
Hy hiu chnh bi 10-3 vi 2 nt nhn UP, DW by gi c tn l START, INV.

Khi nhn START th ng c quay tc t ng tng dn tng cp sau mi giy cho
n khi t cp 10. Chiu quay mc nhin ban u l quay thun.
Khi nhn INV th ng c ngng ngay v o chiu quay.
Nt th 3 l STOP ch khi nhn th ng c gim tc cho n khi ngng, mi ln gim 1
cp cho n khi bng 0.
Bi tp 10-4:
Hy hiu chnh bi 10-3 thay v dng 3 nt nhn th dng bn phm ma trn 4x4 ni vi
portB.
Bi tp 10-5:
Hy hiu chnh bi 10-3 thay v dng 3 nt nhn th dng bn phm ma trn 4x4 ni vi
portB.
11 phm s c m t 0x0 n 0xA dng iu khin 11 cp tng ng, khi nhn s 0 th
ng c ngng, khi nhn phm s 1 th ng c chy cp tc 1, khi nhn phm s 2 th
ng c chy cp 5, tng t cho cc phm cn li. Ch chy 1 chiu.
Bi tp 10-6:
Hy thm vo bi tp 10-5 cc yu cu sau:

Khi nhn phm c m l 0x0B th o chiu ng c, hin th FOR v Rev tng ng trn
LCD.
Khi nhn phm c m l 0x0d m ng c ang chy th khng c tc dng, nu ng c
ang ngng th t ng quay theo chiu chn v tng tc cho n khi t cc i, thi
gia tng mi cp l 1 giy.
Khi nhn phm c m l 0x0e m ng c ang ngng th khng c tc dng, nu ng c
ang chy th t ng gim tc cho n khi ngng, thi gia gim mi cp l 1 giy.
Bi tp 10-7:
Hy thit h thng iu khin 2 motor ko 2 bnh xe ca 1 chic xe 3 bnh bng 4 nt

nhn TI, LI, PHI, TRI.
Khi nhn nt TI th xe chy ti, nu tip tc nhn v gi th xe chy tng tc, khi khng
cn nhn th xe ngng. Nu mun chy tip th nhn li.
Khi nhn nt LI th xe chy li, nu tip tc nhn v gi th xe chy li tng tc, khi
khng cn nhn th xe ngng. Nu mun chy tip th nhn li.
189
Nguyen nh Phu
Khi nhn nt PHI th xe va chy ti va quo phi: ng c bn phi chy cp 1,

ng c bn tri chy cp tng dn nu tip tc nhn v gi, s chnh lch ny lm xe
quo phi.
Khi nhn nt TRI th xe va chy ti va quo tri: ng c bn tri chy cp 1,
ng c bn phi chy cp tng dn nu tip tc nhn v gi, s chnh lch ny lm xe
quo tri.
Thit k mch dng 2 PWM ca vi iu khin PIC16F887 dng transistor v relay, mi
PWM iu khin 1 ng c. Relay c chc nng o chiu. PWM c chc nng thay i
tc .
V.
1.
CU HI N TP
Cu 10-1: Hy cho bit tn cc thanh ghi lin quan n khi CCP ca vi iu khin PIC16F887.
Cu 10-2: Hy cho bit ng dng ca PWM trong iu khin ng c.
2.
CU HI M RNG
Cu 10-3: Hy so snh vi iu khin khng tch hp chc nng PWM v c tch hp PWM trong iu
khin thay i tc ng c DC.
3.
190
CU HI TRC NGHIM

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PIC16F887_VXL_00_0_bia.

KHO ST VI IU KHIN MICROCHIP

Cu hnh ca vi iu khin PIC 16F887

CHNG 2. T CHC B NH, THANH GHI

T CHC B NH CA VI IU KHIN PIC 16F887

T chc b nh chng trnh

LNH HP NG CA VI IU KHIN PIC 16F887

CHNG 4. NGN NG LP TRNH C

CC THNH PHN C BN CA NGN NG C

Cc kiu d liu ca bin

TRNH BIN DCH CCS-C

CHNG 5. GIAO TIP LED, LCD, PHM N, MA TRN PHM

CHC NNG CC PORT CA VI IU KHIN

CC PORT CA PIC 16F887

Port A v thanh ghi TrisA

LNH TRUY XUT PORT DNG NGN NG CCS-C

CC NG DNG IU KHIN LED N

CC NG DNG IU KHIN LED 7 ON TRC TIP

VII. CC NG DNG IU KHIN LED 7 ON QUT

VIII. CC NG DNG GIAO TIP VI NT NHN, BN PHM

CC NG DNG IU KHIN LCD

CHNG 6. TIMER - COUNTER

KHO ST TIMER0 CA PIC 16F887

KHO ST TIMER1 CA PIC 16F887

B chia trc v chia sau ca Timer2

CC LNH CA TIMER COUNTER TRONG NGN NG CCS-C

KHO ST TIMER2 CA PIC 16F887

CC NG DNG NH THI DNG TIMER

VII. CC NG DN M XUNG NGOI DNG COUNTER

VIII. CU HI N TP TRC NGHIM

CHNG 7. CHUYN I TNG T SANG S

ADC CA VI IU KHIN PIC 16F887

Kho st adc ca pic 16F887

CC LNH CA ADC TRONG NGN NG CCS-C

Lnh setup_adc (mode)

CC NG DNG ADC CA PIC 16F887

TNG QUAN V NGT

NGT CA VI IU KHIN PIC16F887

Cc ngun ngt ca PIC16F887

CC LNH NGT CA PIC16F887 TRONG NGN NG CCS-C

lnh enable_interrupt (level)

lnh disable_interrupt (level)

CC NG DNG NGT CA PIC 16F887

CHNG 9. TRUYN D LIU UART

TNG QUAN V CC KIU TRUYN D LIU

TRUYN D LIU NI TIP NG B V KHNG NG B

TRUYN D LIU CA VI IU KHIN PIC 16F887

CC LNH TRUYN D LIU EUSART

Truyn d liu EUSART

NG DNG TRUYN D LIU EUSART

VII. CU HI N TP TRC NGHIM

CHNG 10. IU CH RNG XUNG

Nguyn l iu ch rng xung PWM

CC LNH IU KHIN PWM

Lnh nh cu hnh khi ccp setup_ccp(mode)

CC CHNG TRNH NG DNG PWM

Ti liu tham kho.

Hnh 2-1: Kin trc Von Neumann v Harvard.

Hnh 3-1: Cc dng m lnh.

Hnh 5-1: S kt ni port vi i tng iu khin.

Hnh 5-42: Lu m t 00 n 99.

Hnh 6-1: S khi ca timer0 ca PIC16F887.

Hnh 7-1: S khi ca ADC PIC 16F887.