Bahria University

CEN231: Computer Architectur e

Department of Computer Science

Fall Semester 05 (2015)

Class AssignmentList for Section A & B

1 Differentiate between Conventional Computing Techniques and Von Neumann Architecture
5 Points-3rd week

2 Compare the Physical & Technical Differences of SD vs RD RAMS

5 Points-7th week

3 Write a program on C/C++/Java to achieve the following objectives

A user enter values in a Memory Stack that returns its address
The values in the stack is not executed as per shift & rotate
Operations (selection of operations will be given like 1-Left Rotate,
2-Right Rotate, 3-Arithematic Left Shift etc)
Now retrieve the value of the remainder stack using pointers.
10 Points-11th week

Home Assignment List for Section A & B

1 Discuss the advantages of Buses and their response

2 How Interrupts can make an execution more better/more worst
3 Discuss the family of Multicore processors and what are their requirements
BONUS 5 Points
Deadline: End of Semester

1 |P a ge

BU, CS Department
CEN231: Computer Architecture

2/2

Fall Semester 5 (2015)

Practice Question for Section A & B

Problem 1
Consider a system with 4-way set associative cache of 256 KB. The cache line size is 8 words (32 bits per
word). The smallest addressable unit is a byte, and memory addresses are 64 bits long.
a. Show the division of the bits in a memory address and how they are used to access the cache.
Solution:
We are given that the block size is 8 words (32 bytes). Therefore, the number of bytes required to specify the
block offset is log232 = 5 bits. The number of sets is 256 KB / (32 * 4) = 2048 sets. Therefore, the index field
would require 11 bits. The remaining 64 11 5 = 48 bits are used for the tag field.
b. Draw a diagram showing the organization of the cache and, using your answer from part (a), indicate
how physical addresses are related to cache locations.
Solution:
The diagram would look similar to Figures 5.4 and/or 5.5 from H&P. We know that any physical address with
the same index bits will map to the same set in the cache. The tag is used to distinguish between these
physical locations.
c. What memory addresses can map to set 289 of the cache?
Solution:
Memory locations with index bits 00100100001 will map to set 289.
d. What percentage of the cache memory is used for tag bits?
Solution:
For each cache line (block), we have 1 tag entry. The size of the cache line is 32 * 8 = 256 bits. Therefore, the
percentage of cache memory used for tag bits is 48 / (48 + 256) = 15.8%.