Digital Integrated

Circuits

A Design Perspective

The Inverter

Introduction
q

The inverter is the simplest of all digital logic gates

However, building an understanding of its properties and operation is crucial for

the design and analysis of larger/ more complex logic gates.

We will discuss: General properties of an inverter (and logic gates), and inverter
implementation issues in CMOS technology.

General Properties
q
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Small area is a desirable property for a digital logic gate

Larger packing density
Small parasitic capacitances
Shorter interconnects
Smaller chip area, hence higher number of devices per wafer (lower
cost)
Fewer transistors for a logic gate usually results into smaller area.
Hence, minimum possible number of transistors for a given gate is
important.

The CMOS Inverter: A First Glance

V DD

V in

V out
CL

CMOS Inverter - First-Order DC Analysis

V DD

V DD
Rp

V out

V out

Properties
1)
High and low outputs = V DD and Ground.
Voltage swing= V DD. High Noise Margins.
2)
Logic Levels are independent of device sizes
(ratioless logic)
3)
In steady state, a path exists from O/P to VDD
or GND. Thus, low output impedance. Less
sensitive to noise.
4)
Input resistance is extremly high, since MOS
gate draws no dc input current. Steady-state
input current ~ zero. An inverter can
theoretically drive infinite number of gates and
be functionally operational. This degrades the
transient response.
5)
In steady-state, no direct path exists between
supply and ground rails. No static power
(ignoring leakage)

Rn

V in = V DD

V in = 0

VOL = 0
VOH = VDD
VM = f(Rn, Rp)

Voltage Transfer
Characteristic

PMOS Load Lines

I DSp = I DSn
VGSn = Vin ;VGSp = Vin VDD
VDSn = Vout ;VDSp = Vout VDD

IDp

IDn

IDn

Vin=0

Vin=0

V in=1.5

Vin=1.5

V DSp

V DSp

VGSp=-1
VGSp=-2.5

Vin = V DD +VGSp
IDn = - IDp

Vout = V DD +VDSp

Vout

CMOS Inverter Load Characteristics

ID n

PMOS

Vi n = 0

Vin = 2.5

Vin = 0.5

Vin = 2

Vin = 1

Vin = 1.5

Vin = 1.5
Vin = 2
Vi n = 2.5

NMOS

Vi n = 1
Vi n = 1.5

Vin = 1

Vi n = 0.5
Vi n = 0
Vout

For a dc operating point to be valid, the currents through NMOS and PMOS devices must be equal
(intersections) {Vin = 0, 0.5, 1, 1.5, 2, 2.5}
Operating points are located either at the high or low output levels. The Voltage Transfer Characteristics (VTC)
exhibit a very narrow transition zone (high gain during switching transient a small change in the input voltage
results in a large output variation)

CMOS Inverter VTC (VDD=2.5V)

NMOS off
PMOS res

Vout=Vin

2.5

Vout

NMOS sat
PMOS res

1.5

NMOS sat
PMOS sat

0.5

NMOS res
PMOS sat

0.5

1.5

VM = switching
threshold
NMOS res
PMOS off

2.5

Vin

Switching Threshold as a function of Transistor Ratio

Vin=Vout
PMOS and NMOS are saturated since V DS=VGS. Equate current through NMOS and PMOS.
1.8
1.7
1.6

1.4
1.3

V (V)

1.5

1.2
1.1
1
0.9
0.8

10

VM

rVDD
1+ r

10

Wp/Wn

VM=VDD/2 for comparable high and low noise margins. Thus, r=1.

(W / L ) p = (W / L) n (VDSATn k n ) /(VDSATp k p )
'

'

Increasing strength of NMOS (sizing it up), moves V M closer to GND. Vice versa for PMOS case.
Note: When designing CMOS circuits, it is advisable to balance the strengths of the transistors by
making PMOS wider than NMOS, to obtain large noise margins + symmetrical characteristics.

Switching Threshold as a function of Transistor Ratio

Points
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VM is relatively insensitive to variations in the device ratio. Small variations of the

ratio do not disturb the VTC that much. Setting ratio of W p/W n to {3, 2.5, 2} yields
switching thresholds of {1.22V, 1.18V, 1.13V}

VM shifts towards VDD or GND depending on strength of NMOS and PMOS.

Asymmetrical VTC is sometimes desirable in some designs.
Example in Page 187.

Noise Margin - Determining VIH and VIL

In real life applications, output voltage of a gate may not have the nominal value, owing to load, high
switching speed..etc.
Hence, it is desirable to define an acceptable voltage range for logic 1 and logic 0

Vout
VOH

VM

A simplified approach V
in
VOL

VIL

VIH

These expressions make it clear that a high gain in the transition region is very desirable. For infinite gain:
NMH=VDD-VM, NML=VM
Logic gates have the property to restore the proper output logic values despite of non-ideal input
levels.

Inverter Gain
0
-2
-4
-6

gain

-8

NMOS and PMOS are in saturation. Equate

currents. Differentiate and solve for dVout/dVin

-10
-12

The gain is almost purely determined by

technology parameters, especially the
channel-length modulation.

-14
-16
-18
0

0.5

1.5

V (V)
in

2.5

Gain as a function of VDD

2.5

0.2

2
0.15

0.1

out

V out (V)

(V)

1.5

1
0.05

0.5

Gain=-1
0
0

0.5

1.5
V (V)

2.5

0
0

0.05

0.1
V (V)

0.15

0.2

in

in

The gain of the inverter actually increases with a reduction of VDD . At a VDD =0.5V, which is just 100mV
above V T of the transistors. So why cant we operate all digital circuits at low V DD values?
Yes, you get lower power consumption. But the delay of the gate drastically increases.
DC characteristics become very sensitive to variations in device parameters such at V T once V DD and
intrinsic voltages become comparable.
The signal swing is reduced. Although this is good for internal noise (crosstalk), this is bad for external
noise sources that do not scale.

Impact of Process Variations

2.5

A CMOS inverter remains functional under a

wide range of operating conditions. We
showed that variations in device sizes have
minor impact on switching threshold.

Good PMOS
Bad NMOS

1.5

Nominal

Vout(V)

This robust behavior, which ensures

functionality of the gate over a wide range of
conditions, has contributed in a big way to the
popularity of the static CMOS gate.

Good NMOS
Bad PMOS

0.5

0
0

0.5

1.5

Vin (V)

2.5

Propagation Delay

CMOS Inverter: Transient Response

V DD

V DD

tpHL = f(R on.C L)

Rp

= 0.69 R onCL
V out

V out

CL

CL
Rn

V in = 0
(a) Low-to-high

V in = V DD
(b) High-to-low