Digital Electronics

NUMBER SYSTEM
BINARY CODES
BOOLEAN ALGEBRA
K MAPS

D-Flip-flop using MUX

Q- Can we implement the D-Flip-flop using MUX?
Ans: Yes, we can. As we can derive a D FF from D latch by following circuit:

COMBINATIONAL CKT
SEQUENTIAL CIRCUITS
INTRODUCTION
CLOCK
BISTABLE MULTIVIBRATOR
DERIVATION of FLIPFLOP
circuit
RS FLIPFLOP
RS FLIPFLOP(NAND
IMPLEMENTATION)
R'S' FLIPFLOP

So we implement the above circuit to get D ff from MUX as: The following D FF is a
falling edged or negative edged Flip-flop.

Clocking RS LATCH
Other LATCHes
Timing problem in LATCHES
ASYNCHRONUS INPUTS
Parameters of CLOCK
pulse
QUESTIONS(LATCH using
MUX)
EDGE SENSITIVE LATCH
(i.e. FLIPFLOP)
MASTER SLAVE FF
D FF USING MUX
TIMING PARAMETERS OF FF
CHARACTERISTIC
EQUATIONS OF FFs
EXCITATION TABLES OF FF
CONVERSION OF 1 FF TO
OTHER
FF as 1bit MEMORY CELL
REGISTERS
SHIFT REGISTERS
RING COUNTER
JOHNSON COUNTER
QUESTION(Serial Data
transfer)
ASYNCHRONOUS
COUNTERS
RIPPLE COUNTER
COUNTER other than
MOD-2n

Designing COUNTER Using

K-MAPS
QUESTION(MOD 6 counter)
QUESTION(Counter
design)
DOW N COUNTER
QUESTION(Counter
design)
GLITCH
SYNCHRONOUS COUNTER
COMPARISON B/W SYNC. &
ASYNC. COUNTERS
CLOCK SKEW
QUESTION(Maximum
frequency question)
QUESTION(Maximum

And we can implement the rising edge or positive edged flip-flop using negative
level triggered D-LATCH as:

frequency question)
MORE QUESTIONS

TIMING CIRCUITS

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