Wed Mar 18 12:06:04 2015

circuito.vhd
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-- Diseo de circuito usando estilo estructural

-- con generacin paramtrica
library ieee;
use ieee.std_logic_1164.all;
entity fulladder_n is
generic (
N : integer := 32 -- Parmetro
);
port (
A:
in std_logic_vector(N-1
B:
in std_logic_vector(N-1
Cin: in std_logic;
S:
out std_logic_vector(N-1
Cout: out std_logic
);
end entity fulladder_n;

de diseo: nmero de bits E/S

downto 0);
downto 0);
downto 0);

architecture behave of fulladder_n is

-- Declaracin de COMPONENTES
component fulladder is
port (
A:
in std_logic;
B:
in std_logic;
Cin: in std_logic;
S:
out std_logic;
Cout: out std_logic
);
end component fulladder;
-- Declaracin de SEALES
signal carry_internal: std_logic_vector(N downto 0);
begin
-- Declaracin de BUCLE
gen_fulladder: for i in 0 to N-1 generate
-- Declaracin de INSTANCIA de COMPONENTE
inst_fulladder: fulladder
port map (
A
=> A(i),
B
=> B(i),
Cin => carry_internal(i),
Cout => carry_internal(i+1)
);
end generate;
-- Declara entradas y salidas
carry_internal(0) <= Cin;
Cout <= carry_internal(N);
end behave;

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