AIM:- Write a VHDL program to implement 8:1 multiplexer.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if

instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUX8to1 is
PORT (X:IN STD_LOGIC_VECTOR(0 TO 7);
EN : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR (0 TO 2);
Z : OUT STD_LOGIC);

end MUX8to1;

architecture MUX of MUX8to1 is

BEGIN

PROCESS (S,X,EN)
BEGIN
IF EN = '1' THEN
CASE S IS
WHEN "000" => Z <= X(0);
WHEN "001" => Z <= X(1);
WHEN "010" => Z <= X(2);
WHEN "011" => Z <= X(3);
WHEN "100" => Z <= X(4);
WHEN "101" => Z <= X(5);
WHEN "110" => Z <= X(6);
WHEN "111" => Z <= X(7);
WHEN OTHERS => Z <= '0';
END CASE;
ELSE Z<= '0';
END IF;
END PROCESS;

end MUX;

AIM:- Write a VHDL program to implement 8:1 multiplexer.

entity mux is

-- entity declaration

port(i:in bit_vector(0 to 7);

-- declaration of input output port

s: in bit_vector(0 to 2);
y:out bit);
end mux;

-- end of entity

architecture exp3 of mux is

-- architecture declaration

begin

-- architecture body

process(i,s)
begin
case s is
when"000"=>y<=i(0);
when"001"=>y<=i(1);
when"010"=>y<=i(2);
when"011"=>y<=i(3);
when"100"=>y<=i(4);
when"101"=>y<=i(5);
when"110"=>y<=i(6);
when others=>y<=i(7);
end case;
end process;
end exp3;

-- end of architecture

AIM:- Write a VHDL program to implement 8:1 multiplexer

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY MUX8X1 IS
PORT (X:IN STD_LOGIC_VECTOR(0 TO 7);
EN : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR (0 TO 2);
Z : OUT STD_LOGIC);
END MUX8X1;
ARCHITECTURE MUX OF MUX8X1 IS
BEGIN
PROCESS (S)
BEGIN
IF EN = '1' THEN
CASE S IS
WHEN "000" => Z <= X(0);
WHEN "001" => Z <= X(1);
WHEN "010" => Z <= X(2);
WHEN "011" => Z <= X(3);
WHEN "100" => Z <= X(4);
WHEN "101" => Z <= X(5);
WHEN "110" => Z <= X(6);
WHEN "111" => Z <= X(7);
WHEN OTHERS => Z <= '0';
END CASE;
ELSE Z<= '0';
END IF;
END PROCESS;
END MUX;