Finite'state'machines'(FSM)'

in'VHDL'

Finite'State'Machine'
Model'of'behavior'composed'of'a'nite'number'of'states,'input'events,'
transi,ons'between'those'states'(rules'or'condi,ons),'and'ac,ons.'
Eec,ve'method'for'implemen,ng'control'func,onality.'
FSM'design'_'just'a'step'beyond'sequen,al'design:'

HW'implementa,on'requires'a'register'to'store'state'variables,'a'block'of'
combina,onal'logic'which'determines'the'state'transi,on,'and'a'block'of'
combina,onal'logic'that'determines'the'output'of'the'FSM.'

Current'state'is'stored'in'registers'and'updated'synchronous'to'the'clock''
Two'phases:''

calculate'new'state'
new'state'is'sampled'into'a'register'

Two'main'types'
Moore'machine'
Edward'F.'Moore,'1956'

Mealy'machine'
George'H.'Mealy,'1955'

Moore'machine'
Output'signals'

State'

Input'

Outputs'of'Moore'machine'are'a'func,on'of'the'present'state'only'
Output'transi,ons'are'synchronous'to'system'clock'
Propaga,on'delay'through'output'logic'nevertheless'leads'to'
asynchronous'outputs'which'can'lead'to'slower'opera,ng'
frequencies'

Mealy'machine'

Inputs'

Outputs'

State'

Outputs'of'Mealy'machine'are'a'func,on'of'the'present'state'and'all'the'
inputs.'
Outputs'transi,ons'are'asynchronous'to'the'clock'
They'change'immediately'when'the'inputs'change'

=>'A'Mealy'machine'works'one'clock'cycle'in'advance'of'a'Moore'machine'

Design'of'FSM'in'VHDL'
Declara,on'of'states''
'''''''''''''''''''''''''''''''''''''''''''''''''Choose'explanatory'names'using'enumerated'types'

Clocked'process'

'

Mealy3
Moore3

Combina,onal'output'process'

'
Mealy3
Moore3

VHDL'structure'

Declara,on'

Clocked'process'

Combina,onal'
process'

Enumerated'data'type'
It'is'possible'to'dene'your'own'enumerated'data'type'in'VHDL''
This'data'type'allows'a'user'to'specify'the'list'of'legal'values'that'a'
variable'or'signal'of'the'dened'type'may'be'assigned'
Commonly'used'for'state'machines:'
type'state_type''is'(start,'idle,'wai,ng,'run);'
signal'state':'state_type'

4'states'!'2'bit'vector'

Most'synthesis'tools'can'build'logic'from'enumerated'types'

Examples'of'predened'types'
type'std_ulogic''is'('U,'''__'Unini,alized''
''''''''''''''''''''''''''''''''''''X,'''__'Forcing'unknown''
''''''''''''''''''''''''''''''''''''0,'''__'Forcing'
'0'
''''''''''''''''''''''''''''''''''''1,'''__'Forcing'
'1'
''''''''''''''''''''''''''''''''''''Z,'''__'High'impedance'
''''''''''''''''''''''''''''''''''''W,'__'Weak' '
'unknown'
''''''''''''''''''''''''''''''''''''L,'''__'Weak '
'0''
''''''''''''''''''''''''''''''''''''H,''__'Weak '
'1'
'''''''''''''''''''''''''''''''''''''_','__'Dont'care'
'
'
'
');'
'
type'std_logic'is'resolved'std_ulogic;'

type'boolean'is'(false,'true);'
'
type'bit'is'(0,'1);'

std_logic_1164.vhd'

Converted'to'1'and'0'during'synthesis'
standard.vhd'

Design'of'FSM'in'VHDL'
1'process'
2'processes'

Clocked'state'process'
Combina,onal'output'process'

3'processes'

Combina,onal'coding'of'next'state'
Clocked'update'of'present'state'(present'state'<='next'state)'
Combina,onal'output'process'

Example''Moore'(2'processes)'

Moore)3)2)prosesser)

Declara,on'

Moore)3)2)prosesser)

Clocked'process'

Moore)3)2)prosesser)

Clocked'process'

Moore)3)2)prosesser)

Combina,onal'output'process'

Next'state'

Outputs'of'Moore'machine'are'a'func,on'of'the'present'state'only.'
Moore)3)2)prosesser)

Combina,onal'output'process'

Outputs'of'Moore'machine'are'a'func,on'of'the'present'state'only.'
Moore)3)2)prosesser)

Example'_'Moore'(3'processes)'

Moore)3)3)prosesser)

Declarac,on'

Moore)3)3)prosesser)

Decoding'of'next'state'

Next'state'

Moore)3)3)prosesser)

Decoding'of'next'state'

Moore)3)3)prosesser)

Clocked'process'
Update'of'present'state'(current'state)'

Next'state'

Moore)3)3)prosesser)

Clocked'process'
Update'of'present'state'(current'state)'

Moore)3)3)prosesser)

Combina,onal'output'process'

Next'state'

Outputs'of'Moore'machine'are'a'func,on'of'the'present'state'only.'
Moore)3)3)prosesser)

Combina,onal'output'process'

Outputs'of'Moore'machine'are'a'func,on'of'the'present'state'only.'
Moore)3)3)prosesser)

Mealy'

Outputs'of'Mealy'machine'are'a'func,on'of'
the'present'state'and'all'the'inputs.'

Mealy'

Outputs'of'Mealy'machine'are'a'func,on'of'
the'present'state'and'all'the'inputs.'

Declara,on'

Iden6cal)to)Moore)machine)

Clocked'process'

Iden6cal)to)Moore)machine)

Combina,onal'output'process'
Outputs3directly33
dependent3on3
value3of3inputs3

Mealy'

Clk'=' 1 '
Utgang'endres'

Inngang'endres'

Mealy)

Utgang'flger''
bde'inngang'
og'n_,lstand,'
mens'n_,lstand'
skieer'p'klokken'

Mealy'vs'Moore'
Next'state'

Mealy'vs'Moore'