Analog Integrated Circuits and Signal Processing, 19, 163168 (1999)

# 1999 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

A CMOS Four Quadrant Current/Transconductance Multiplier

ALEJANDRO DIAZ-SANCHEZ,
Centro Nacional de Investigacion y Desarrollo Tecnologico, Cuernavaca, Morelos Mexico

JAIME RAMIREZ-ANGULO,
Klipsch School of Electrical and Computer Engineering New Mexico State University. Las Cruces, New Mexico, USA

NCHEZ-SINENCIO AND GUNHEE HAN

EDGAR SA
Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX

Received April 10, 1998; Accepted June 20, 1998

Abstract. This paper describes a highly linear current four quadrant multiplier. The circuit is designed to operate
in a fully differential way. It is based on the square-law characteristic of MOS transistors in saturation region.
Experimental results for 2 mm CMOS technology are provided.
Key Words: analog integrated circuits, analog multipliers

1.

Introduction

Four quadrant multipliers are one of the most

frequently used building blocks in analog applications, such as signal processing and articial neural
networks. Recent literature reports several works on
CMOS low power multipliers. However, most of them
were designed for voltage mode applications [1,2]. On
the other hand, reported current multipliers were
designed for specic applications or using bipolar
transistors [3].
The present work describes the design of a four
quadrant current/transconductance multiplier for
analog signal processing applications. The multiplier
fullls simplicity and operation requirements at
commonly used frequency ranges. In addition, the
circuit is extremely compact (134 mm 6 122 mm) and
can be used in modular design. The circuit is designed
to operate with + 2.5 V.

2.

Operation of the Multiplier

The current multiplier shown in Fig. 1, is based on the

square-law principle [4]. The differential current

signal inputs Ii and Ii are applied to regulated

source followers, and converted to voltage signals Va
and Vb respectively, as Fig. 2 shows. It can be shown
that nodes a and b have a very low impedance of
approximately:
Ra;b

1 1
gm gm ro

where gm and ro are the small signal transconductance

and output resistance of transistors M5 and M6.
These voltages Va and Vb are applied to the sources
of two differential cross-coupled pairs, M7-M8 and
M9-M10. Given that nodes ``a'' and ``b'' behave as
very low impedance sources, the drain currents in M7M10 are given by:
IdM7 kp

W
V Va VTH 2
L C

2a

IdM8 kp

W
2
V Vb VTH
L C

2b

IdM9 kp

W
V Va VTH 2
L C

2c

IdM10 kp

W
2
V Vb VTH
L C

2d

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A. Diaz-Sanchez et al.

Iout Iout
Iout
IdM7 IdM8 IdM9 IdM10
W
3
2kp VC VC Va Vb
L

Since Ii and Ii are complementary, we can assume

[8]:
s
Ii
VTH
Va
kp WL
s

I 2i
VTH

kp WL
!
 
 2
 3
 4
1 i
1 i
1 i
5 i
.
.
.

K 1

2 2I
8 2I
16 2I
128 2I

Fig. 1. Current multiplier diagram.

4a
VTH
s
Ii
Vb
VTH
kp WL
s
I 2i
VTH

kp WL
!
 
 2
 3
 4
1 i
1 i
1 i
5 i
.
.
.

K 1

2 2I
8 2I
16 2I
126 2I
VTH

4b

where:
s
I
K
kp WL

Subtracting equation (4b) from equation (4a) we have:

!
 3
i
1 i

...
V a Vb K
2I 8 2I
r
K
6
I Ii
V a Vb %
2I i
So, differential output current in equation (3) can be
written as:
Fig. 2. Transconductance multiplier.

where kp mn2Cox and VTH have the usual meaning of

transconductance parameter and threshold voltage,
respectively.
The resultant differential output current is obtained
as:

Iout &kp

WK
V VC Ii Ii
L I C

If the differential component of the input signal i is

small enough with respect to the common mode
component I (i.e. if i=I  0:25, total harmonic
distortion is less than 1%), then the approximation
in (7) is valid.
Cascode transistors M11 and M12 are provided to
reduce the drain potential uctuation of transistors

Transconductance Multiplier

M7-M10. Transistors M1 and M2 use W/L 8 mm/

3 mm, while regulator pair transistors M3, M4, M5 and
M6 use W/L 25 mm/2 mm. The cross coupled
transistors M7, M8, M9 and M10 use W/L 6 mm/
2 mm, and transistors M11 and M12 use W/L 14 mm/
2 mm.
The output of the multiplier is delivered as a
differential current signal using two low voltage
cascode current mirrors. All the transistors of the
output current mirrors are W/L 12 mm/3 mm.
Fig. 2 shows the transconductance multiplier. It has
the same operating principle as the current multiplier,
but its input voltage signal VB VB is delivered by a
differential amplier M1M2. The difference of the
voltage Va and Vb can be represented as:
Va Vb MVB VB

3.

165

Experimental Results

Fig. 3 shows experimentally determined DC transfer

characteristics of the current multiplier with
I 10 mA. It can be observed that the circuit has a
characteristic that is highly linear with deviation from
linearity less than 0.1% over most of the range of the
input signals.
Fig. 4 shows the measured frequency response of
Iout with Vc stepped from 0.4 V to 0.4 V, in 0.1 V
steps. The experimental bandwidth of the circuit is
120 kHz with a capacitive load of 15 pF, and it is seen to
remain approximately constant with gain adjustment.

where:
v

u W

ukp L M1; M2
M t W

kn L M3; M4

Iout
is given by:
The output current Iout Iout

Iout 2Mkn

 
W
VC VC VB VB
L
10

Fig. 4. Experimental frequency response.

where kp and kn are the transconductance parameters

of the differential pair transistors and of the load
transistors, respectively.

Fig. 3. Measured DC transfer characteristics.

Fig. 5. Microphotograph
multiplier.

of

fabricated

transconductance

166

A. Diaz-Sanchez et al.

The circuit was fabricated in 2 mm nwell technology (MOSIS). All current sources have channel
lengths of 3 mm in order to minimize mismatch
problems. Fig. 5 shows the microphotograh of the
transconductance multiplier, while Fig. 6 shows the
low harmonic distortion performance of the multiplier.
Fig. 7 shows experimental results obtained by
modulating a 50 kHz high frequency sinusoidal signal
with a 2 kHz low frequency triangular wave.

conductance multiplier. Its simplicity and compact

implementation allow it to be used in analog signal
processing systems [6]. The circuit is built using only
MOS transistors in order to be compatible with any
standard MOS process.
References

Fig. 6. Harmonic distortion performance.

1. J. Ramrez-Angulo and A. Daz-Sanchez, ``Low Voltage

Programmable Filter Using Voltage Followers and Analog
Multipliers.'' Proceedings of the IEEE International
Symposium on Circuits and Systems 2, pp. 14081411,
Chicago, Illinois, 1993.
2. S. Liu and C. Chang, ``CMOS Analog Divider and Four
Quadrant Multiplier Using Pool Circuits.'' IEEE Journal of
Solid State Circuits 30(9), pp. 10251029, 1995.
3. J. Ramrez-Angulo, ``Yet Another Low-Voltage Four Quadrant
Analog CMOS Multiplier.'' Proceedings of the 38th Midwest
Symposium on Circuits and Systems. Rio de Janeiro, Brazil,
pp. 405408, 1995.
4. E. Seevinck and R. F. Wassenaar, ``A Versatile CMOS Linear
Transconductor/Squared-Law Function Circuit.'' IEEE Journal
on Solid State Circuits SC-22(3), pp. 366377, 1988.
5. G. Han and E. Sanchez-Sinencio, ``Low Power CMOS
Multiplier.'' Presented at the IEEE International Symposium
on Circuit and Systems. Atlanta, Georgia, 1996.
6. J. Ramrez-Angulo, ``Highly Linear Four Quadrant BiCMOS
Analogue Multiplier.'' Electronics Letters 27(10), pp. 1783
1784, 1992.
7. J. Ramrez, S. C. Choi, and G. Gonzalez-Altamirano, ``Low
Voltage Building Blocks Using Multiple Input Floating-Gate
Transistors.'' IEEE Transactions on Circuits and Systems
I:Fundamental Theory and Applications 42(11), pp. 971974,
1995.
8. M. R. Spiegel, Mathematical Handbook of Formulas and Tables.
New York, NY, McGraw-Hill, Inc., 1988.

Fig. 7. Waveform multiplication. Vertical: 0.5 V/Div, horizontal

0.1 ms/Div.

Alejandro Diaz-Sanchez received the B.E. from

Madero Technical Institute of Astrophysics, Optics
and Electronics at Tonantzintla, Mexico. He is
currently working toward the Ph.D. degree at New
Mexico State University at Las Cruces, New Mexico.
His research concerns analog integrated circuits,
adaptive lters and analog signal processing.

4.

Conclusions

The present work describes the design and implementation of a low distortion current/trans-

Transconductance Multiplier

Jaime Ramrez-Angulo He is currently professor

of Electrical Engineering at the Klipsch School of
Electrical and Computer Engineering, Mexico State
University. BSEE, MSEE (1973, 1975) National
Polytechnic Institute, Mexico City, Ph.D. (82)
University of Stuttgart, Germany. His research areas
are analog and digital VLSI circuit Design, test
techniques for VLSI systems and design of fuzzy and
neuro-fuzzy VLSI hardware.

Edgar Sanchez-Sinencio (Professor) was born in

Mexico City, Mexico, on October 27, 1944. He
received the degree in communications and electronic
engineering (Professional degree) from the National
Polytechnic Institute of Mexico, Mexico City, the
M.S.E.E. degree from Stanford University, CA, and
the Ph.D. degree from the University of Illinois at
Champaign-Urbana, in 1966, 1970, and 1973,
respectively. During his graduate studies he was
awarded with fellowships from the United Nations
Educational, Scientic, and Cultural Organization, the
Mexican Atomic Energy Commission, the Consejo
Nacional de Ciencia y Tecnologia of Mexico.
From January 1965 to March 1967 he worked with
the Mexican Atomic Energy Commission as a Design
Engineer. In April 1967 he joined the Petroleum
Institute of Mexico, where he was associated with the
design of instrumentation equipment until August

167

1967. He worked as a Research Assistant at the

Coordinated Science Laboratory, University of
Illinois, from September 1971 to August 1973. In
1974 he held an industrial Post-Doctoral position with
the Central Research Laboratories, Nippon Electric
Company, Ltd., Kawasaki, Japan. From 1976 to 1983
he was the Head of the Department of Electronics at
the Instituto Nacional de Astrofsica, Optica y
Electronica (INAOE), Puebla, Mexico. He was a
Visiting Professor in the Department of Electrical
Engineering at Texas A&M University, College
Station, during the academic years of 19791980
and 19831984. He is currently a Professor at Texas
A&M University. He was the General Chairman of the
1983 26th Midwest Symposium on Circuits and
Systems. He was an Associate Editor of News and
Events for the IEEE Circuits and Devices Magazine
(19851988), and an Associate Editor for the IEEE
Trans. on Circuits and Systems, (19851987). He was
an Associate Editor for the IEEE Trans. on Neural
Networks. He is currently the Editor-in-Chief of the
Transactions on Circuits and Systems II. He is coauthor of the book Switched Capacitor Circuits (Van
Nostrand-Reinhold, 1984). He is a former President of
the IEEE Circuits and Systems Technical Committee
on Neural Systems and Applications and CAS
Technical Committee on Analog Signal Processing.
He received the 1995 Guillemin-Cauer for his work
on Cellular Networks. He is a former IEEE CAS Vice
President-Publications. He was also the co-recipient
of the 1997 Darlington Award for his work on highfrequency lters. His present interests are in the area
of active lter design, RF-Communication circuits and
analog and mixed-mode circuit design. He is an IEEE
Fellow Member. He is the holder of the TI Analog
Engineering Chair. E-mail: sanchez@ee.tamu.edu

Gunhee Han received the B.S. degree from Yonsei

University, Seoul, Korea, in 1990 and the Ph.D.
degree from Texas A&M University, College Station,
in 1997.

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A. Diaz-Sanchez et al.

He was a Visiting Assistant Professor in Texas

A&M University during the 19971998 academic
year. He is an Assistant Professor in the Department
of Electronic Engineering in Yonsei University as of

August 1998. His research interests include mixedsignal circuit design, neural network, and digital
signal recovery.