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    Bài giảng ASIC - Tài liệu, ebook PDF

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    Lazy Bkk

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    CHUONG 1: Gidi thigu ASIC. LA Che logh ASIC san 5 1.1, Fulleustom ASIC. 1.2, Standard-Cell-Based ASIC (CBIC). 6 1.3. Gate-aray-based ASIC (GA) 8 VA PLD & FPGA sosssnmnnsnonnonnnrnnnn . cs 9 ° Lidl. PLA&PAL 12 Quitrinh thie ké ASIC. 13 Kéttugn CHUONG 2: CMOS logic. 2 i Pos 212 lobia van te oy son. 213. Mie logic. 22 Quitrinh ché tg0 CMOS 24.1. Dinh lujt de Morgan. 242. Drive strength 243. TG&MUX... 25. Té bio logic tudn ty (Sequential Logle Cell) 25.1. Bpehétd ligu~ latch or atch 252. Fliphop.nnn 253. Céng do od nang clock 2.6 VO cell 2.7 Trinh djch cell - Cell Compiler. HUONG 3: Thiét ké the vign ASIC. 3.1 Mé hinh tricia transistor. 32 Twhysinh 33 Logical Effort... 33.1, Use tinh te, 332. Digntich logic & higu qua logic. 34 Baitp.. HUONG 4: VHD! locked inverie Sach tham khao Michael JS. Smith, Application Spesifie ICs, Addison Wesley, 1997 Charles H. Roth, Digital System Design using VHDL, PWS, 1998 Stephen Brown & Zvonko, Fundamentals of Digital Logic with VHDL Design, Mc- GGrawHil, 2000 4. Neil LE, Weste & Kamran, Pri ‘Addison Wesley, 1993, David Johns & Ken Martin, Analog IC design, John Wiley & Sons, 1997 Kang & Leblebici, CMOS Digital ICs, Me-Graw il, 1999 Allen & Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002 John P. Uyemura, Cireuit Design for CMOS VLSI, Kluwer Publisher, 1992 Nguyen Quoe Tuan, Giao trinh ngon ngu VHDL de thiet ke vi mach, 2002 CAch thie tinh diém iples of CMOS VLSI Design ~ a system prospective, Bai dp: [20% "The inh [20% ‘Thi cudi ky (cho phép ding tai ligu: 60% D&n nhap Bing Karnaugh, 2-input NAND, NOR & vé mach CMOS logic tung duong, ky higu. Tam quan trong cia NAND & NOR gates. mng hén hop (compound gate), n-input gates, AND gate Bai tip 1 ‘Tham khio file [M-chip Disk on chip, filename: NOR_vs_NAND.pdi cong ngh§ NOR va NAND: kién tric cua NOR chi thich hop cho ede thiét bj lu tri tir 1 — 4MB, NOR cho higu suat doc cao nhung thai gian xéa va this gian lip trinh lin, nén khOng thich hgp cho céc thiét bi luu trit yeu cau dung lng va toc 6 cao nh hign nay. NAND ¢6 duge céc tinh ning vira néu, dung Inong tir 8 — 512 MB e6ng véi gid ca phai ching hon. Bi Iai, cc nha ché tao phai dong diu v6i giao dign khOng chuin (non-standard interface) vi sy quin Iy phic tap (complicated management) ciia NAND CHUONG 1: Gidi thigu ASIC ASIC (Application Specific IC). IC and PGA package (Pin Grid Array) (hinh 1.1). Hinh 1-1. An integrated circuit 10) (a) A pin- ‘rid array (PGA) package. (b) The silicon die or ‘hip is under the package ld. Tinh todn kich e@ IC: theo sb long eéng (logic-gate hay transistor) bén trong IC. ‘Dom vi tinh kich c& IC la NAND hoje NOR gate. Vi du: 100k-gate = 100.000 two- input NAND gates. 2-input NAND gate = 4 CMOS transistors. Tuong tw cho NOR gate, (xem chuong dn nhép) Cac giai doan phit trién ciia cong ngh@ tich hep: SSI (thap nién 70), MSI, LSI, VLSI, ULSI. (SSI v6i wii chue transistor tite c@ 1-10 gates, LSI 6 thé ché tao ‘microprocessor, thuit tic VSI (pho bién) = ULSI (Nhdt)) oe [SE PE ssc | = | Stange *_Kich 6 lon NMOS | Thipnién | MOS IC 70 Metal gate nMOS, churn of pMOS * ftede bude masking "Mat dé cao hon (denser) + Tiéu tn it ning long (consumed less power) ‘Thi truimg MOS IC — o ‘Dot phd: Polysilicon Gate cho phép tich hop nMOS & pMOS trén cing IC = Tigu tén it ning lugng hon nia * Polysiticon cho phép don giin qua trink ché a0 din dén tu nhd kich 6 IC Bipolar & BICMOS ICs vin duge sit dung trong cic img dung dign thé cao (s/v CMOS) nhu dign tir céng suat, xe hoi, mach dign thoai Feature size: dic trong bii 2; = % smallest transistor size; VD: 2. = 0,25um twong ‘img transistor nhé nhdt o6 kich o8 0.5 um (lién hé edu tao CMOS transistor va cén nghé ché tao) ‘Thong thuimg, xy dimg hé théng vi dign tir (microelectronic system) sit dung cic thinh phan chufin - “standard parts” hay IC chuiin - “standard ICs”. Sau sutra di ciia VLSI nhimg nim 80, ta ¢6 thé xdy dimg moi thir rén m6t IC don cho céc img dung chuyén dung khéc nhau (customized to a particular system) > “custom ICs”. Tat nhién li khéng phai trang hgp nio cing thich hop. Neuyén tic li dinh nghia yéu ciu bai todin (xiic dinh design entry), sau 46 xy dug mét sé phan sir dung standard IC, phin cdn lai sit dung custom IC > gid ré, tang dé tin cay. ‘Custom IC la hodn toan kh6ng cn thiét déi véi b6 nhé chang han. IEEE Custom IC Conference (CIC) > custom IC durge phat trién manh mé cho v6 86 cdc img dung khéc nhau > thugt ngit ASIC, IEEE International ASIC Conference cho rigng ASIC. ‘hin dang ASIC: Nain dang . o = Cae die diém vat ly = Phuong phap thiét ké ASIC ~ > ce loai ASIC 1.1 Cée logi ASIC 'Néu cdc khai nigm Wafer, Mask layer, Interconnect. Full-custom ASIC . Topi cells & rns ayers ue thi kth you chu user = gid thanh cao "© thoi gian ché tao 8 tuan (khéng bao gm thé gian thiét ké) 14.2. Standard-Cell-Based ASIC (CBIC) Neu cdc khdi nigm: Standard cell = logic cell = cell (AND, OR, MUX, Flip-Flop, Latch). Megacell = full-custom block = System Level Macro (SLM) = fixed block = core = Functional Standard Block (FSB). VD: SRAM, SCSI Controller, MPEG Decoder. Hinh 1-2 (CBIO) die with a single standard-cell area (a flexible block) together with 4 fixed blocks. The ‘Slexible block contains rows of standard cells. This is ‘what you might see through a low-powered microscope looking down on the dic of Hink 1.1). The small squares around the edge of the die are pads that are connected fo the pins of the ASIC package. Bie diém CBIC: | ‘= mask layers duge thiét ké theo yéu chu user vy cell & megacell 6 thé dat bat ky du va trén cing 1 chip us + Cell duge thitké sin (preesigned) > mb cll duge tht ké ti wu de ip * Cell dugc kiém tra (pretested) > gitm ri ro = Cell duge die ta rd (precharacterized) > gidm gid thinh side ig ho pian hig ae rere gin hi hay chi phi mua the vi ot Thai gan ché to cde mask layer * Thi gian ché igo: 8 twiin (khng bao gbm thoi gian thiét ké) Cell-based ASIC (CBIO) Gate-based ASIC (GA) ‘Dim chung: Predesigned cells, ‘C6 thé thay d6i kich o& transistor trong cell | Kich cé transistor e6 dinh (fixed cell) 4é 161 wu hoa toc d6 va higu suat Surthoa higp git digmtich (area) va higu | > Syr thos higp gita din veh (area) vi higu ‘suit (performance) 6 ting thu vign suit (performance) 6 ting silicon ASIC tién tién dung 2 dén 3 lip kim logi (metal layer) hoe nhiéu hon cho interconnect. Metal 1: power bus. Metal 2: input hay output cells. Xem hinh 1.3. Hinh 1-3 layout of a standard cel, with 4 = 0.25 microns. Standard cells are stacked like bricks in 44 wall; the abutment bax (AB) defines the “edges” of the brick. The difference between the ‘Bounding box (BB) and the AB is the area of overlap beaween the brick. Power supplies (VDD and GND) rum horizontally inside a standard cell on a metal layer that les above the transistor layers. Each different shaded and labeled pattern represents a different layer. This standard cell has ‘enter connectors (the three squares, labeled AI, B1, and Z) that allow the cell to connect 0 ‘others. The layout was drawn using ROSE, a symbolic layout editor developed by Rockwell and Compass, and then imported into Tanner Research's L-Eidit. Ce kd i Feedthrough: dung din kim loai xuyén qua cell Spacer cell: hhigu chinh chigu doe cic hing cell Row-end-cell: ‘két ndi nguén cho cdc hang khée nhau Power-cell: ding khi cell-row qué dai See ge 0 ee na roet ot atone Hinh 1-4 Routing the CBIC (cell-based IC) shown in hink 1.2. The use of regularly shaped standard ells, such asthe one in hink 1:3, from a library allows ASICS lke this tobe designed automaticaly. This ASIC uses to separate ayers of metal Interconnect (metall and metal2) running at right dangles 10 each other (like traces on a printed-circut board). Interconnections between logic cells uses spaces (called channels) between the rows of cells. ASICs may have three (or more) layers of ‘metal allowing the cell rows to touch withthe interconnect running over the top ofthe cells. Datapath: Khi nhigu tin higu di qua mot bus dir ligu thi cfc logic cell khong cn higu qua, khi 6, datapath durge sit dung. Tao ra datapath bing datapath compiler tir cic nha SX. Datapath library bao gom cée datapath cell nhut la: b9 cong - adder, b6 tri - subtracter, b@ nhan - multiplier & khéi logic s6 hoc don gian ~ simple ALU, Uw; két ni cée datapath cell dé tg0 nén datapath thong thurimg cho ra layout chit hon (tén it ign tich) & hogt dng nhanh hom (so v6i standard-cell hay gate-array). 1.4.3. Gate-array-based ASIC (GA) SY tw doc séich 14.4. PLD &FPGA ‘© Logic cell vA mask layer ob sfin (khéng theo yéu clu user) Interconnect kha trinh ‘+ Ma tran cic macrocell bao gm cdc PAL + FF hoic Latch ‘* ‘Thdi gian thiét ké hoan chinh kha nhank (vai gid) Ficld-programmable: PROM, EPROM, EEPROM, UVPROM ‘= Mask-programmable: Mask- programmable ROM (Masked ROM) Field-programmable: céc két néi ding chuyén mgch lap trinh duge (céu chi ching hen, CMOS transistor) & vi véy chim bon cfc két ni cig numgo6 un Gide a ré khi SX v6i s6 lugng nho va thi gian I§p trinh tie thi, ‘Mask-programmable: cic két n6i bén trong duge thu hign bing phin cimg khi SX 66 nhuge diém la lp trinh mat vai thing, song bi Iai gid thanh gidm néu SX véi 5 Jugng 16m. PLD: gm khéi cng AND néi véi khéi cng OR. Mach logic thye hign trong PLD theo dang ting cia tich (sum-of-product). Cie logi PLD: . . + PLD co bin: PAL (Khéi AND Kha trinh, kh6i OR 6 dinh) PLD linh hogt: PLA (Khéi AND va OR déu Kha trinh), PLA cé thé la mask- programmable hay field- programmable. Cé hai loai PLD trén cho phép thuec hin cdc mach logic tée di cao. Tuy nhién edu tric dom gin ciia nd chi cho phép hin thy cde mach logic nh. Ci PLD phitc tap (complex PLD - CPLD) due biét aén nhur nhimg FPGA. Minh 1-5 FPGA dic. Chu trie FPGA ox thin bao gm cée eel! khi inh bao ‘quanh bit interconnect Kha tinh, Cie Iogi FPGA Khe nau o6 x6 lng cell & ih cell ft Khe nba. 1.41. PLA & PAL (Cu trie PLA: Mang logic kha trin, ‘Tim bang PLA hang toi thigu ‘Cfu trée PAL: Logic mang kha trinh, la tr.h ring ciia PLA - ming OR c6 dink, Bai tp 2 1.2 Qui trinh thiét ké ASIC i =I A. |= aa Finen Hinh 1-6 ASIC design flow Better impress this flow on the memory by explaining in comparison with building construction. 1. -Mé ta bai todn: sit dung ngén ngit mé ti phin cimg HDL (VHDL hay Verilog) (VHDL by Department of Defense in 1980s and standardized by IEEE in 1993 - Verilog is created by Cadence in 1989 and standardized by IEEE in 1995) 2. Téng hgp logic: ding HDL va céng cy ting hgp logic dé xay dyng netlist — la sir mo ta cde 18 bao (cell), ede KhOi (block) va két n6i (interconnect) gitta ching 3. Phan chia hg théng: chia hé thong Io thanh céc phan thich hop 4. M6 phong tién layout: kiém tra tinh ding diin cha thiét ké (tién layout = so 48 mach logic — chi gn diing voi thye t8) 5. Shp xdp che khbi trén chip: skp xp che khbi cia netlist trén chip. Nén xem x6t ch khia cqnh vAt lf vi logic khithiétké bude ndy B6 tri cel: dinh vj cell bén trong kh6i Thiét ké tayén: ket n6i git céc cell va cée khdi Kiém tra tink hop {f ctia bude 7; tinh toin tr khing va dung khing lop interconnect 9. Mé phing hu layout: kiém tra kha ning lam vige én dinh cia toan bo thiét é trong trudng hgp ¢6 thém tai tr dp interconnect (hau layout ~ so 46 mach tye 18) Cac bude 1-5: logic. (Cac buée thigt ké 5 —9 : vat ly. 1.3 Kétluan ASIC: thay vi phiii xem x6t nhigu khia canh trong khi thiét ké ché tgo IC chudin thi cedng ngh ASIC cho phép t6i tru héa thiét ké theo mt mye dich cu thé (specifi task) nén s& cho higu suit cao hon, cu thé la cho phép liu git lugmg mach logic (chi chi 14: mach logic) lon hom so véi céc chip chuan cing kich thuéc. Ben canh tinh tin cy cao thi IC don 1é con chiém dung it khéng gian hon trén bo mach in, kéo theo gid tinh 1 hon 20 v6i 1 bé théng 06 cing mpe dich si dung nhitu IC chain, Trinh ty thidt ké ASIC theo eée bude : 1, Thiét ké logic (logic design) 2, Chon ky thus thich hop thiét ké mach vit IY (physical design) 3. Ché tgo chip (fabrication) bai Ong ty chuyén nghigp. ASIC kha trinh: CPLD hay FPGA: chia céc chuyén mgch lip trinh duge nhiéu lin (cée chuyén mgch sir dung cho cé cell kha trinh va interconnect kha trinh). Cée PLA thugmg durge xem la thinh phan co bin cia FPGA. CPU Pentium 4 chika 55 trigu cong ché tao biing cong nghé 80-130nm, Véi céc vat ligu méi, chip ngay cing dice thu nhd thi Kh dé leg dig thodt ra ki bing bin dan cang lan, do dé tao ra site néng lim hom va khién cdc transistor dé bj hong (tea rnlue phién ta nhige edng nhé thi kha ning tin nhigt cang thdp). Theo ghi nhdn cia ede nhi Khoa hoc DH Maryland (Mj) thi silicon da cé hau dug: a5 la carbon nanotube. Chat nay 6 dp din dign manh gdp 70 lin silicon, déng thoi ciing cho ‘uring 6 dang dign lon hon. Trong khi theo hang Toyota va Denso thi chit méi 1a Siticon Carbua (SiO). Cudi nam 2003, Intel thang béo sé cho ra déi chip 45 - 65Snm trong thoi gian t6i, thi ‘vio thang 09 ném 2004, chip mdi véi cng nghé 65nm (I 1} transistor) da ra déi. Intel khéng cho biét tén chinh xc logi vt ligu méi. 10 CHU'ONG 2: CMOS logic Dain nhp: ching ta 48 biét ti vige sir dung NAND hoge NOR nur ef tinh phiin co bin trong ché tg0 IC. Vay tai sao Iai phai la NAND hoje NOR? Céu thinh NAND hay NOR theo céng nghé CMOS ca ban tigu tén 4 transistor (2 nMOS vi 2 pMOS) trong khi cic cng AND, OR cling cé thé ché tao tir 4 transistor!!! NAND gate: Z = (AB)’ Diode va ving nghéo: céc tiép xiic kim loai thuémg néi véi viing p+ vi nt (C6 mite ich tap cao hon so v6i p va n) dé trinh cfc diode schottky. Ving p+ c6 tuomg lin cic jon dong ty do edn trong ving n* e6 lung Kin ede ion fm ur do, LB tng trong p+ 6 khuynh hurimg khuéch tén sang phia n trong khi electron trong n Iai khuéch tén sang p+ (ging nhur cdc loai gas trén lin vao nhau). Sy khuéch tén vi vay lim gm su ‘ip trung cia cée ion ty do trong viing tgp xiie. Khudeh tan eva electron ten 38 Kin xh ving dia tich + bén phia n tei ving x, nguoc 1gi, Khuéch tén ota 18 tring tir p+ sé lim xh ving din tich ~ bén phia p tai ving Ux. Sir khuéch tin ca eéc ion ty do nay hinh thanh nén ving t/x nghéo (depletion region). Sid; Dige ruing = z me +] a2 pajunction pe Bale ——~ —_—s OE Ving nehdo Mele dade pon MG hi dom gin — 45 rg ing ‘nghé ln hom cho pha ich ap thip High 2-1 Diode p-n_ Diode schottky: khi cé tiép xtc kim logi trac tép tai bé mat chét ban din kich tap nhe (a, n- hay p, p-), digu nay khién cho dic tinh diode c6 thay déi so véi p-n junction diode thong thiimg, 1. Vo nhé hon binh thudng, sur khc biét vé tinh nang lim vige gitta kim loai vam Toi va n+. 3-0.5V sv 0.6-0.8V div silicon p-n diode, 1a do ‘cao hon s/v giita kim u 2. ‘Dang trong diode schottky chi do hat din da s6 tao nén (electrons). Khi diode phan eye thugin sé khdng edn su tich dign cia hat din thiéu s6 trong ving n-, hay n6i Cs=0 (depletion cap) trong m6 hinh tong dung tin higu nho. Diéu niy lam cho diode dap img nhanh hon, dic bigt la khi turn-off - vi khéng cén phai xa dign tich GaAs duge diing ché t90 diode schottky. Sid: Pr Buk Mat cit diode Schoey inh 2-2 Diode Schottky ‘Vai trd nt cho cde tiép xic gta bin din kich tap nhe véi kim logi? 2.1 CMOS transistor = Hinh 2-3 nMOS transistor. ety || rhe geteenide thickness L Tac , is approximately 100 os Yes] sane] |" | angstroms (0.01u mm). A ° ‘ppieal transistor length, L=2A.. bulk = substrate = well, The diodes represent | ae nsjuncions that must be reverse-biased, khong din dign (khdng c6 sy di chuyén cia cée dign tich - electron). Dé kich din transistor MOS loai kénh n, ching ta cdn dua vo eye G dign thé Vos duong len hon “dign thé nguémg Vi, ~ threshold voltage c& 0.SV. Bign thé nay lim hinh thinh 1 kénh din rit ming (50A° , 14° =10°"m) bén dud bé mat eye eika G. (MOS tran tgo ra dng ri vai micro ampe khi Vos bé hon Vi, tam thei Khong xem xét ti TH nay). ‘Transistor MOS c6 thé din ma khong c6 dong chay qua. Dong chi c6 khi d3t ign thé Vps hgp Iy vio 2 eye D va S. Vos la duong voi nMOS. Well (bulk , substrate or tub): két néi véi noi e6 dign thé nhé nhit, ky higu GND hay VSS, nhim dim bao phin eye ngurge cho céc diode hinh thanh bdi cde tiép gidp p-n tia bulk — drain hay bulk — source. Mai tén & terminal 4 - bulk bigu dién chiéu cia cfc diode nay. 2 Dang qua transistor (A) = dign tich (C)/ thoi gian (s) ‘Néu goi Q 1a téng dign tich trong kénh dn, t; Ia thei gian cde dign tir di chuyén tir S sang D (noi e6 dign thé thap sang noi c6 dign thé cao), thi dong Inso ¢6 gid tr: Tog, = 2 1) ‘Tim te That vay, theo Ohm’s Law: Vane (0.2) 14, 4 di dong dign tir = 500-1000.cm"V's"'. E (Vm") trang din tir gy boi Vos. DE don gidn, v6i E ta chi xét thanh phin ngang Ex, bd qua thanh phin doc Ey. E,=Voo/L tinh tir D 163 S. L: chigu dai gate, = 22. Dign tir di chuyén qua doan durimg L véi van tbe v=—1,£ tén khoding thoi gian: L_P vos ‘Tim Q: kénh din va gate tao nén 2 bé mat cia I tu dign ma chit céch dign la dioxide. V@i ty tuyén tinh Q=CV. Vi TH ching ta, kenh din a bé mat din dign phi tuyén tinh ~ dign tich chi xudt hign trén kénh khi Vj. kin hom ¥,,..V6i ty phi tuyén thé nay, ta 6: Q=CV gee) (04) trong tb C= «M1, (03) &, lihiing s6 dign méi gate-oxide. C,, 18 din dung don vi. Ta.cd Voc =Vog tai S vA Vac =Vox Vag Néu gid sit Voc ld him tuyén tinh theo x (0 PL), thi gid tr trung binh cia dign tich: os) bid didn Q theo cde tham sb transistor: o=m,| as-%0)-$os} 6) Cudi cting ta 66 edng thie cho Tos: w * Cu) Cos Vu ri fe ) f 1 Hl sha) Lost 0.7) =A WixYa)~ 4% Po trong 6 ham s6 hb bn (transconductance parameter): (0.8) (0.9) 1B voi z 1a h@ s6 hinh dang (shape factor) ‘Viing tuyén tinh Visg > Vi.Vag SVs Vox =Vosiuny? linear region - triode region (0.7) biéu din hogt déng transistor trong ving tuyén tink Ving bio ba Vs > V Vas > Vor Va = Vegi Saturation region ~ active region hi Pog Vuot qué gid tH Vag thi gid tri Voc khng i cho vige duy tri kénh din, Vectaay =Vos —Vostuay Vee TeeTy 1) SA ae Tos =~ Wes Vo) Vas Ips). Ng ra D Iie nay chuyén sang logic 0 — va diy thye sy la logic 0 ing ngkia — logic 0 kde. Gidi thich tuong ty, hinh b cho logic 1 yéu, hinh ¢ cho logic 0 yéu, hinh d cho logie 1 khde. Két ng: nMOS cung sip logic 0 khée, logic 1 yéu. pMOS thi nguge Iai. Ghi nh nguyén tic nay khi thiét ké mach, Néu cfc cell e6 img dung nguyén tic trén, phan tich hoat dng cia cell dé lam r6 wu ” inh 2-9 sora Gia sit ede transistor o6 kich thuée 6 dinh va bing nau. INV cfu thinh boi 2 transistor c6 tham s6 hé dln lin uot li 2k, va ky/2 (ky~4k,). Neu mudn ding NOR2 & tao INV dat duge 49 bén diéu khién thi cdc transistor tong NOR2 phai cé tham ‘so h6 dn la bao nhiéu? Giai thich, vé hinh? Tri lois ai INV véi cde gid thiét 45 cho la dat durge 46 bén digu khién. Da biét: R ty 1é nghich voi =k, trong.ab © cb dink, Cho néa: T T Reww = Ryvows + Rywons 1 1 wv = Rovorr !! Revonr = Kavon = kaw i ae Flor “Tinh tin con s6 224 ells (lor AOL fail) 243. TE&MUX Lome hs went om en . . « Hinh 2-10 CMOS transmission gate (TG). (a) transistor kenh p vin mic song song tgothinh "TG. (b) KS higu TG thong dyng (c)hign tuyng chia sé dign tie Biéu thie TG: Z=TG(A, 8) (Chi ra uu diém sir dung 2 transistor s/v pass transistor, v8, giai thich. Nhuge cia TG: hign tugng chia sé dign tich (charge sharing) véi phim mach nh trén = cho vi dy chimg minh, +, =/Sicsuu “A0CRe. Cg = O.2pF (10 Lin gid tr] tai chudin véi G5) Cswatt = 0.02pF. Vaio OV, Vswati=SV thi tinh duge Ve = 0.45V. Cach edi tién: ng6 vao dii manh hog la ding butter gitta A va Z ‘Thike ké MUX: 2 cic 1. siedung TG 2. sir dung te bao logic AOI, OAL Céch 1: Thiét ké MUX2:1 ding TG: Z = TGA, S) + TGB, S)=A.S+B.S-MUX(A,BS) 7y 2 Mink 2-11 CMOS MUX. (a) MUN2:L ding'TG khing 6 b9 fn (b) KS hu MUX () KS hig ‘MUX theo chuiin IEEE (d) Ky higu MUX phé bién (theo IEEE) (e) MUX dao ¢6 d@m ngé ra {D MUX2II 6 dim vao ra. Giai thich. Cac tnrimg hop (e) va (f) lc tién cia (a). Gai thich ¥ nghia G va ch thite tic dng. Néu la MUX4:1 ta 06 w01,2,3 voi s1,0. ‘Céch 2: Thiét ké MUX2:1 dio ding OAI cell: ZN = A’S' + B'S= [(A'S') - (B'S) = [(A+S)(B+S)} = OAI22[A,S,B,NOT(S)] . Minh 2-12 MUN2A ding OAI2 cl Sumo ‘SED Preduct ciel) A ip ‘Thiét ké MUX2:1 sir dung té bao logic AOI? ‘Thiét ké MUX 4:1 ding AOL cell? ‘Thiét ké MUX 4:1 ding MUX 2:1? ‘Thiét ké MUX 16:1 ding MUX 4:1? ‘Thiét ké tri-state buffer diing TG tranh hign tugng chia sé dign tich? XOR XOR(AL,A2/*AL.A2"+A1'A2°MUX(ALNOT(A1),A2) XOR(ALA2-NOTIMUX(NOT(A1)NOTONOT(AT)}A2)] XOR(AI,A2)ALA2+AT’A2={ALA2+A1’.A2'=[(ALA2}4AT+A2)) AODITALA2,NOR(ALA2)] (AL.A2}+NOR(ALAD)) XNOR BNOH(ALAD}ALADAT“AZ-NOTINOTIMUN(ANOT(AI)ADFOAIIIALAZNANDALLA Chi ra cée wu diém TG so véi pass transistor? ‘Thiét ké XOR2 sir dung TG sao cho téng s6 transistor la 8 hoc 6? 2.5 Té bao logic tuan tu (Sequential Logic Cell) So sinh mach logic t6 hgp (CL) va logic tuin ty (SL). Moore & Meal FSM. 23 Hai pp clocking chinh trong e®ng nghé VLSI: 1, Xung dong hé da pha hog dom pha - multiphase or single clock dong b9 - synchronous design «wu diém hon nhur 1, Cho phép thiét ké ty dong 2. Antodn 3. Cho phép thye thi ASIC giéng nhur d3'm6 phing - vendor signoff 2.5.1. BO chét dor ligu — latch or D-latch Hinh duéi day chi ra 1 logic cell tun ty - latch hay D-Latch. Xung ding hd bén trong (adi) CLKN (N for negative) & CLKP (P for postive), tao tir xung clock he thong CLK, bai 2 cing dio (14, 15). Hai cdng dio nay la ben trong latch. Tuy e6 thé tet kigm khéng gian song sé nguy hiém néu tao céc tn higu nay bén ngoai. inh 2-13, CMOS latch. () Lateh kich > hat mire Zoom] | diromg (ding eer, "TG king 06 «dem ng ra), sxung lock “a ex | duge ag ben STATS | ton Latch a. ae in kh xumg AN, OL | crock mie exo of @ ‘ (©) Lateh ou 1 ergug hal {91D khixung clock xubeg mire thip. DE nhin man si khée nhau gitta latch véi FF ngudi ta goi ng6 vao clock latin higu cho phép (enable), nhin vao hinh (b), khi xung clock mic cao, Latch din thong, nghia imi thay déi 6 D din dén sy thay 46i ng@ ra Q (rat khic so vi FF s€ xem xét sau). ‘Cén khi clock xudng mée thip, nhur trong hinh (c), céng dao 12 va 13 két néi véi hau tao nén vong hu git trang thai ct tai D cho dén khi c6 clock mite cao tré lai, Vong niy thye hign cng vige Inu git chimg nio con cung cp nguén, cho nén goi day Ia Tatch tinh. Logie tuiin ty khéie véi logic t6 hop 1a vi die diém liu tri hay nhér ny (leature of storage or memory). Neb ra Q la khong dm vi két nbi tre tip én ng ra 12, chinh 1 mit tr, Thu vign ASIC thong c6 thém 2 INV ngé ra cho Q va QN nham dam bao cach ly cho nut liu tr. Khi ndy Latch bao gém 7 INV va 2 TG ben trong (4.5 gates) Latch kich kh mite am: thém eng di cho eée xung clock bén trong hoge hodn déi chite ning CLKN véi CLKP. 25.2. Flip-Flop Ding 2 D-latch (master latch & slave latch) xy dmg Flip-flop nhw trong hinh, FF gim 9 inverters & 4 TGs, tire tong céng 6.5 gates. Nit luu trit $ duge dém. 24 Tr clock-to-Q + tr8 inverter tr clock-t0-QN. o » «o > P aime [45 1, lend nate ave aca lb ave ax_a @ 0 Ly wane ae

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