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Common Mode Rejection Ratio: Open Loop Gain
Common Mode Rejection Ratio: Open Loop Gain
common
mode
gain
v1
v2
vcm
vo
vo
A = ----------------v2 v1
vo
vo
A cm = --------v cm
A
CMRR = ---------A cm
Lecture 8-1
CMRR
We would like to have an infinite CMRR
v id = v 2 v 1
v1
v2 + v1
v Icm = ----------------2
v2
v o = Av id + Acm v Icm
Lecture 8-2
CMRR
Not really a problem for inverting amplifier configurations --- why?
R2
R1
Vo
Vin
Lecture 8-3
Difference Amplifier
Also a problem for difference amplifiers
R2
R1
Vo
Va
Vb
Lecture 8-4
Difference Amplifier
We have to scale the voltage vb to achieve balanced amplification of vb-va
R2
R1
R1
Va
Vb
Vo
R2
Lecture 8-5
CMRR
Opamp data sheets specify the CMRR for the opamp itself, but the opamp
Rf
Rs
vo
vin
vp
R1
R2
Lecture 8-6
v1 _
v id
v2
IB1
IB2
There is also a component of input current that changes with input voltage
v Icm
Rcm
v1 _
v id
v2
Rid
Lecture 8-7
Input Resistance
These resistances are generally quite large: Rcm ~ 100M, and Rid ~ 1M
These resistances are even larger for MOS opamps
2Rcm
Rid
2
2Rcm
Lecture 8-8
Input Resistance
These opamp input resistances do not affect an inverting amplifier
Vin
But these resistances are what determines the input resistance of a non-
Lecture 8-9
Input Resistances
The resistors R1 and R2 should be kept significantly smaller than the input
R1
v1
2Rcm
vo
Rid
iin
v2
2Rcm
A ( v2 v1 )
vin
Rin
Lecture 8-10
Input Resistances
R2
R1
v1
2Rcm
vo
Rid
iin
v2
2Rcm
A ( v2 v1 )
vin
Rin
Lecture 8-11
if
vin < 0
R1
iL
Ro
A ( v 2 v1 )
RL
note that vo
definition is
changed when
output resistance
is added to
the model
Lecture 8-12
Ro
A ( v2 v1 )
Lecture 8-13
output impedance
Lecture 8-14
dc output response
R2
R1
IB1
IB2
Lecture 8-15
Compensating for IB
In practice, a resistor is added so that the bias current drops are compensated
Rs
vo
vin
Rcomp
Lecture 8-16
Compensating for IB
R2
R1
R3
IB1
IB2
Lecture 8-17
dc Offset Voltage
Another unwanted dc output signal is due to the dc offset voltage
A dc differential input is required for a real opamp to zero the output
This offset is due to mismatch in transistor parameters, and is temperature
VOS ~ 1-5mV
1
VOS
Lecture 8-18
Rs
vo
vin
VOS
Lecture 8-19
ac Coupling
We can avoid this offset voltage at the output by using ac coupling
Rf
CC
Rs
vo
vin
VOS
Lecture 8-20