ECE 410 Microelectronics II

Homework #6

Dr. Suat Ay

Fall 2015

Due Date: 11/11/2015 - Wednesday

Two-Stage CMOS OPAMP Design
Design and simulate and n-type two stage, miller compensated CMOS OPAMP satisfying all of the following
specifications.
Av
PM
GB (fu)
SR
Pdiss
Input CMR
CL
Vaa

(20-pts)
(15-pts)
(15-pts)
(15-pts)
(15-pts)
(20-pts)

> 60 dB
> 60o
> 10MHz
> 10V/sec
< 5mW (DC and peek)
>1.0Vpp (i.e. 1.2V to 2.25V)
5pF
+3.3V

Use: Allen/Holberg handout for design and procedures. Also use Table 6.3-1 as guidelines if you need to do
iteration during simulation. Use Cadence IC design tools and class model card which is 0.35um CMOS analog
process. Turn in your simulation result plots, simulation setup and schematic plots along with your hand
calculations (W/L of all TRs, I bias, I5, and I7 currents, Cc capacitor, etc.) and design justifications and
explanations. Ideal current/voltage sources (Ibias /Vbias) from analogLib could be used for the design.

Use NMOS and PMOS transistors for your design. For hand calculation use the information given for the
transistors in next pages. Also use CMOS_opamp_simulation_and_measurement.pdf handout for simulation
setup to verify the design spec.

Make sure that you went through CADENCE IC design tools tutorials before you start working on.
http://www.ece.uidaho.edu/ee/analog/suatay/cadence.html

It is not encouraged but GROUP WORK (maximum 3 students) is allowed on this assignment. If you work in
groups, report how you collaborate and who did what on this assignment CLEARLY. Use of reporting template
(Report_Template.v1.doc) is mandatory for group works.
If you work alone, 10pts bonus will be considered if reporting template is used.

ECE410 Microelectronics II

1/3

University of Idaho

ECE410 Microelectronics II

2/3

University of Idaho

ECE410 Microelectronics II

3/3

University of Idaho