set lib_path "/users/eesunz/faculty/cdsemac/EE5375/UTFSM_libraries"

set syn_path "/export/cadence/synopsys/Synthesis/libraries/syn"

set search_path [list "$lib_path/MW_UTAH" "$syn_path"]
set target_library [list UofU_Digital_v1_2.db]
set synthetic_library [list dw_foundation.sldb standard.sldb]
set link_library [concat $target_library $synthetic_library]
# These cells have two outputs which causes a DRC error in ICC
set_dont_use UofU_Digital_v1_2/DCBX1
set_dont_use UofU_Digital_v1_2/DCBNX1
define_design_lib work -path ./work
#############################
# Change this to your file(s)
#############################
analyze -format verilog ./xtal_chip.v
#############################
# Change this to your module name
#############################
elaborate xtal_chip
#############################
# Change this to match your clocks and timing constriaints
#############################
set_max_delay 25 -to [all_outputs]
create_clock "clk_in1" -period 100
create_clock "clk_in2" -period 100
create_clock "clk_in3" -period 100
#############################
# if you have an internally generated clock instantiate a buffer
(BUFX2)
# to provide a pin to identify the source of your new clock
#############################
create_generated_clock -divide_by 1024 -source clk_in1 [get_pins
{buffer/Y}]
report_clocks
check_design > check_design.output
ungroup -flatten -all
set_flatten true -effort high
uniquify

compile_ultra
#############################
# Check these files once completed
#############################
report_area > area.rpt
report_hierarchy > hierarchy.rpt
report_constraints > constraints.rpt
report_timing > timing.rpt
set_propagated_clock [all_clocks]
#############################
# Your timing file for IC Compiler
#############################
write_sdc xtal_chip.sdc
#############################
# Your output netlist
#############################
write -f verilog xtal_chip -output xtal_chip.post_synth.v -hierarchy
exit