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Group 8
Objectives:
a) To calculate the small signal gain of given common source amplifier.
b) Enhance the small signal gain of given circuit by changing value of R D and putting two NMOS
in parallel.
Component Values:
a)
b)
c)
d)
e)
VDD = 12.37V
0 to 11.14 k rheostat
IC 4007 for NMOS
2.64 k resistor
2.71 k resistor
Circuit Diagram:
Data Tables:
1.) For RD = 2.71 k
VGS(V)
0
0.71
1.15
1.43
2.15
2.55
3.06
3.41
3.84
3.91
4.17
4.25
4.46
4.43
4.84
VDS(V)
12.36
12.36
12.36
12.35
12.16
11.45
9.84
8.33
6.05
5.63
4.05
3.59
2.23
2.42
1.16
2
4.95
5.20
5.53
5.87
6.41
6.99
7.60
8.25
9.11
9.93
1.08
0.95
0.84
0.76
0.68
0.61
0.56
0.52
0.47
0.44
VDS(V)
12.36
12.35
12.35
12.09
11.88
11.38
10.74
10.58
10.00
9.46
8.25
7.95
7.29
6.46
5.64
4.70
3.77
2.55
2.32
1.19
0.78
0.67
0.61
0.53
0.48
0.44
0.34
0.28
0.27
0.25
3
VDS(V)
12.36
12.36
12.36
12.3
12.24
12.01
11.24
10.61
9.52
10.33
7.89
8.44
5.53
7.14
4.54
3.57
2.1
0.9
0.45
0.56
0.35
0.23
0.19
0.16
0.14
0.12
Plots:
Discussions:
Abhinav Kumar Verma, 14EC30001
1.) The graph observed as a result of this experiment was expetcted from theorectical result
too.
2.) Two ways of increasing gain are to increase the resistance RD or to put two NMOS in
parallel.
3.) Increase in gain results to decrease in maximum swing of input possible.
4.) By curve fitting of what is normally thought tobe linear part to a polynomial, we can predict
the harmonics that will be present in the output signal.