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  • VLSI Design Lab Assignments

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    Tarun Vatwani
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    1. The document outlines the assignments for a lab course on VLSI design techniques. It includes two assignment sheets with 4 assignments on topics like designing arithmetic/logic applications in VHDL/Verilog, implementing graph algorithms for high-level synthesis, optimizing logic functions, and optimizing sequential circuits. 2. It also provides examples of basic logic gates and applications that can be used for the first assignment, including a 4-point FFT, Cordic algorithms, and averaging floating point numbers in arrays. 3. Finally, it lists problem sets for algorithm implementation involving topics in boolean algebra, graph-based optimization, list scheduling, and allocation and binding.

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    LabVLSIIITJ

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    LabVLSIIITJ

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    1. The document outlines the assignments for a lab course on VLSI design techniques. It includes two assignment sheets with 4 assignments on topics like designing arithmetic/logic applications in VHDL/Verilog, implementing graph algorithms for high-level synthesis, optimizing logic functions, and optimizing sequential circuits. 2. It also provides examples of basic logic gates and applications that can be used for the first assignment, including a 4-point FFT, Cordic algorithms, and averaging floating point numbers in arrays. 3. Finally, it lists problem sets for algorithm implementation involving topics in boolean algebra, graph-based optimization, list scheduling, and allocation and binding.

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    © All Rights Reserved
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    12 views2 pages

    VLSI Design Lab Assignments

    Uploaded by

    Tarun Vatwani
    1. The document outlines the assignments for a lab course on VLSI design techniques. It includes two assignment sheets with 4 assignments on topics like designing arithmetic/logic applications in VHDL/Verilog, implementing graph algorithms for high-level synthesis, optimizing logic functions, and optimizing sequential circuits. 2. It also provides examples of basic logic gates and applications that can be used for the first assignment, including a 4-point FFT, Cordic algorithms, and averaging floating point numbers in arrays. 3. Finally, it lists problem sets for algorithm implementation involving topics in boolean algebra, graph-based optimization, list scheduling, and allocation and binding.

    Copyright:

    © All Rights Reserved
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    of 2

    8th Semester B. Tech./2nd Semester M. Tech.

    2015-16
    VLSI Design techniques Lab.
    Lab-Assignments Sheet 1 (Total assignment sheets are two)
    1. (a) Design data-path & control for an arithmetic/logic application.
    a. Verify using VHDL/Verilog.
    b. Synthesize using Xilinx FPGA tool
    2. (a) Devise a method to input a graph into a C-programme.
    a. Implement any one algorithm for high level synthesis- (i) Scheduling, (ii)
    Allocation OR (iii) binding.
    3. Find optimal representation of a given 6-input logic function using different
    optimization techniques. [Logic synthesis]
    a. Manual method: K-map OR Quine-McClusky
    b. Computer based method: Esspresso tool
    4. With an FSM as input, find an optimal sequential circuit using different
    techniques.
    a. Manual method: State minimization
    b. Computer based method: SIS tool
    c. Timing optimization method
    A-1. Basic logic gates/functions- Half adder, full adder, 2-to1MUX, FF, Register, counter,
    Decoder, Encoder etc.
    A-2. Application/problems for assignment 1.
    1. 4- point FFT
    2. 4-point IFFT
    3. Cordic for Sin /Cos
    4. Cordic for Sin-1 x /Cos-1 x
    5. Non-Linear function e-2.5/Sin1.45/Cos3.1/Sinh2.5/cosh3.2/lognatural (Angles are in radians).
    6. Find Average of Floating Point Numbers in an Array of Size
    16/32/64/128 (Using a 4-Ssage FP-adder).

    Problem-set for algorithm implementation:


    Boolean algebraic formulations
    a. Covering algorithm- Brach & bound
    b. ROBDD computation
    c. Operation between ROBDDs: +, .
    Graph based optimization
    a. Two consideration each
    b. Two consideration each
    c. Graph coloring
    d. Clique partitioning
    e. Edge covering
    f. Vertex covering
    g. Independent set finding
    List scheduling
    a. Latency constrained resource minimization
    b. Resource constrained latency minimization
    c. Path based scheduling
    d. Pipelined datapath scheduling
    e. Hus multiprocessor scheduling
    Allocation & binding
    a. FU binding
    a. Coloring
    b. Clique finding
    c. Left edge based binding
    b. Storage unit binding
    a. Coloring
    b. Clique finding
    c. Left edge based binding
    c. Interconnect binding
    a. Coloring
    b. Clique finding
    c. edge based binding

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