Professional Documents
Culture Documents
Fault Testing of CMOS Integrated Circuits Using Signature Analysis Method
Fault Testing of CMOS Integrated Circuits Using Signature Analysis Method
Associate Professor, Department of Electronics Engineering, Pillai Institute of Information Technology, New Panvel,
Mumbai University
Lecturer, Department of Electronics Engineering, Pillai Institute of Information Technology, New Panvel, Mumbai
University
ABSTRACT
Moores law states that the number of transistors in integrated circuits doubles every 18 months. Increasing complexity of
digital system over the past decade has made it essential to increase the awareness of need of fault testing and diagnosis. With
the increase in complexity of the digital system, a test simulation along with diagnosis has become an important issue in VLSI
testing. In this paper, a signature analysis method is presented for testing of CMOS integrated circuits.
1. INTRODUCTION
There has been a continuous pressure on VLSI chip manufacturing industry to increase the manufacturing yield.
Integrated circuit manufacturers are constantly trying to decrease the number of faulty parts they produce. The
reliability of System-on-Chips must be ensured to a certain extent since a single fault is likely to make the whole chip
useless. Therefore, fault diagnosis and fault repairing techniques are gaining importance these days. A manufacturer
may be able to improve the circuit design or the manufacturing process by analyzing the parts that fail production tests
and determining the cause of failure for each part. Detection of fault and the type of fault present in a circuit is known
as fault diagnosis. With the growth of technology and advent of reconfigurable circuits like FPGAs, PLAs, PLDs etc.
testing only for faulty chip is not adequate [1]. Fault location may be required to identify and then replace or discard the
faulty sub-circuit. It can also be used to analyze the defect causing the faulty behavior. Fault diagnosis is executed upon
manufactured chips, which are found to be faulty in order to identify the position and types of the faults present in them
[2].
2.
HISTORICAL BACKGROUND
Current measurement based testing of electronics components has always been an integral part of the testing
since the birth of semiconductor industry. It is used to detect gross shorts and is generally referred to as static
IDD test. The present form of quiescent current (IDDQ) measurement based testing for CMOS VLSI, known as
IDDQ testing, was first publicly proposed in 1981 [1] and then formulated in [2] and [4] for the detection of
bridging faults. Around the same time, researchers at IBM also proposed the monitoring of switching current to
detect transient failures (noise related failures) in memory devices [5].
CORRECT
CIRCUIT
UNDER TEST
OUTPUT
RESPONSE
COMPARATOR
RESPONSE
TEST RESULT
Page 73
4. IDDQ TESTING
IDDQ testing refers to the integrated circuit (IC) testing method based upon measurement of steady state powersupply current. IDDQ stands for quiescent power-supply current. Today, the majority of ICs are manufactured
using complementary metaloxidesemiconductor (CMOS) technology. In steady state, when all switching
transients are settled-down, a CMOS circuit dissipates almost zero static current. The leakage current in a
defect-free CMOS circuit is negligible (on the order of few nano amperes). However, in case of a defect such as
gate-oxide short or short between two metal lines, a conduction path from power-supply (VDD) to ground
(GND) is formed and subsequently the circuit dissipates significantly high current. This faulty current is a few
orders of magnitude higher than the fault-free leakage current. Thus, by monitoring the power-supply current,
one may distinguish between faulty and fault-free circuit [3].
The steady state or quiescent current (IDDQ) testing of CMOS integrated circuits is known to be very efficient
for improving test quality [8]. The test methodology based on the observation of the quiescent current on power
supply lines allows a good coverage of physical defects such as gate-oxide shorts, floating gates and bridging
faults. These defects are neither well modelled by the classical fault models, nor detectable by conventional
logic tests. In addition, IDDQ testing can be used as a reliability predictor due to its ability to detect defects that
do not yet involve faulty circuit behaviour, but could be transformed into functional failures at an early stage of
circuit life. Thus, IDDQ testing became a powerful complement to the conventional logic testing. Under the fault
conditions, the normal values of IDDQ may be increased, decreased or generally distorted. Thus, fault detection
can be accomplished by monitoring the Iddq current fluctuations using a current sensing circuit. In report, a
simple built-in current sensor (BICS) is presented, which provides a digital output for supply current
monitoring and testing in circuits. BICS is inserted in series with the power supply or the ground of the Circuit
under test (CUT) to detect abnormal IDDQ current in the integrated circuit [6] as shown in Figure 2.
Page 74
Page 75
Figure 6 Signature of the faulty inverter IC (Length of channel is less than the normal)
Page 76
Figure 7 Signature of the faulty inverter IC (Length of channel is larger than the normal)
Page 77
Figure 10 Signature of the faulty inverter IC (Stuck-at-0 fault at the gate of PMOS)
Page 78
Figure 11 Signature of the faulty inverter IC (Stuck-at-0 fault at the gate of NMOS)
Figure 12 Signature of the faulty inverter IC (Stuck-at-1 fault at the gate of PMOS)
Page 79
Figure 13 Signature of the faulty inverter IC (Stuck-at-1 fault at the gate of NMOS)
Figure 14 Circuit for comparing the signature of the fault free IC and IC under test
Figure 5 shows the signature of the fault free inverter IC. In this signature, it can be seen that when the input is given
to the inverter, the capacitor C starts discharging through it. In this figure, for fault free circuit voltage across capacitor
and output of inverter is shown. Figure 6 to 13 show the responses of the inverter IC with different faults. These faults
occur when the length or width of the channel of the transistors is varied or in the presence of stuck-at faults at various
Page 80
5. CONCLUSION
A new method for signature analysis has been described. This method provides a robust and flexible way to implement
signature analysis. The most powerful aspect of this method is the ability to implement it for single failures, making it
useful for field returns, qualification failures. Another important benefit of this method is the ability to use a low degree
of belief with any number of signatures that are not well known or rely entirely on expert opinion. This method
obviously requires a standard set of failure mechanisms as well as a standard set of terms and definitions for failure
analysis. This SA method has the ability to be incorporated into an automated IC diagnosis process that uses defect
models and classes for site localization in addition to failure mechanism determination. Improved models and diagnosis
procedures will help reduce the amount of testing and physical failure analysis necessary to determine a signature for
the failure mechanism and its location.
References
[1] Groza, V.; Abielmona, R.; Assaf, M.H.; Elbadri, M.; El-Kadri, M.; Khalaf, A.; A Self-Reconfigurable Platform
for Built-In Self-Test Applications, Instrumentation and Measurement, IEEE Transactions on , vol.56, no.4,
pp.1307-1315, Aug. 2007.
[2] M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press,
1995.
[3] Rochit Rajsuman, Iddq Testing for CMOS VLSI, PROCEEDINGS OF THE IEEE, VOL. 88, NO. 4, APRIL
2000.
[4] J. M. Acken, Testing for bridging faults (shorts) in CMOS circuits, in Design Auto. Conf., 1983, pp. 717718.
[5] R. Y. Li, S. C. Diehl, and S. Harrison, Power supply noise testing of VLSI chips, in Int. Test Conf., 1983, pp.
366369
[6] D. Baschiera and B. Courtois, Testing CMOS: A challenge, in VLSI Design, Oct. 1984, pp. 5862.
[7] C. F. Hawkins and J. Soden, Electrical characteristics and testing for gate oxide shorts in CMOS ICs, in Int. Test
Conf., 1985, pp. 544555
[8] E. I. Muehldorf, A quality measure for LSI components, IEEE J. Solid State Circuits, pp. 291297, Oct. 1974.
[9] R. L. Wadsack, Fault modeling and logic simulation of CMOS and MOS integrated circuits, Bell Syst. Tech. J.,
pp. 14491488, MayJune 1978.
[10] J. Shen, W. Maly, and F. Ferguson, Systematic characterization of physical defects for fault analysis of MOS IC
cells, in Int. Test Conf., 1984, pp. 390399.
[11] H.Walker and S. Director, VLASIC: A catastrophic fault yield simulator for integrated circuits, IEEE Trans.
Computer-Aided Design, pp. 114130, Jan. 1986.
[12] M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press,
1995.
[13] Bob Duell, Iddq made easy CMOS Iddq test methodology Fundamental concepts, System Science, Inc., Revised
edition,1997.
[14] J.M. Soden, C.F. Hawkins, R.K. Gulati and W. Mao IDDQ testing: a review, Journal of Electronic Testing:
Theory And Applications, vol.3, 1992, pp. 291- 303.
[15] S.D McEuen, Reliability benefits of IDDQ, J. of Electronic Testing: Theory and Application, Vol.3, 1992, pp904-910.
[16] J.A. Segura, V.H. Champac, R.R. Montanes, J. Figueras and J.A. Rubio, Quiescent current analysis and
experimentation of defective CMOS circuits, J. of Electronic Testing: Theory and Applications, Vol.3, 1992, pp.
337-346.
[17] P. Nigh, W. Maly, Test generation for current testing, IEEE Design and Test of Computers, Feb.1990, pp.26-38.
[18] S.D McEuen, Reliability benefits of IDDQ, J. of Electronic Testing: Theory and Application, Vol.3, 1992, pp904-910.
[19] K.J. Lee and J.J. Tang, A built-in current sensor based on current-mode design, IEEE Transactions on Circuits
and Systems-II Analog and Digital Signal Processing, Vol. 45, No. 1, Jan.1998, pp. 133-137.
[20] T.L. Shen, J. C. Daly, and J. C. Lo, On Chip current sensing circuit for CMOS VLSI, Proc. IEEE VLSI Test
Symposium paper 16.2, 1992, pp. 309-314.
[21] Christopher L. Henderson and Jerry M. Soden, A Signature Analysis Method for IC Failure Analysis,
International Symposium for Testing and Failure Analysis, Nov. 18-22. I996.
Page 81
Page 82