IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO.
2, MARCH/APRIL 2020
A Generalized Switch Fault Diagnosis for Cascaded
H-Bridge Multilevel Inverters Using Mean
Voltage Prediction
Anjali Anand , Member, IEEE, Akhil Vinayak B , Student Member, IEEE, Nithin Raj , Member, IEEE,
Jagadanand G, Member, IEEE, and Saly George , Member, IEEE
Abstract—A cascaded H-bridge multilevel inverter is an in-
dispensable part of high-power industrial drives. The multilevel
inverters have an increased chance of switch fault as a conse-
quence of a considerably large number of semiconductor switches
associated in the power conversion. A quick and precise fault
detection–isolation strategy improves the system reliability as well
as reduces the shutdown time of the drive. This article presents
a novel generalized open-switch fault-diagnostic approach for an
N -level cascaded H-bridge multilevel inverter. In this detection
technique, half-cycle mean values of bridge voltages, which are
calculated for positive and negative half cycles individually, are
used as fault identification features. These means under open-
switch fault are predicted from the reference half-cycle means and
compared with those measured values to locate the open-switch
fault. This quick detection scheme can identify the faulty switch
within one fundamental period of output voltage for the cascaded
inverters having different number of voltage levels. The computa-
tion requirement is minimum, since this approach does not need
complex calculations or domain transformations. This strategy
can efficiently locate the faulty switch of the cascaded inverter
working with various level-shifted pulsewidth modulation schemes,
different loading conditions, modulation indexes, and switching
frequencies. The potency of the fault classification algorithm is
verified through simulation and experimentation.
Index Terms—Cascaded H-bridge multilevel inverter (CHB
MLI), fault detection, half-cycle mean voltage (HCMV), level-
shifted pulse width modulation (LS PWM), open-switch fault.
I. INTRODUCTION
ULTILEVEL inverters (MLIs) have now become
M a favorite choice in high-power dc–ac conversion
Manuscript received June 5, 2019; revised September 1, 2019 and October
22, 2019; accepted November 18, 2019. Date of publication December 12,
2019; date of current version March 17, 2020. Paper 2019-IPCC-0618.R2,
presented at the 2018 IEEE Power Electronics, Drives and Energy Systems
Conference, Chennai, India, Dec. 18–21, and approved for publication in the
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power
Converter Committee of the IEEE Industry Applications Society. This work
was supported by Technical Enhancement of R&D and Institutional Consul-
tancy Activities of TEQIP phase II at National Institute of Technology Calicut
(NITC/TEQIP-II/R&D/2014 dated 16-08-2016). (Corresponding author: Anjali
Anand.)
A. Anand, A. Vinayak B, Jagadanand G, and S. George are with the De-
partment of Electrical Engineering, National Institute of Technology Calicut,
Kozhikode 673601, India (e-mail: anjalianandk89@gmail.com; vinayakakhil@
gmail.com; jagadanand@nitc.ac.in; saly@nitc.ac.in).
N. Raj was with the Department of Electrical Engineering, National Institute
of Technology Calicut, Kozhikode 673601, India. He is now with L&T Tech-
nology Services, Bangalore 560001, India (e-mail: nithinrmu@gmail.com).
Color versions of one or more of the figures in this article are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2019.2959540
0093-9994 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
1563
systems owing to their high-quality voltage output using
switches having lesser ratings. A cascaded H-bridge (CHB)
MLI, which is popular among MLIs, is a prospective component
in high-power medium-voltage industrial and large automotive
drives due to its modularity and fault ride-through capabil-
ity [1]. Since MLIs incorporate a large number of semicon-
ductor switches to derive high-quality output power, the cen-
tral dilemma with them is the elevated probability of switch
failure [2], and it was reported that these switch faults are
responsible for nearly one-third of total failures in converter
systems [3]. The switch faults, in general, can be classified
as open-switch fault (OSF) and short-switch fault (SSF). The
former one does not always lead to the complete halt of the
drive, and not so critical as SSF, mostly these faults remain in
the system undetected for a long time and may cause secondary
faults and complete shutdown of the system [4]. The downtime of
crucial drive systems must be avoided to improve plant reliability
and to minimize the maintenance and production cost. Hence, a
dedicated switch fault diagnostic system, which can quickly and
efficiently identify the location of switch fault, is a mandatory
element in MLI-fed drives [3]. This fault detection system
can assure continuous functioning of the drive by avoiding the
unwanted operating conditions, which arise due to the presence
of switch faults.
Many techniques for condition monitoring and switch fault
classification of MLI have been proposed in recent years.
Different classifier algorithms, heuristic methods, and statisti-
cal feature optimization techniques, which are developed for
other applications, were utilized for switch fault detection in
the CHB MLI [5]–[9]. These methods have larger compu-
tational complexity and need intensive training requirements
for the classifier, which leads to larger detection time. The
hardware implementation of these schemes demands advanced
processors. In [9], an OSF diagnosis in the CHB MLI us-
ing fast Fourier transform–principal component rearrangement–
backpropagation neural network is suggested. This scheme re-
quires nearly two fundamental periods to detect the fault due to
its intensive computation steps involving complex matrix oper-
ations. An artificial-neural-network-based detection scheme for
an asymmetric CHB MLI using the output voltage is discussed
in [10]. This method is not suitable for the symmetric CHB MLI,
since it fails to accurately separate the location of the OSF within
a bridge for the symmetric inverter.
1564
A fault detection scheme based on frequency-domain anal-
ysis, which can discriminate between faults and transients, is
proposed in [11]. However, this method needs a dedicated
complex filtering circuit, and the phase angle oscillations at a
higher number of output voltage levels decline the efficiency of
the classifier. In [12], an OSF detection scheme for the CHB
MLI with asymmetric zero-voltage switching using the slope of
fault current is presented. This method, which is only applicable
to the CHB MLI with rotating carrier pulsewidth modulation
(PWM), needs m cycles to detect the OSF in an inverter with m
number of H-bridges. The diagnostic strategy suggested in [13]
uses an instantaneous voltage error for fault identification, and
classification is done by modifying the switching sequences.
This method needs the status of switching states, as well as
current directions, for the classification, and fault verification
is necessary to confirm the fault position. The OSF detection
strategies with bridge voltages as input parameters are proposed
for the CHB MLI in [14] and [15]. The faulty switch in a
five-level CHB MLI working with the modified phase dispo-
sition (PD) PWM scheme is identified in [14] by the variation
in measured normalized half-cycle mean values. The scheme
suggested in [15] uses mean voltages for fault identification and
is verified only for the CHB MLI working with PD PWM.
A fault diagnosis scheme for the OSF in insulated-gate bipolar
transistors (IGBTs) and clamping diodes of a neutral point
clamped (NPC) MLI is suggested in [16]. This approach requires
reactive power injection for fault classification in switches;
hence, it can be applied for grid-connected systems. A diag-
nostic scheme based on variations in neutral point current of
a T-type MLI is proposed in [17], which requires lookup table
and status of the current switching state for fault classification. A
fault-tolerant scheme for a flying capacitor (FC) MLI is proposed
in [18], where the knowledge about the charging state of the ca-
pacitor and switching states is utilized for fault localization. The
OSF detection in IGBTs of a fault-tolerant hybrid FC-NPC con-
verter is addressed in [19], and this strategy uses a logic-based
detection module with phase voltage as input. Two detection
methods for the OSF in clamping diodes of the NPC MLI are
proposed in [20]. As the number of levels of output voltage
increases, the fault feature extraction becomes difficult due to
short conduction time of each diode. In [21], the rate of change
of current residual is utilized to achieve the OSF detection in the
NPC MLI. A fuzzy-based fault classifier is suggested in [22]
for the OSF in the voltage-source-inverter-fed PMSM drive
has a longer detection time. Even though different approaches
in [16]–[22] are developed for other MLI topologies, they cannot
be directly applied to detect the OSF in the CHB MLI.
In this article, a quick and efficient OSF detection scheme
with minimum computational requirements is proposed for an
N -level CHB MLI. This generalized OSF diagnosis approach is
valid for an N -level symmetric CHB MLI controlled by various
PWM schemes with unequal dc source utilization, including
level-shifted PWM (LS PWM). This method can detect the fault
within one fundamental period of output voltage using half-cycle
mean voltages (HCMVs), which has been derived from bridge
output voltages. The validity of the proposed detection strategy
is tested through simulation and verified with experimentation
on the CHB MLI working with LS PWM schemes for different
Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 2, MARCH/APRIL 2020
Fig. 1. Single leg of a three-phase N -level CHB MLI with m H-bridges.
number of levels at output voltage under various operating
conditions. This scheme can locate multiple OSFs at different
bridges. The identification of the OSF location is the first step for
the fault-tolerant operation of the inverter-fed drive, and then,
the resilient functioning of the drive can be ensured by suitable
modification of the PWM strategy without using any redundant
switches. The proposed scheme initiates this fault ride-through
operation of the inverter under the fault condition with the fast
identification of the faulty switch.
II. CASCADED H-BRIDGE MULTILEVEL INVERTER
A. System Description
The CHB MLI is constituted by a series combination of
H-bridges and low-voltage input dc sources. The switches are
controlled by various multilevel PWM schemes to generate a
stepped output voltage with lesser total harmonic distortion.
Fig. 1 shows a single leg of a general three-phase N -level CHB
MLI with m H-bridge cells at each phase. An xth H-bridge HB-x
is constituted by two complementary switch pairs, Spx1 /Spx3
and Spx2 /Spx4 , where x and p denote the order of the H-bridge
and the phase of the inverter, respectively. Vp indicates the
phase output voltage, and V1 , V2 , . . . , Vx , . . . , Vm are the bridge
voltages of HB-1 to HB-m, respectively. Here, a symmetric
CHB MLI with input dc sources having equal magnitude Vdc
is considered.
Commonly used carrier-based PWM schemes for MLIs are
LS PWM and phase-shifted PWM (PS PWM). The advantages
of LS PWM over PS PWM are lower input current and output
voltage distortions. The various classes of LS PWM schemes
include PD PWM, phase opposite disposition (POD) PWM,
and alternate phase opposite disposition (APOD) PWM. These
control strategies generate slightly different output waveforms,
which reflect as a variation in their harmonic spectra. In this
article, IGBTs of the CHB MLI are controlled by LS PWM
schemes, and the switching states used to obtain different levels
of output voltage are listed in Table I. The input source utilization
is not equal for inverter employing LS PWM, and HB-x conducts
for more duration than HB-(x − 1).
ANAND et al.: GENERALIZED SWITCH FAULT DIAGNOSIS FOR CASCADED H-BRIDGE MLIs USING MEAN VOLTAGE PREDICTION 1565

TABLE I
SWITCHING STATES FOR FIVE-, SEVEN-, AND NINE-LEVEL CASCADED INVERTERS

B. Cascaded Inverter Under OSF

The primary sources of failure in an inverter are semicon-
ductor switches and their drive systems [23]. Since N -level
multilevel works with 2 (N − 1) controllable switches, the prob-
ability of switch fault is boosted in these inverters. The frequency
of occurrence of the OSF in these inverters is significantly
higher than other defects, even though it is less than that of
the SSF. Most of the drive systems have in-built SSF detection
facilities due to the highly detrimental consequences of this fault,
and ultrafast isolation of the SSF is included in present-day
drive systems. The OSF may emerge in a converter system
because of opened IGBTs or diodes, gate driver malfunction,
gate–controller circuit failure, temperature stresses, and ruptures
due to short circuits [15]. Load–torque oscillations, derating in
output power of the drive, and overloading of other switches are
some of immediate consequences of open fault. The OSF in the
inverter will be usually unrecognized by fuses or conventional
relay protection schemes. This fault results in additional stresses
for other healthy switches [10], and eventually, the OSF leads
to the development of a short-circuit fault in other switches due
to power cycling. Open faults are barely diagnosed in real time;
hence, commonly, they lead to secondary faults. Hence, it is
recommended to integrate a dedicated diagnostic strategy for the
OSF in control systems associated with the critical inverter-fed
drives. In this article, the single-switch OSF due to gate driver
failure, which is the most common type of OSF in converters
[24], is considered. The OSF is created in a three-phase CHB
MLI by disabling the corresponding gate pulse. The output
voltages of R-phase in a seven-level CHB MLI working with
PD PWM and having an load of R = 200 Ω and L = 20 mH for
all possible single OSF conditions are demonstrated in Figs. 2
and 3. A modulation index (MI) of unity and carrier switching
frequency (fs ) of 2 kHz are considered for the experimentation.
The no-fault bridge voltages and output phase voltage are given
in Fig. 2(a). In Fig. 3, the OSF at switches of diagonal positions
in HB-3 results in a similar pattern for the bridge voltage V3 ,
whereas the OSF in other bridges creates a distinct distortion for
the corresponding bridge voltage, as shown in Fig. 2. The same
observation is valid for the CHB MLI working with POD and Fig. 2. Voltages and current of a three-phase seven-level CHB MLI under
(a) no-fault condition and OSF at (b) SR11 , (c) SR12 , (d) SR13 , (e) SR14 ,
APOD PWM schemes. These voltage patterns can be utilized (f) SR21 , (g) SR22 , (h) SR23 , and (i) SR24 .
for the identification of a faulty switch.

Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
1566
Fig. 3. Voltages and current of a seven-level CHB MLI under the OSF at
(a) SR31 , (b) SR32 , (c) SR33 , and (d) SR34 .
III. PROPOSED OSF DIAGNOSIS SCHEME
The proposed OSF diagnosis scheme is based on waveform
distortions appearing in the output voltage under the OSF. The
OSF at upper switches (Spx1 /Spx2 ) results in clipping of the
bridge voltage for the corresponding conducting half cycle. The
OSF at a lower switch Spx4 reflects as a negative dc offset in
Vx for a positive half cycle, while an opened Spx3 produces
a positive dc offset in Vx during a negative half cycle. These
distortions, which are less dependent on load variations, are
quantified using mean values and utilized to locate the faulty
switch within a bridge [15].
In the proposed detection scheme, the mean values of the
measured bridge voltages are calculated for positive and negative
half cycles, and these HCMV values are selected as the fault
detection feature. Under the presence of OSF in a bridge, HCMV
values of voltage across the corresponding bridge alone change,
and these variations are unique for a particular switch. The
output voltages across H-bridges (Vx ) are taken for analysis,
and HCMVs are calculated for positive and negative half cycles,
respectively, as MxP and MxN using

n Mx(ref)c = A(MI)2 + B(MI) + C × Vdc .
MxP = Vx [i]
i=1

2n
MxN = Vx [i]
i=n+1
where x ∈ 1, 2, . . . , m, and 2n is the total number of samples
in one cycle of acquired bridge voltages.
MxP and MxN , which are calculated from the acquired bridge
voltages during normal operation of the CHB MLI, are consid-
ered as the reference HCMVs and are denoted as MxP (ref) and
MxN (ref) , respectively. These reference means are the functions
of the selected MI, input dc voltage, and the number of output
voltage levels of the CHB MLI. Usually, MxN (ref) = −MxP (ref) ;
hence, a single value of the HCMV is sufficient for a bridge
Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 2, MARCH/APRIL 2020
TABLE II
COEFFICIENTS FOR HCMV REFERENCE CALCULATION
TABLE III
COMPARISON OF MEASURED AND PREDETERMINED REFERENCE HCMV
VALUES FOR A FIVE-LEVEL CHB MLI AT VARIOUS MIS
under normal (no-fault) operations. This single reference mean
is denoted as Mx(ref) and Mx(ref) = |MxP (ref) | = |MxN (ref) |.
In an N -level CHB MLI, Mx(ref) values for different bridges
can be predetermined using (3) for various numbers of levels in
output voltages, and these predicted values are represented as
Mx(ref)c . The coefficients (A, B, C, and D) in (3) are valid for
all operating condition of the CHB MLI, and their magnitudes
are listed in Table II
 
(3)
(1)
Equation (3) is derived through curve-fitting methods using
simulation and hardware data under different MIs after nor-
malizing with input dc source voltage. Mx(ref)c values in (3)
(2)
are calculated for a particular dc input Vdc , which is a design
parameter of the inverter. The input data used for curve fitting
and the testing data used for verification are given in Table III.
The coefficients for the five-level inverter in Table II are derived
using this data input, and the calculated reference mean values
are compared with the input data. The error between calculated
and measured reference HCMV values for HB-1 and HB-2 are
denoted as δM1 and δM2 , respectively. These are quite small
indicating the accuracy of (3) for a five-level CHB MLI under
various MIs. The predetermined reference means using (3) and
the measured reference HCMVs for a nine-level CHB MLI
ANAND et al.: GENERALIZED SWITCH FAULT DIAGNOSIS FOR CASCADED H-BRIDGE MLIs USING MEAN VOLTAGE PREDICTION 1567

TABLE IV
COMPARISON OF MEASURED AND PREDETERMINED REFERENCE HCMV VALUES FOR A NINE-LEVEL CHB MLI AT VARIOUS MIS

Fig. 4. HCMVs under a healthy operation of the CHB MLI with various levels
of output voltage (MI = 1, fs = 10 kHz, load R = 100 Ω, and L = 20 mH).
Fig. 5. Schematic diagram of opened switches and affected HCMV of an
N -level CHB MLI.

are given in Table IV. The comparison of values from this TABLE V
table shows that the error between these reference values is AFFECTED OUTPUT VOLTAGE LEVELS UNDER OSF AT Spx1 /Spx4 FOR AN
negligible for a nine-level CHB MLI with different MIs. Mx(ref) N -LEVEL CHB MLI WITH m BRIDGES
and Mx(ref)c are plotted in Fig. 4 for a different number of
output voltage levels, and these values are found to be in close
correlation. Since bridge voltages are independent of loading of
the inverter under healthy condition, the reference values will not
change with the variation in the applied load. Hence, Mx(ref)c
are valid for different loading conditions of the CHB MLI. These
predicted HCMV references are independent of fs used for the
inverter.
A three-phase N -level symmetric CHB MLI with input dc
sources of magnitude Vdc generates the rated output voltage
under unity MI. When the magnitude of dc sources is varied to
Vdc1 , the new reference HCMV values, Mx(ref)c1 , can be derived the HCMV value (MaP or MaN ) under the OSF is zero for a
from Mx(ref)c values using pair of switches in this particular bridge. Hence, for this bridge,
Vdc1 the switch fault position can only be identified as pairs, i.e.,
Mx(ref)c1 = Mx(ref)c × . (4) Spa1 /Spa4 and Spa2 /Spa3 . For a CHB MLI controlled by the
Vdc
switching states as in Table I, the mth bridge (HB-m) has the
In a general CHB MLI working with LS PWM, the input maximum dc source utilization, i.e., a = m. The OSF at lower
source utilization is unequal, and the bridge with highest conduc- switches Spx4 or Spx3 (x = a) reflects as a change in magnitude
tion time (or dc source power utilization) under normal operation and sign of MxP and MxN , respectively. The schematic diagram
is denoted as HB-a in this article. Under normal operation, MxP of the failed switches and the corresponding affected HCMV
and MxN are positive and negative values, respectively. The values is shown in Fig. 5. The switches that conduct for a positive
OSF at upper switches Spx1 or Spx2 of HB-x in an N -level half cycle are marked in red, and those conduct in a negative half
CHB MLI is indicated by a nearly zero value for MxP and cycle are drawn in blue.
MxN , respectively. The OSF at HB-a results in a similar output Table V shows the affected output voltage levels when a
voltage pattern for the diagonally opposite switch positions, and particular switch, which conducts for a positive half-cycle,

Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
1568 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 2, MARCH/APRIL 2020

fails. The detailed analysis indicates that for the mth H-bridge,
which has the maximum conduction time, the OSF at Spm1 and
Spm4 affects similarly except that the OSF at Spm4 produces
an additional distortion at 0Vdc . The distortion at zero voltage
will not be visible in the output bridge voltage. Hence, the OSF
at Spm1 and Spm4 results in similar distortions at the bridge
voltage Vm . Except this bridge, bridge voltages under the OSF
at all other positive conducting switches are visibly different.
This observation can be justified with in Figs. 2 and 3. A faulty
switch is located accurately for the remaining bridges from HB-1
to HB-(m-1), while the opened switch in HB-m is detected as
pairs.
The value of affected HCMV (MxP and MxN ) under OSF
at lower switches for HB-x can be predetermined from the no-
fault HCMV values, and these predicted HCMV under OSF
for positive and negative half cycles are denoted as MxP,e , and
MxN,e , respectively,
MxP,e = MxP (ref) − MaP (ref) (5)
MxN,e = MxN (ref) − MaN (ref) (6)
where MaP (ref) and MaN (ref) are HCMVs under normal op-
eration of HB-a. MxP (ref) and MxN (ref) can be replaced by
Mx(ref)c and -Mx(ref)c , respectively, without compromising the
detection accuracy, since the error between Mx(ref)c and Mx(ref)
is negligibly small.
The proposed detection strategy is detailed as a flowchart
in Fig. 6. MxP and MxN are calculated from measured
bridge voltages of the CHB MLI, and these values are equal
to the corresponding references MxP (ref) (or Mx(ref)c ) and
MxN (ref) (or −Mx(ref)c ), respectively, under normal operation.
A nearly zero value of the HCMV is expected for OSF at upper
switches; hence, a comparison between the normalized mea-
sured HCMV (MxP % /MxN % ) in percentage and the low-value
threshold (Mth ) is used for fault identification in upper switches.
The OSF at Spx1 (Spx2 ) is indicated by MxP % (MxN % ) value,
which is less than Mth .
The fault at Spm4 /Spm3 is identified when MmP % /MmN % is
smaller than Mth . The error between expected and measured
HCMVs under the OSF is determined for locating the fault
at lower switches with x = 1, 2, 3, . . .(m − 1). This error for
the positive and negative half cycles is calculated as δMxP Fig. 6. Proposed fault diagnosis strategy for an N -level CHB MLI.
and δMxN , respectively, using (7) and (8). δMxP and δMxN
are compared with a threshold value (δMth ) to identify the
fault at Spx3 and Spx4 respectively. When δMxP (δMxN ) is IV. RESULTS AND DISCUSSION
less than δMth , an OSF at Spx4 (Spx3 ) is detected. δMth is
A three-phase CHB MLI with a different number of levels
usually smaller than Mth , since the error between predicted and
at the output voltage, which is controlled by LS PWM control
measured HCMV values is negligibly small. The OSF can be
schemes, is considered for the analysis. The OSF is introduced to
traced up to the individual switch in all bridges using HCMV
the system by disabling the gate pulses, and the dc input voltage
except for a single-bridge HB-a, where the fault positions are
is kept constant at a magnitude, which generates the rated phase
identified as pairs of switches
voltage of 230 Vrms at the output of a healthy N -level CHB MLI
δMxP = MxP,e − MxP (7) under unity MI. The behavior of five-, seven-, and nine-level
CHB MLIs with various RL loads working under different MIs
δMxN = MxN,e − MxN (8)
with the OSF is studied with simulation and experimentation.
where MxP,e and MxN,e are the predicted HCMVs from ref- The experimental setup of a three-phase CHB MLI used in this
erence values, and MxP and MxN are the calculated HCMVs article is shown in Fig. 7. The inverter is controlled using field-
from the real-time acquisition of bridge voltages under the OSF. programmable gate array (FPGA) XC6SLX25, and H-bridges

Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
ANAND et al.: GENERALIZED SWITCH FAULT DIAGNOSIS FOR CASCADED H-BRIDGE MLIs USING MEAN VOLTAGE PREDICTION 1569

Fig. 7. Hardware implementation of the three-phase CHB MLI.

Fig. 8. Output voltages and half-cycle pulse of a five-level CHB MLI under Fig. 9. HCMVs of the five-level CHB MLI with RL load (200 Ω and 50 mH)
healthy operation (MI = 0.8, fs = 2 kHz, load R = 200 Ω, and L = 5 mH and under the OSF from (a) simulation and (b) hardware (fs = 2 kHz, MI = 1, POD
PD PWM). PWM).

are realized by SKM50GB063D IGBT Modules with SKYPER

32 R driver. The bridge voltages are acquired using the LV-
25P transducer and the NI PCI-6251 data acquisition card. The
half-cycle voltages for different phases are obtained from the
acquired bridge voltages using half-cycle pulses, and HCMV
values are calculated under various operating conditions. The
half cycle pulses are derived from the reference sinusoidal wave
used in the PWM pulse generation. The synchronized half-cycle
pulses (VR(pulse) ) and output voltages of R-phase in a five-level
CHB MLI are shown in Fig. 8.
The HCMV value of a five-level CHB MLI under the OSF at
different switch positions in R-phase is given in Fig. 9 . These
Fig. 10. HCMVs of nine-level CHB MLI from simulation and experimentation
means were calculated from the bridge voltages under fault under OSF (MI = 1, fs = 2 kHz, load R = 100 Ω, and L = 20 mH, PD PWM).
conditions in simulation and plotted along with the HCMV value
computed from real-time voltages. A single value of HCMV is
affected by the OSF depending on the fault position, and this The proposed HCMV prediction method is checked with
particular mean can be used as a fault identifier. The simulation, simulation and verified using hardware results in a nine-level
as well as experimentation, follows the same deviation in the CHB MLI. In Fig. 10, HCMV values under the OSF are cal-
HCMV under the OSF. HB-2 is having the highest conduction culated from measured bridge voltages using (1) and (2), and
time in this five-level inverter, and the OSF at Sp21 or Sp24 plotted along predicted HCMV values determined using (5) and
generates a similar MxP value, as discussed in Section III. (6). The predetermined HCMVs from the reference voltages
HCMV values of a seven-level CHB MLI with various MI are in close range with the measured HCMV under the OSF,
under healthy and OSF conditions obtained from simulation and and the anticipated HCMVs are, hence, used for the real-time
hardware are tabulated in Tables VI and VII, respectively. The implementation. In Fig. 11, MxP (ref) under normal operation
minimum value of MI, which is applied to obtain seven levels and MxP under the OSF at SRx4 for a nine-level CHB MLI
at the output voltage of the inverter under consideration, is 0.67, with different MIs are plotted. M1P (ref) is sharply increasing
hence; 0.7 is selected as the minimum MI value for analysis in with increment in the MI, while M4P (ref) is nearly stable under
the seven-level CHB MLI. The MxP (ref)c values are calculated various MIs. M4P is not shown in Fig. 11, since this value is
using (3) and Table II. zero under the OSF at SR44 .

Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
1570 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 2, MARCH/APRIL 2020

TABLE VI
SIMULATION RESULTS: MEASURED AND EXPECTED HCMVS OF A SEVEN-LEVEL CHB MLI UNDER OSF (fs = 2 kHz, LOAD R = 100 Ω, AND
L = 20 mH, PD PWM)

TABLE VII
HARDWARE RESULTS: MEASURED AND EXPECTED HCMVS OF A SEVEN-LEVEL CHB MLI UNDER OSF (fs = 2 kHz, LOAD R = 100 Ω, AND
L = 20 mH, PD PWM)

The following observations can be derived from Figs. 9–11

and Tables VI and VII.
1) The dc source utilization in the CHB MLI with LS PWM is
unequal, and consequently, the magnitude of the HCMV
is different for various bridges under normal operation.
The highest HCMV at a particular MI under the no-fault
condition is for HB-m because of its highest conduction
time (or dc source utilization).
2) As the MI increases, the HCMV also increases for all
bridges during normal operation. This increment in ref-
erence means is more in bridges with lower conduction
time.
3) The lower bridges are utilized for less duration in one
Fig. 11. No-fault and measured HCMV of a nine-level CHB MLI under the
OSF at SRx4 for different MIs (fs = 10 kHz, load R = 100 Ω, and L = 20 mH, cycle of the voltage at lower MI, and as the MI increases,
PD PWM). this conduction time and means increase rapidly for these

Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
ANAND et al.: GENERALIZED SWITCH FAULT DIAGNOSIS FOR CASCADED H-BRIDGE MLIs USING MEAN VOLTAGE PREDICTION
Fig. 12. Variation of HCMVs with load inductance in a seven-level CHB MLI
under the OSF (MI = 1, fs = 2 kHz, and R load = 200 Ω, PD PWM).
TABLE VIII
HCMVS OF A NINE-LEVEL CHB MLI WITH DIFFERENT fs (MI = 1,
LOAD R = 100 Ω, AND L = 20 mH, POD PWM)
bridges. Hence, the change in the MI has a prominent role
in deciding MxP (ref) and MxN (ref) of lower bridges.
4) The dc input source of highest bridge HB-m is utilized
nearly full of its capacity even at low MI. As a result, the
change in means with the MI is marginal in higher bridges.
5) The error between measured and predetermined reference
means is negligible; hence, predicted means MxP,e and
MxN,e can be used as references in the proposed diag-
nostic scheme. This prediction avoids the measurement
of no-fault system voltages before the installation of the
detection algorithm.
6) MxP and MxN under fault have distinguishable magni-
tudes for the OSF at different switch positions; hence, the
diagnostic scheme can accurately locate the fault position.
7) MxP (MxN ) has nearly zero magnitude for fault at
Spx1 (Spx2 ) under various MIs.
8) The error between MxP (or MxN ) and MxP,e (or MxN,e )
is almost zero under the OSF. Therefore, the comparison
between the error and δMth reliably detects the faulty
switch.
The adaptability of the proposed diagnostic approach is exam-
ined under various operating conditions, including load variation
and fs variations. Fig. 12 shows the hardware results of a
seven-level CHB MLI under various load impedances, where a
constant resistive load with a variable inductance is considered.
The reference and affected HCMV values under the OSF remain
constant under these variations. Therefore, the fault detection
scheme can perform with adequate precision even under various
load conditions. Table VIII justifies the invariability of HCMV
Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
1571
Fig. 13. HCMVs of a five-level CHB MLI with different LS PWM schemes
from simulation and experimentation under (a) no-fault condition (Mx(ref) ) and
(b) OSF at HB-1 (M I = 1, fs = 2 kHz, load R = 200 Ω, and L = 45 mH).
Fig. 14. Hardware results of OSF detection in HB-1 of a five-level CHB MLI
with the OSF at (a) SR11 , (b) SR12 , (c) SR13 , and (d) SR14 (PD PWM, MI = 1,
fs = 2 kHz, load R = 100 Ω, and L = 20 mH).
values under different fs ; hence, the developed strategy can be
used for fault detection with profound accuracy in CHB MLI-fed
drives. The comparison of these MxP (ref) values with predicted
HCMV reference values of the nine-level CHB MLI given in
Fig. 4 shows the invariability of MxP (ref)c with change in fs .
The HCMVs from simulation and experimentation using
different LS PWM strategies (PD, POD, and APOD PWM) are
compared in Fig. 13. Here, no-fault and OSF operations of HB-1
are considered. The behavior of the CHB MLI is similar for
all conditions irrespective of the specific LS PWM. Therefore,
the proposed approach is a generalized OSF diagnostic scheme,
which can be applied to detect the faulty switch in an N -level
CHB MLI working with various LS PWM schemes as well as
control strategies with similar unequal dc source utilization.
The potency of the fault classifier is studied with experimen-
tation on a three-phase five-level CHB MLI with PD and POD
PWM. The output voltages of phase-R with the OSF applied at
different switch positions in HB-1 of this five-level CHB MLI
with PD PWM are given in Fig. 14. The detection of the OSF
1572 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 2, MARCH/APRIL 2020
Fig. 15. Hardware results of OSF detection. (a) SR14 of the nine-level CHB
MLI with PD PWM. (b) SR11 of the seven-level CHB MLI with POD PWM
(MI = 1, fs = 2 kHz, load R = 100 Ω, and L = 20 mH).
Fig. 16. Hardware results of OSF detection for SR24 in a five-level CHB MLI
with PD PWM (a) for light-load condition and (b) for a highly inductive load
(MI = 1, fs = 2 kHz, load R = 100 Ω, and L = 20 mH).
at SR14 for a nine-level CHB MLI and the OSF at SR11 for the
seven-level CHB MLI is represented in Fig. 15. The recognition
of a faulty switch is indicated by a positive going edge of the fault
identifier flag (Fi ), as in Figs. 14 and 15. Ti and Td designate the
instant of occurrence of fault and fault detection, respectively.
The detection time for the algorithm is Ti − Td , and the fault
classier system can determine the fault position within 12 ms
in all cases of fault at HB-1. The OSF at SR34 is also analyzed,
since the detection of a fault at this switch position includes
the maximum number of calculation steps for the system under
consideration, and the faulty switch was located after 12.5 ms.
The effectiveness of the classifier algorithm is studied under
light-load condition, as well as under low-power-factor loads.
The hardware results are given in Fig. 16, and under these
operating conditions, the fault position is identified within 16 ms.
Since the bridge voltages are used for the OSF diagnosis, the
single OSF at multiple bridges can be easily identified using
the same proposed algorithm. The hardware results of multiple
OSFs in a seven-level CHB MLI are given in Fig. 17. For
a seven-level inverter, as HB-3 is the bridge with maximum
conduction time, the fault at SR31 or SR34 is identified as a pair
SR31 /SR34 . In Fig. 17(a), OSFs at SR11 and SR31 are created
at instant Ti , and these multiple faults at different bridges are
identified simultaneously at Td after 14 ms. OSFs are introduced
at SR31 and SR11 at Ti1 and Ti2 , respectively, in Fig. 17(b) and
17(c), and these faulty switches are identified at Td1 and Td2 ,
respectively. The fault positions SR31 and SR11 are identified
with the positive going edge of the fault identifier flags Fi1 and
Fi2 , respectively. In Fig. 17(c), the fault at SR31 is cleared at Ti2 .
Fig. 17(d) shows the result under multiple OSFs at SR11 and SR12
of HB-1, and the detection algorithm efficiently classifies the
Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
Fig. 17. Hardware results of fault detection in a seven-level CHB MLI under
multiple OSFs at (a)–(c) SR11 and SR31 , (d) SR11 and SR12 , (e) SR11 , SR12 ,
and SR23 (MI = 1, fs = 2 kHz, load R = 100 Ω, and L = 40 mH, PD PWM).
multiple faults at upper switches within a bridge. A multiple fault
condition involving OSFs at SR11 , SR12 , and SR23 is considered
in Fig. 17(e). The faults at SR11 , SR12 , and SR23 are introduced
at Ti1 , Ti2 , and Ti3 , respectively. Here, fault flag for SR12 is not
shown due to the channel limitation of the four-channel digital
storage oscilloscope. Fig. 17 proves that multiple faults within
a bridge and at different bridges can also be identified using
the proposed diagnostic strategy, and the multiple OSFs are
identified within one fundamental period of the output voltage.
The essential features of an eminent fault diagnosis strategy
are economical implementation and operation, reliability, ac-
curacy, optimal detection time, adaptability to different operat-
ing conditions of the system, lesser computational complexity,
and easier hardware realization. The analysis proves that the
proposed classifier possess all these characteristics; hence, this
scheme is a superior switch fault-diagnostic strategy for the
CHB MLI than the existing systems. The diagnostic approaches
presented in literature [5]–[11] need input data processing tools,
like discrete Fourier transform and principal component anal-
ysis, and use heuristic methods to locate the fault positions.
The training of these fault classifiers is time-consuming, and
a large amount of training and testing data are required as N
increases. The detection methods addressed in [4], [6], [9], and
[11] are not capable of locating the individual faulty switch.
The techniques in [4], [5], [7], [9], and [12] require more than
one cycle to locate the OSF positions, and effectiveness of the
detection algorithm under various operating conditions has not
been validated for these methods. In general, for an N -level CHB
ANAND et al.: GENERALIZED SWITCH FAULT DIAGNOSIS FOR CASCADED H-BRIDGE MLIs USING MEAN VOLTAGE PREDICTION
MLI, the proposed generalized fault diagnosis will be completed
within one fundamental period (T ) of the output voltage under
different operating conditions. The fault identification time for
different levels of the CHB MLI is almost same due to the lesser
steps involved in the algorithm to extract the fault feature.
V. CONCLUSION
A generalized OSF diagnosis scheme, which can be employed
for CHB MLI working with LS PWM schemes for any N -levels,
is proposed. This method suggests use of the HCMV of bridge
voltages as a fault identification feature, and these mean values
of the CHB MLI under OSF condition are predicted using no-
fault mean values. The error between the predicated mean and
real-time HCMVs is compared with a threshold value to locate
the fault position accurately. The competence of the algorithm
is validated with simulation and experimentation on the CHB
MLI for a different number output voltage levels under various
MIs, fs , PWM schemes, and load variations.
The proposed scheme provides an extensive improvement
over the existing methods. The real-time implementation of the
fault classifier can be realized with a very basic processor or
microcontroller due to computational simplicity. This scheme
does not involve any domain transformations or lookup tables.
This strategy can be applied to MLIs working with different
PWM schemes having unequal dc source utilization, and fault
classification is independent of the number of levels at the output
voltage in the CHB MLI. The proposed approach quickly detects
the faulty switch with a detection time less than one fundamental
period of output voltage, and the reliable OSF detection is
possible under different operating conditions of the CHB MLI,
including variations in MI, fs , load, and dc input voltage. This
method can be generalized to obtain a PWM-independent fault
detection technique in various MLIs.
REFERENCES
[1] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, “A survey
on cascaded multilevel inverters,” IEEE Trans. Ind. Electron., vol. 57,
no. 7, pp. 2197–2206, Jul. 2010.
[2] C. Cecati, A. O. Di Tommaso, F. Genduso, R. Miceli, and G. R. Galluzzo,
“Comprehensive modeling and experimental testing of fault detection
and management of a nonredundant fault-tolerant VSI,” IEEE Trans. Ind.
Electron., vol. 62, no. 6, pp. 3945–3954, Jun. 2015.
[3] U. Choi, F. Blaabjerg, and K. Lee, “Study and handling methods of power
IGBT module failures in power electronic converter systems,” IEEE Trans.
Power Electron., vol. 30, no. 5, pp. 2517–2533, May 2015.
[4] N. Raj, A. Anand, A. Riyas, J. G, and S. George, “A novel open-transistor
fault detection method in symmetric cascaded H-bridge multilevel in-
verter,” in Proc. IEEE Int. Conf. Power Electron., Drives Energy Syst.,
Dec. 2016, pp. 1–6.
[5] S. Khomfoi and L. M. Tolbert, “Fault diagnosis and reconfiguration for
multilevel inverter drive using AI-based techniques,” IEEE Trans. Ind.
Electron., vol. 54, no. 6, pp. 2954–2968, Dec. 2007.
[6] W. Jiang, C. Wang, Y.-p. Li, and M. Wang, “Fault detection and remedy
of multilevel inverter based on BP neural network,” in Proc. Asia-Pacific
Power Energy Eng. Conf., Mar. 2012, pp. 1–4.
[7] X. Hao, Z. Jian, Q. Jie, W. Tianzhen, and H. Jingang, “RPCA-SVM fault
diagnosis strategy of cascaded H-bridge multilevel inverters,” in Proc. 1st
Int. Conf. Green Energy, Mar. 2014, pp. 164–169.
[8] T. Wang, H. Xu, J. Han, E. Elbouchikhi, and M. El Hachemi Benbouzid,
“Cascaded H-bridge multilevel inverter system fault diagnosis using a PCA
and multiclass relevance vector machine approach,” IEEE Trans. Power
Electron., vol. 30, no. 12, pp. 7006–7018, Dec. 2015.
Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
1573
[9] Z. Liu, T. Wang, T. Tang, and Y. Wang, “A principal components rear-
rangement method for feature representation and its application to the
fault diagnosis of CHMI,” Energies, vol. 10, no. 9, 2017, Art. no. 1273.
[10] N. Raj et al., “Switch fault detection and diagnosis in space vector mod-
ulated cascaded H-bridge multilevel inverter,” Int. J. Electron., vol. 105,
no. 12, pp. 1977–1992, 2018.
[11] P. Lezana, R. Aguilera, and J. Rodriguez, “Fault detection on multicell
converter based on output voltage frequency analysis,” IEEE Trans. Ind.
Electron., vol. 56, no. 6, pp. 2275–2283, Jun. 2009.
[12] H. W. Sim, J. S. Lee, and K. B. Lee, “Detecting open-switch faults: Using
asymmetric zero-voltage switching states,” IEEE Ind. Appl. Mag., vol. 22,
no. 2, pp. 27–37, Mar. 2016.
[13] J. Lamb and B. Mirafzal, “Open-circuit IGBT fault detection and location
isolation for cascaded multilevel converters,” IEEE Trans. Ind. Electron.,
vol. 64, no. 6, pp. 4846–4856, Jun. 2017.
[14] A. Anand, N. Raj, S. George, and G. Jagadanand, “Open switch fault
detection in cascaded H-bridge multilevel inverter using normalised mean
voltages,” in Proc. IEEE 6th Int. Conf. Power Syst., Mar. 2016, pp. 1–6.
[15] A. Anand, V. B. Akhil, N. Raj, G. Jagadanand, and S. George, “An open
switch fault detection strategy using mean voltage prediction for cascaded
H-bridge multilevel inverters,” in Proc. IEEE Int. Conf. Power Electron.,
Drives Energy Syst., Dec. 2018, pp. 1–5.
[16] U. Choi, J. Lee, F. Blaabjerg, and K. Lee, “Open-circuit fault diagnosis
and fault-tolerant control for a grid-connected NPC inverter,” IEEE Trans.
Power Electron., vol. 31, no. 10, pp. 7234–7247, Oct. 2016.
[17] J. He, N. A. O. Demerdash, N. Weise, and R. Katebi, “A fast on-line
diagnostic method for open-circuit switch faults in SiC-MOSFET-based t-
type multilevel inverters,” IEEE Trans. Ind. Appl., vol. 53, no. 3, pp. 2948–
2958, May/Jun. 2017.
[18] J. Amini and M. Moallem, “A fault-diagnosis and fault-tolerant control
scheme for flying capacitor multilevel inverters,” IEEE Trans. Ind. Elec-
tron., vol. 64, no. 3, pp. 1818–1826, Mar. 2017.
[19] A. Bennani-Ben Abdelghani, H. Ben Abdelghani, F. Richardeau, J.
Blaquire, F. Mosser, and I. Slama-Belkhodja, “Versatile three-level FC-
NPC converter with high fault-tolerance capabilities: Switch fault detec-
tion and isolation and safe postfault operation,” IEEE Trans. Ind. Electron.,
vol. 64, no. 8, pp. 6453–6464, Aug. 2017.
[20] I. Abari, A. Lahouar, M. Hamouda, J. B. H. Slama, and K. Al-Haddad,
“Fault detection methods for three-level NPC inverter based on dc-bus
electromagnetic signatures,” IEEE Trans. Ind. Electron., vol. 65, no. 7,
pp. 5224–5236, Jul. 2018.
[21] X. Ge, J. Pu, B. Gou, and Y. Liu, “An open-circuit fault diagnosis
approach for single-phase three-level neutral-point-clamped converters,”
IEEE Trans. Power Electron., vol. 33, no. 3, pp. 2559–2570, Mar. 2018.
[22] H. Yan, Y. Xu, F. Cai, H. Zhang, W. Zhao, and C. Gerada, “PWM-VSI
fault diagnosis for a PMSM drive based on the fuzzy logic approach,”
IEEE Trans. Power Electron., vol. 34, no. 1, pp. 759–768, Jan. 2019.
[23] J. Falck, C. Felgemacher, A. Rojko, M. Liserre, and P. Zacharias, “Reli-
ability of power electronic systems: An industry perspective,” IEEE Ind.
Electron. Mag., vol. 12, no. 2, pp. 24–35, Jun. 2018.
[24] L. M. A. Caseiro and A. M. S. Mendes, “Real-time IGBT open-circuit fault
diagnosis in three-level neutral-point-clamped voltage-source rectifiers
based on instant voltage error,” IEEE Trans. Ind. Electron., vol. 62, no. 3,
pp. 1669–1678, Mar. 2015.
Anjali Anand (S’17–M’20) received the B.Tech. de-
gree in electrical and electronics engineering from
the NSS College of Engineering, Palakkad, India, in
2010, and the M.Tech. degree in power electronics
and drives from the Visvesvaraya National Institute
of Technology, Nagpur, India, in 2013. She is cur-
rently working toward the Ph.D. degree in electrical
engineering with the National Institute of Technology
Calicut, Kozhikode, India.
She is also an Assistant Professor with the De-
partment of Electrical and Electronics Engineering,
Government College of Engineering Kannur, Kannur, India. Her current research
interests include multilevel inverters, condition monitoring, and fault-tolerant
operation of inverter-fed drives.
1574 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 2, MARCH/APRIL 2020
Akhil Vinayak B (S’17) received the B.Tech. de-
gree in electrical and electronics engineering from
College of Engineering Trivandrum, India, in 2010,
and the M.Tech. degree in power and energy systems
from the National Institute of Technology Karnataka,
Surathkal, India, in 2012. He is currently working
toward the Ph.D. degree in electrical engineering
with the National Institute of Technology Calicut,
Kozhikode, India.
He has two years of experience in the field of
cockpit simulation and virtual reality for airplane pilot
training. His research interests include condition monitoring of inverter-fed
motor drives, fault modeling of electrical machines, and fault diagnosis in
multilevel inverters.
Nithin Raj (S’15–M’20) received the B.Tech. degree
in electrical and electronics engineering from the
College of Engineering Kidangoor, Kottayam, India,
in 2010, the M.Tech. degree in electrical engineering
from the Maulana Azad National Institute of Tech-
nology, Bhopal, India, in 2013, and the Ph.D. degree
in electrical engineering from the National Institute
of Technology (NIT) Calicut, Kozhikode, India, in
2018.
After a brief stint with NIT Calicut, as an ad hoc
faculty with the Department of Electrical Engineering
in 2018, he joined L&T Technology Services, Bangalore, India, where he is
currently working in the field of electric vehicles. His research interests include
multilevel inverters, fault diagnostics in inverter systems, and applications of
power electronics in electric vehicles.
Authorized licensed use limited to: University of Warwick. Downloaded on May 22,2020 at 23:57:10 UTC from IEEE Xplore. Restrictions apply.
Jagadanand G (M’10) received the B.Tech. degree
in electrical and electronics engineering from the NSS
College of Engineering, Palakkad, India, in 1989,
the M.Tech. degree in electrical engineering from
Regional Engineering College Calicut, Kozhikode,
India, in 1991, and the Ph.D. degree in electrical
engineering from the National Institute of Technology
Calicut, Kozhikode, in 2013.
He is currently an Associate Professor with the
Department of Electrical Engineering, National In-
stitute of Technology Calicut. His current research
interests include power electronic circuits and control, multilevel inverters,
switching-mode power supplies, condition monitoring and diagnosis of drives
and converters, and induction motor drives.
Saly George (M’17) received the B.Tech. degree
in electrical engineering from the College of Engi-
neering Trivandrum, India, in 1982, and the M.Tech.
degree in power electronics and the Ph.D. degree in
power electronic drives from the National Institute of
Technology Calicut, Kozhikode, India, in 1990 and
2000, respectively.
Since 1983, she has been with the Department of
Electrical Engineering, National Institute of Tech-
nology Calicut, where she is currently a Pro-
fessor. Her research interests include dc and ac
motor drives, power electronic controllers, power quality issues, and flexible
ac transmission systems.