NANDHA ENGINEERING COLLEGE

(AUTONOMOUS)
E-ASSIGNMENT

NAME : R.MONISHA

REG NO :19VLF04

DEPT&YEAR : M.E-VLSI DESIGN/I-YEAR

SUBJECT : VLSI SYSTEM TESTING

DATE :
FAULTS IN DIGITAL CIRCUITS

The digital testing is to prevent faulty circuits from being assembled into
equipment, or to detect circuits which have developed faults subsequent to their
commitment. Our discussions here are largely in the context of LSI/VLSI circuits, but
apply equally to digital systems which have comparable controllability and observability
limitations.

Digital testing may be considered to have three purposes, namely:

 fault detection, which is to discover something wrong in a circuit or system,

ideally before it has caused any trouble;
 physical fault location, which is the location of the source of a fault within an
integrated circuit;
 component fault location, which is the location of a faulty component or
connection within a completed system.

The heirarchy of digital testing objectives:Many test procedures are equally

applicable to IC and system test, but some may be IC or system specific. Analogue
testing, see later, has an identical hierarchy. At each step every output test response has to
be checked, which requires prior knowledge of what the fault-free responses should be.
For very simple circuits; particularly of SSI and MSI complexity, the procedure may be
used; for more complex circuits. The principal difficulties with digital network testing are
(i) the volume of the simulation data, and (ii) the volume of data which has to be checked
at network outputs when under test.
In this consider means which have been proposed to ease the task of checking the
output response when under test, so that the very large number of individual 0 or 1 output
bits do not have to be compared step by step against the expected (fault-free)
response.Design for testability, sometimes called design for test and almost always
abbreviated to DFT, is therefore the philosophy of considering at the design stage how
the circuit or system shall be tested, rather than leaving it as a tack-on exercise at the end
of the design phase.DFT techniques normally fall into three general categories, namely:

 ad hoc design methods
 structured design methods
 self test.

The first two of these methods usually require the use of some external
comprehensive test facility, but the third method usually minimises to a considerable
extent the use of external test resources.

CLASSIFICATION OF FAULTS IN DIGITAL CIRCUITS

The fault model used in today’s are

 Stuck at fault
  Bridging fault
 Stuck open fault

STUCK AT FAULT

A stuck-at fault is a particular fault model used by fault simulators and automatic test

pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated
circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For
example, an input is tied to a logical 1 state during test generation to assure that a
manufacturing defect with that type of behavior can be found with a specific test pattern.
Likewise the input could be tied to a logical 0 to model the behavior of a defective circuit
that cannot switch its output pin. Not all faults can be analyzed using the stuck-at fault
model. Compensation for static hazards, namely branching signals, can render a circuit
untestable using this model. Also, redundant circuits cannot be tested using this model,
since by design there is no change in any output as a result of a single fault.

BRIDGING FAULT

A bridging fault consists of two signals that are connected when they should not be.
Depending on the logic circuitry employed, this may result in a wired-OR or wired-
AND logic function. Since there are O(n^2) potential bridging faults, they are normally
restricted to signals that are physically adjacent in the design. Bridging to VDD or Vss is
equivalent to stuck at fault model. Traditionally bridged signals were modeled with logic
AND or OR of signals. If one driver dominates the other driver in a bridging situation,
the dominant driver forces the logic to the other one, in such case a dominant bridging
fault is used. To better reflect the reality of CMOS VLSI devices, a dominant AND or
dominant OR bridging fault model is used where dominant driver keeps its value, while
the other signal value is the result of AND (or OR) of its own value with the dominant
driver.

STUCK OPEN FAULT

P1 and P2 are PMOS transistors when the gate terminal inputs A and B are 0.
Further, the inputs A and B also applied at the gate of NMOS transistors, N 1 and N2, If A
= B = 0 then P1 and P2 are shorted in the fault-free circuit and only P 2 is shorted in the
faulty circuit. N1 and N2 are open in both circuits. In CMOS circuit output C has some
parasitic capacitance with the charge from the previous operation of the circuit. In order
to detect the fault, Z assumes value 0.The output is produced by a BUS network whose
truth table is shown in Figure. Furthermore, as unknown three-state simulation, the state
in this model indicates the short circuit between the supply nodes. Stuck-open fault of a
PMOS transistor is modeled as a stuck-at-1 fault at the corresponding input signal and
that of an NMOS transistor as a stuck-at-0 fault.
ADVANTAGES OF FAULT MODEL

 Fault model identifies target faults

 Limits the scope of test generation
 Creates test only for the modeled faults
 Fault model makes effectiveness by experiments