VLSI Design, (KEC-072)

(KEC
Unit V VLSI Testing
 VLSI Testing
the number of transistors integrated into a single chip increases, the task of chip tes
ensure correct functionality becomes increasingly more difficult. However, in
oduction environment, many chips must be tested within a short time for timely deliv
customers. To overcome such difficult issues, design for testability has become ever m
ical.

put test vectors are devised and applied to the device under test (DUT) or circuit un
t (CUT) as its stimuli. Then the measured outputs are compared with the expec
rect responses to determine whether DUT is good or bad.
Defect : A defect in an electronic system is the unintended difference between th
implemented hardware and its intended design. For example: Process Defects –
missing contact windows, parasitic transistors, oxide break-down, etc. Materia
Defects – bulk defects (cracks, crystal imperfections), surface impurities, etc. Ag
Defects – dielectric breakdown, electromigration, Package Defects – contac
degradation, seal leaks, etc.

Error: A wrong output signal produced by a defective system is called an error. An

error is an “effect” whose cause is some “defect.”

Fault: A representation of a “defect” at the abstracted function level is called

fault.
 Fault Types and Models
hip testing, in the conventional sense, is usually multi-purpose
multi and attempts to detect
ults in fabrication, design, and failures due to stressful operating conditions.

cal defects include:

Defects in silicon substrate

hotolithographic defects

Mask contamination and scratches

rocess variations and abnormalities

Oxide defects
hysical defects can cause electrical faults and logical faults.
lectrical faults include:
Shorts (bridging faults)
Opens
Transistor stuck-on, stuck-open
Resistive shorts and opens
Excessive change in threshold voltage
Excessive steady-state currents
lectrical faults in turn can be translated into logical faults. The logical faults include:
Logical stuck-at-0 or stuck-at-1
Slower transition (delay fault)
AND-bridging, OR-bridging
Stuck at faults
 Stuck at fault

*Single stuck-at fault is independent of technology, design style.

*Single stuck-at tests cover a large percentage of multiple stuck-at faults.
* Single stuck-at tests cover a large percentage of unmodeled physical defects.

e delay fault which causes timing failures at target speed can be due to several factors.

Improper estimation of on-chip interconnect delays and other timing considerations,

Excessive variations in the fabrication process which cause significant variations in circuit
delays and clock skews,

Opens in metal lines connecting parallel transistors which make the effective transistor
size much smaller,

Aging effects such as hot-carrier induced delay increase.

 Controllability and Observability
he controllability of a circuit is a measure of the ease (or difficulty) with which th
ntroller (test engineer) can establish a specific signal value at each node by settin
lues at the circuit input terminals.

he observability is a measure of the ease (or difficulty) with which one can determin
e signal value at any logic node in the circuit by controlling its primary input an
bserving the primary output.

ere the term primary refers to the I/O boundary of the circuit under test. The degre
controllability and observability and, thus, the degree of testability of a circuit, ca
measured with respect to whether test vectors are generated deterministically o
ndomly.
detect any defect on line 8, the primary inputs A and B must be set to logic 1.
wever, such a setting forces line 7 to logic 1..

stuck-at- (s-a- 1) fault on line 7 can not be tested at the primary output, although in
absence of such a fault, the logic value on line 7 can be fully controllable through
mary inputs B, C, and D. Therefore, this circuit is not fully testable.

main cause of this difficulty in this circuit is the fact that input B fans out to lines
nd 6, and then after the OR3 gate, both line signals are combined in the AND3
. Such a fanout is called reconvergent fanout..

onvergent fanouts make the testing of the circuit much more difficult.
 Ad Hoc Testable Design Techniques
Hoc DFT techniques aim at improving the testability of stuck-at
stuck faults. The ad- hoc
T relies on “good” design practices learned from experience. Some of these are:
ition-and-Mux Technique
Since the sequence of many serial gates, functional blocks, or large circuits are
difficult to test, such circuits can be partitioned and multiplexors (muxes) can be
inserted such that some of the primary inputs can be fed to partitioned parts
through multiplexers with accessible control signals. With this design technique,
the number of accessible nodes can be increased and the number of test patterns
can be reduced. A case in point would be the 32-bit counter. Dividing this
counter into two 16-bit parts would reduce the testing time in principle by a factor
of 215. However, circuit partitioning and addition of multiplexers may increase
the chip area and circuit delay.
nitialize Sequential Circuit

When the sequential circuit is powered up, its initial state can be a random,
nknown state. In this case, it is not possible to start the test sequence correctly.
he state of a sequential circuit can be brought to a known state through
itialization. In many designs, the initialization can be easily done by connecting
ynchronous preset or clear-input signals from primary or controllable inputs to
ip-flops or latches.

isable Internal Oscillators and Clocks

 o avoid synchronization problems during testing, internal oscillators and clocks should be
isabled..
d Asynchronous Logic and Redundant Logic
he enhancement of testability requires serious trade-offs. The speed of an asynchronous
ogic circuit can be faster than that of the synchronous logic circuit counterpart.
he design and test of an asynchronous logic circuit are more difficult than for a
ynchronous logic circuit, and its state transition times are difficult to predict.
he operation of an asynchronous logic circuit is sensitive to input test patterns, often
ausing race problems and hazards of having momentary signal values opposite to the
xpected values.
ometimes, designed-in logic redundancy is used to mask a static hazard condition for
eliability. However, the redundant node cannot be observed since the primary output value
annot be made dependent on the value of the redundant node.
Hence, certain faults on the redundant node cannot be tested or detected. shows that the
ottom NAND2 gate is redundant and the stuck-at- fault on its output line cannot be
etected. If a fault is undetectable, the associated line or gate can be removed without
hanging the logic function.
Redundancy in circuits may be unintentional due to lack of design efficiency.

Avoid Delay-Dependent Logic

Chains of inverters can be used to design in delay times and use AND operation
heir outputs along with inputs to generate pulses,

As a result, such delay-dependent logic is viewed as redundant combinational logic, a

he output of the re-convergent gate is always set to logic 0, which is not correct. Thu
he use of delay-dependent logic should be avoided in design for testability.
 Scan-Based
Based Techniques
e controllability and observability can be enhanced by providing more accessible logic nodes
additional primary input lines and multiplexors
multiplexors.
e use of additional I/O pins can be costly not only for chip fabrication but also for pack
pular alternative is to use scan registers with both shift and parallel load capabilities.
e scan design technique is a structured approach to design sequential circuits for testabi
rage cells in registers are used as observation points, control points, or both.
using the scan design techniques, the testing of a sequential circuit is reduced to the pro
ing a combinational circuit.
general, a sequential circuit consists of a combinational circuit and some storage element
n-based design, the storage elements are connected to form a long serial shift register, the
n path, by using multiplexors and a mode (test/ normal) control

the test mode, the scan-in signal is clocked into the scan path, and the output of the last stag
nned out. In the normal mode, the scan-in path is disabled and the circuit functions as a se
uit. The testing sequence is as follows:
 ep 1: Set the mode to test and, let latches accept data from scan-in input.
ep 2: Verify the scan path by shifting in and out the test data.
ep 3: Scan in (shift in) the desired state vector into the shift register.
ep 4: Apply the test pattern to the primary input pins.
ep:5 Set the mode to normal and observe the primary outputs of the circuit
ufficient time for propagation.
ep:6 Assert the circuit clock, for one machine cycle to capture the outputs of
ombinational logic into the registers.
ep 7: Return to test mode; scan out the contents of the registers, and at the same
an in the next pattern.
ep 8: Repeat steps 3-7 until all test patterns are applied.
The main idea in scan design is to obtain control and observability for flip-flops. This
s done by adding a test mode to the circuit such that when the circuit is in this
mode, all flip-flops functionally form one or more shift registers.

The inputs and outputs of these shift registers (also known as scan registers) are
made into primary inputs and primary outputs
outputs. Thus, using the test mode, all flip-
lops can be set to any desired states by shifting those logic states into the shift
egister.

Similarly, the states of flip-flops are observed by shifting the contents of the scan
egister out. All flip-flops can be set or observed in a time (in terms of clock periods)
hat equals the number of flip-flops in the longest scan register
 BIST(Built in Self Test)
built-in self test (BIST) design, parts of the circuit are used to test the circuit itself. O
ne BIST is used to perform the test under normal operation, whereas off-line BIST
ed to perform the test off-line. The essential circuit modules required for BIST inclu

eudo random pattern generator (PRPG)

utput response analyzer (ORA)

he implementation of both PRPG and ORA can be done with Linear Feedback S
egisters (LFSRs).
 Pseudo Random Pattern Generator
o test the circuit, test patterns first have to be generated either by using a pseudo
ndom pattern generator, a weighted test generator, an adaptive test generator, or
her means. A pseudo random test generator circuit can use an LFSR.
Linear Feedback Shift register
 Random Logic BIST
BILBO – Built-In Logic Block Observer. This is a bank of circuit flip-flops with added te
hardware, which can be configured to make the flip-flops behave like a scan chain, a linear fee
hift register (LFSR) pattern generator, an LFSR
LFSR-based response compacter, or merely as D
lops.

Concurrent Testing – A testing process that detects faults during normal system operation.

CUT – Circuit-Under-Test

Exhaustive Testing – A BIST approach in which all possible patterns are applied to n c
nputs.

rreducible Polynomial – A Boolean polynomial that cannot be factored.

LFSR – Linear Feedback Shift Register. This is hardware that generates an exhaustive or pse
andom pattern sequence of test patterns, and can also be used as a response compacter.
Signature Analysis – A method of circuit response compaction during testing,
whereby the entire good circuit response is compacted into a good machine signature.
The actual circuit signature is generated during the testing process on the CUT,
and then compared with the good machine signature to determine whether the
CUT is faulty.

Output Response Analyzer

The on-chip storage of a fault dictionary containing all test inputs with the
orresponding outputs is prohibitively expensive in terms of the chip area. A simple
alternative method is to compare the outputs of two identical circuits for the same
nput, with one of them regarded as reference
reference. However, if both circuits have the
ame faults, their outputs can still match. Such faults cannot be detected with this
echnique, although, the probability of two identical circuits having exactly the
ame faults would be very low.
Example Modular LFSR
Response Analyzer

LFSR seed is “00000”

Copy
Agrawal
Signature by Logic Simulation

Input bits X0 X1 X2 X3 X4
Initial State 0 0 0 0 0
1 1 0 0 0 0
0 0 1 0 0 0
0 0 0 1 0 0
0 0 0 0 1 0
1 1 0 0 0 1
0 1 0 0 1 0
1 1 1 0 0 1
0 1 0 1 1 0 Signature

Copy
Agrawal
 Signature by Polynomial Division
Input bit stream: 0 1 0 1 0 0 0 1

0 ∙ X0 + 1 ∙ X1 + 0 ∙ X 2 + 1 ∙ X 3 + 0 ∙ X 4 + 0 ∙ X 5 + 0 ∙ X 6 + 1 ∙ X 7

X2 + 1
X5 + X3 + X + 1 X7 + X3 +X
Char. polynomial X7 + X5 + X3 + X2
X5 + X2 + X
X5 + X3 +X +1
remainder X3 + X2 +1
Signature: X0 X1 X2 X3 X4 = 1 0 1 1 0
Copy
Agrawal
 Built-In
In Logic Block Observer
The built-in
in logic block observer (BILBO) register is a form of ORA which can
be used in each cluster of partitioned registers. A basic BILBO circuit is shown
in Figure which allows four different modes controlled by C0 and Cl signals.
 Current Monitoring IDDQ Test
An often-used
used technique for testing fabrication defects is the IDDQ test. Under a bridging faul
the static currents drawn from the power supply in CMOS circuits can be noticeably high, w
beyond the expected range of leakage currents. For example, if the drain node of the pMOS
transistor in a CMOS inverter is shorted to the power supply rail due to a bridging fault, its
IDDQ current can be very high even when the input is high. It can also detect other fabricatio
defects not easily detected by other test methods, including:

Gate oxide short

Channel punch-through

p-n diode leakage

Transmission-gate defect
The design guidelines for IDDQ testability are as follows:

Low static current states, e.g., full CMOS is preferred

No active pull-ups or pull-downs

No internal drive conflicts, e.g., drivers share a bus

No floating nodes in the circuit

No degraded voltages, e.g., must have VOH = VDD and VOL = 0