UTaus Logic in CMOS

Introduction to VLSI Design, VLSI I, Fall 2011
3. Implementing Logic in CMOS
mm
40
40
60
80
100
120

J. A. Abraham
60
Department
of Electrical and Computer Engineering

The University of Texas at Austin
EE 382M.7 VLSI I
Fall 2011
80
August 31, 2011

ECE Department, University of Texas at Austin
Lecture 3. Implementing Logic in CMOS
J. A. Abraham, August 31, 2011
1 / 37
Static CMOS Circuits

N- and P-channel Networks
mm
40
60 implement80logic functions
100
N- and P-channel
networks
120
Each network connected between Output and VDD or VSS

Function defines path between the terminals
40
60
80
1 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin


Duality in CMOS Networks

Straightforward way of constructing static CMOS circuits is to
implement
mm dual N40and P- networks
60
80
100
N- and P- networks must implement complementary
functions
120
Duality sufficient for correct operation (but not necessary)

40
60
80
2 / 37
Constructing Complex Gates

mm F = (A40
Example:
B) + (C 60
D)
80
100
Take uninverted function F = (A B) + (C D) and derive

N-network
Identify AN D, OR components: F is OR of AB, CD
Make connections of transistors
120
40
60
80
3 / 37


Construction of Complex Gates, Contd

4
mm
40
Construct P-network
by 60
taking complement of
N-expression (AB + CD),
which gives the
expression,
40
(A + B) (C + D)
80
100
120
Combine P and N circuits

60
80
4 / 37
Layout of Complex Gate

mm
40
60
80
100
AND-OR-INVERT (AOI) gate
120
40
60
80
Note: Arbitrary shapes are not

allowed in some nanoscale
design rules
5 / 37


Example of Compound Gate

F = (A
+ B + C) D)
mm
40
Note:
60
80
100
120
N- and P- graphs are duals of each

other
40
In this case, the function is the

complement of the switching
function between F and GND
60
Question: Does it make any

difference to the function if the
transistor with input D is connected
between the parallel A, B, C,
80
transistors
and GND?
What about the electrical behavior?
6 / 37
Example of More Complex Gate

mm
40
60
80
100
120
40
60
80
OU T = (A + B) (C + D) (E + F + (G H))
7 / 37


Exclusive-NOR Gate in CMOS

mm
40
60
80
100
120
40
60
Note:80designs such as these should be checked very carefully for

correct behavior using circuit simulation
8 / 37
Pseudo nMOS Logic

Based on the old NMOS technology where a depletion transistor
was used as a pullup resistor
mm
40
60
80
100
What happens when there is no path from Z to ground (i.e., Z =

1)?
120
What happens when there is a path from Z to ground (i.e., Z = 0)?

40
60
80
9 / 37


Duality is Not Necessary for a CMOS Structure

Functions realized by N and P networks must be complementary,
and one of them must conduct for every input combination
mm
40
60
80
100
120
40
F = ab+ab+ac+cd+ab
The N and P networks are
NOT duals, but the switching
functions they implement
are complementary
60
80
10 / 37
Example of Complex CMOS Gate

mm
40
60
40
60
80
100
120
F=
G=
80
11 / 37


Example of Complex CMOS Gate, Contd

mm
40
60
40
80
100
120
F = xyz+xyz+xyz+xyz
G = xyz+xyz+xyz+xyz
60
80
12 / 37
Example of Complex CMOS Gate

mm
40
60
40
60
80
100
120
F =xyz+xyz+xy
G=xyz+xyz+xy
80
13 / 37


Signal Strength
mm
40
60
Voltages represent digital logic values

Strength of signal:
80
100
120
How close it approximates ideal voltage
V40DD and GN D rails are strongest 1 and 0

nMOS transistors pass a strong 0
But degraded or weak 1
pMOS transistors pass a strong 1

60
But degraded or weak 0
Therefore, nMOS transistors are best for the pull-down

network
80
14 / 37
Pass Transistors and Transmission Gates

Transistors can be used as switches; however, they could produce
degraded outputs
mm
40
60
80
100
120
40
Transmission gates pass both 0 and 1 well

60
80
15 / 37


Pass Transistor Logic

mm
40
60
80
100
120
40
Pull-Up Circuit
Used to restore degraded logic 1 from output of nMOS pass
transistor
60
80
16 / 37
Pass Transistor Logic Better Layout

mm
40
60 can be in80the same well
100
Group
similar transistors,
so they
120
40
60
80
17 / 37


10
Tristates
Tristate Buffer produces Z (high impedance) when not enabled
mm
EN A
0
0
0
1
1 400
1
1
Y
Z
Z
0
1
40
60
80
100
120
60
Non-Restoring
Tristate
Transmission gate acts as a tristate buffer

Only two transistors, but nonrestoring
Noise
on A is passed to Y
80
18 / 37
Tristate Inverter
Tristate inverter produces restored output, but complements signal
mm
40
60
80
100
120
40
EN
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
60
80
19 / 37


11
Multiplexers
mm
S
0
0
1
1
D1
X
X
40
0
1
40
D0
0
1
X
X
60
80
100
120
Y
0
1
0
1
60
How many transistors are needed?

(The better design uses 3 NAND
gates and 1 inverter)
80
20 / 37
Transmission Gate MUX

mm
Nonrestoring
MUX40
Uses two transmission
gates = only 4
transistors
60
80
100
120
40
Inverting MUX adds an inverter

Uses compound gate AOI22
Alternatively, a pair of tristate inverters (same thing)
60
80
21 / 37


12
4:1 Multiplexer
A 4:1 MUX chooses one of 4 inputs using two selects
mm
40
60
80
100
Two levels of 2:1 MUXes
120
Alternatively, four tristates

40
60
80
22 / 37
D Latch
Basicmm
Memory Element
40
60
80
When CLK = 1, latch is transparent
100
120
D flows through to Q like a buffer
When CLK = 0, the latch is opaque

40
Q holds its old value independent of D
a.k.a., transparent latch or level-sensitive latch
60
80
23 / 37


13
D Latch, Contd
mm
D Latch
Design: 40
MUX chooses
between D and
old Q
60
80
100
120
40
60
D Latch
80
Operation
24 / 37
D Flip-Flop (D-Flop)
Another common storage element
mm
40 D is copied
60 to Q
When CLK rises,
80
100
120
At all other times, Q holds its value

positive edge-triggered flip-flop or master-slave flip-flop
Built
40 from master and slave D latches
60
80
25 / 37


14
D Flip-Flop Operation
mm
40
60
80
100
120
40
60
80
26 / 37
Race Condition Hold Time Failure

mm
40
60
80
Back-to-back flops can malfunction from clock skew

Second flip-flop fires late
100
120
Sees first flip-flop change and captures its result

40
Called
hold-time failure or race condition
60
80
27 / 37


15
Non-Overlapping Clocks
A simple way to prevent races
mm
60
80 clock skew
100
This works as40long as non-overlap
exceeds
120
Used in safe (conservative) designs

Industry does not generally use this approach managing
skew more carefully instead
40
60
80
28 / 37
Gate Layout
Building a library of standard cells
mm
40
60
Layout can be time consuming
80
100
120
One solution is to have layouts of commonly used functions

(Inverter, NAND, OR, MUX, etc.), designed to fit together
very
40 well
Standard cell design methodology
VDD and GN D should abut (standard height)
60
Adjacent
gates should satisfy design rules
nMOS at bottom and pMOS at top

All gates include well and substrate contacts
One of the large industry suppliers is ARM (which purchased
80
ARTISAN)
29 / 37


16
Examples of Standard Cell Layout

Inverter
mm
NAND3
40
60
80
100
120
40
60
Horizontal N-diffusion and P-diffusion strips

80 Polysilicon gates
Vertical
Metal1 VDD rail at top, Metal1 GN D rail at bottom
32 by 40
30 / 37
Wiring Tracks and Well Spacing

Wiring
mmTrack is the
40 space
60
required for a wire
Example, 4 width, 4 spacing
from neighbor = 8 pitch
Transistors
also consume one
40
wiring track
Example,
wells 120
80 well spacing:
100
must surround transistors by
6
Implies 12 between opposite
transistor flavors
Leaves room for one wire track
60
80
31 / 37


17
Example of Area Estimation

mmarea by counting
Estimate
40
wiring tracks
Multiply by 8 to express in
60 Estimating80area of O3AI
100
120
Sketch a stick diagram and estimate

area
40
60
80
32 / 37
Example Circuit 1
Fill in the Karnaugh map to represent the Boolean function
mm
40 pass-transistor
60
100
implemented
by the
circuit.80
120
40
60
80
33 / 37


18
Example Circuit 1
mm
40
60
80
100
120
40
a
c
F(a,b,c,d,e):
e
60
0
d
80
0
1
0
10
1
3
0
1
0
11
9
5
7
e
1
0
1
15
13
4
6
1
0
1
14
12
20
22
30
28
21
23
31
29
17
19
27
25
16
18
26
24
34 / 37
Example Circuit 2
mm
40
60
80
100
Find the function, F, implemented by the following circuit
120
40
60
A + BC + B C
80
35 / 37


19
Example Circuit 2
mm
40
60
80
100
Find the function, F, implemented by the following circuit
120
40
60
A + BC + B C
80
35 / 37
Example Circuit 3
Find the functions X and Y implemented by the following circuit
mm
40
60
80
100
120
40
60
80
36 / 37


20
Example Circuit 3
Find the functions X and Y implemented by the following circuit
mm
40
60
80
100
120
40
60
80
37 / 37


UTaus Logic in CMOS

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

UTaus Logic in CMOS

Uploaded by

Copyright:

Available Formats

Introduction to VLSI Design, VLSI I, Fall 2011

3. Implementing Logic in CMOS

3. Implementing Logic in CMOS

of Electrical and Computer Engineering

August 31, 2011

Lecture 3. Implementing Logic in CMOS

J. A. Abraham, August 31, 2011

Static CMOS Circuits

Each network connected between Output and VDD or VSS

ECE Department, University of Texas at Austin

Lecture 3. Implementing Logic in CMOS

J. A. Abraham, August 31, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

Duality in CMOS Networks

Duality sufficient for correct operation (but not necessary)

ECE Department, University of Texas at Austin

Lecture 3. Implementing Logic in CMOS

J. A. Abraham, August 31, 2011

Constructing Complex Gates

Take uninverted function F = (A B) + (C D) and derive

Identify AN D, OR components: F is OR of AB, CD

Make connections of transistors

ECE Department, University of Texas at Austin

Lecture 3. Implementing Logic in CMOS

J. A. Abraham, August 31, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

Construction of Complex Gates, Contd

Combine P and N circuits

ECE Department, University of Texas at Austin

Lecture 3. Implementing Logic in CMOS

J. A. Abraham, August 31, 2011

Layout of Complex Gate

AND-OR-INVERT (AOI) gate

ECE Department, University of Texas at Austin

Note: Arbitrary shapes are not

J. A. Abraham, August 31, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

Example of Compound Gate

N- and P- graphs are duals of each

In this case, the function is the

Question: Does it make any

Lecture 3. Implementing Logic in CMOS

J. A. Abraham, August 31, 2011

Example of More Complex Gate

Lecture 3. Implementing Logic in CMOS

J. A. Abraham, August 31, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

Exclusive-NOR Gate in CMOS

Note:80designs such as these should be checked very carefully for

Lecture 3. Implementing Logic in CMOS

J. A. Abraham, August 31, 2011

Pseudo nMOS Logic

What happens when there is no path from Z to ground (i.e., Z =

What happens when there is a path from Z to ground (i.e., Z = 0)?

ECE Department, University of Texas at Austin

Lecture 3. Implementing Logic in CMOS

J. A. Abraham, August 31, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

Duality is Not Necessary for a CMOS Structure