Professional Documents
Culture Documents
VLSI Back End Tutorial
VLSI Back End Tutorial
Contents
1
Counters ................................................................................................................................................ 3
1.1
1.2
1.2.1
1.3
1.3.2
2.2
3.1.1
3.1.2
3.1.3
Rule 1. ................................................................................................................................. 12
3.1.4
Microwind ........................................................................................................................................... 16
4.1
1.3.1
3.1
4.1.1
NAND gate........................................................................................................................... 18
4.1.2
Figure
Figure 1 Logic Diagram of 2-bit Asynchronous Counter_________________________________________________ 3
Figure 2 Logic Diagram of 2 Bit synchronous Counters _________________________________________________ 5
Figure 3 Logic Diagram of Up/Down Counter ________________________________________________________ 7
Figure 4 an asynchronous up counter_______________________________________________________________ 9
Figure 5 Timing diagram of SISO register ___________________________________________________________ 10
Figure 6 4-Bit PISO register ______________________________________________________________________ 11
Figure 7 Layers used in Stick diagram______________________________________________________________ 12
Figure 8 Rule 1 representation ___________________________________________________________________ 12
Figure 9 Rule 2 representation ___________________________________________________________________ 13
Figure 10 Rule 3 Representation __________________________________________________________________ 13
Figure 11 Rule Representation ___________________________________________________________________ 13
Figure 12 P diffusion inside N well ________________________________________________________________ 15
Figure 13 an N well ____________________________________________________________________________ 15
Figure 14 A PMOS _____________________________________________________________________________ 15
Figure 15 An N diffusion layer ____________________________________________________________________ 15
Figure 16 An N-MOS ___________________________________________________________________________ 15
Figure 17 NOT gate ____________________________________________________________________________ 16
Figure 18 NOT Gate Stick Diagram ________________________________________________________________ 16
Figure 19 Pallet _______________________________________________________________________________ 16
Figure 20 Design in the Microwind ________________________________________________________________ 17
Figure 21 NAND gate CMOS_____________________________________________________________________ 18
Figure 22 NAND gate __________________________________________________________________________ 18
Figure 23 Timing Diagram of the NAND gate________________________________________________________ 18
Figure 24 AND gate using CMOS _________________________________________________________________ 19
Figure 25 AND gate by CMOS ______________________________________________Error! Bookmark not defined.
Figure 26 Clock wizard _________________________________________________________________________ 20
Figure 27 Timing diagram of AND gate ____________________________________________________________ 20
1 COUNTERS
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter.
Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Counters
can be classified into following types:-
Counters
Based on Clock
input
Synchronus
Counters
Asynchronous
Counters
Based on counting
Progress
Up Counter
Down Counter
Up Down Counter
S.N. Condition
1
Operation
Initially let both the FFs be in the reset state QBQA = 00................initially
On the arrival of second negative clock edge, FFA toggles again and QA = 0.
The change in QA acts as a negative clock edge
for FF-B. So it will also toggle, and QB will be 1.
QBQA = 10................After the second clock pulse
S.N.
Condition
Operation
QBQA = 00................initially
7
connected to the clock of the next stage if up counting is to be achieved. For this mode, the mode select
input M is at logic 0 (M=0). DOWN counting mode (M=1) - If M =1, then the Q bar output of the preceding
FF is connected to the next FF. This will operate the counter in the counting mode.
EXAMPLE:
S.N.
Condition
Operation
Shift
Registers
Serial input
Serial In
Serial Out
9
Serial in
Parallel Out
Parallel
input
Prallel In
Serial Out
Parallel In
Parallel Out
10
As shown above in Figure 5 a timing diagram of SISO register, the first wave form is of clock, second one
is data and the last is the output, as you can see, whatever the data is given is reflecting in output after
sometime, this is because of the delay of the register, in the figure the data is 1010 which is reflecting in
the output after the data entry is completed.
Shift Mode => This mode is for shifting the data from one register to another
Load Mode => this mode is for loading the data into the register
S.N. Condition
Operation
A 4bit PISO register and is time flow diagram is shown below in the figures:10
11
If M = 1, then the AND gates 1, 3, 5 and 7 are enable whereas the remaining
AND gates 2, 4, 6 and 8 will be disabled.
The data at DR is shifted to right bit by bit from FF-3 to FF-0 on the
application of clock pulses. Thus with M = 1 we get the serial right shift
operation.
When the mode control M is connected to 0 then the AND gates 2, 4, 6 and
8 are enabled while 1, 3, 5 and 7 are disabled.
The data at DL is shifted left bit by bit from FF-0 to FF-3 on the application
of clock pulses. Thus with M = 0 we get the serial right shift operation.
In this type of register a multiplexer is used, so as to switch between the output of Flip-Flop and the input
data, the switch decides the mode of the register. This is made by using 3 multiplexer and 4 flip flop.
11
12
Metal 1
Poly
Poly
N-diffusion
P diffusion
Figure 7 Layers used in Stick diagram
3.1.1
In essence we can say that a stick diagram is a cartoon of the circuit diagram.
3.1.2
3.1.3 Rule 1.
When two or more sticks of the same type cross or touch each other that represents electrical contact
12
Figure 8 Rule 1 representation
13
3.1.3.1 Rule 2
When two or more sticks of different type cross or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection explicitly).
3.1.3.2 Rule 3
When a poly crosses diffusion it represents a transistor.
3.1.3.3 Rule 4
In CMOS a demarcation line is drawn to avoid touching of P-diffusion with N-diffusion. All P-MOS must lie
on one side of the line and all N-MOS will have to be on the other side.
13
14
14
15
3.1.4 How to draw stick diagram
As we know CMOS abbreviated for Complementary Metal oxide semiconductor, it means it contain both
NMOS and CMOS in one substrate, so as to make circuit diagram some steps have to be considered, these
steps are
3.1.4.1 Steps to draw a PMOS
For implementing a PMOS
N well
Figure 13 an N well
Figure 14 A PMOS
N Diffusion
Figure 15 An N diffusion layer
15
Figure 16 An N-MOS
16
3.1.4.3 Example
Designing stick diagram of a Not gate:-
P-MOS
Shorted
Gates
P-MOS
Shorted
Gates
Shorted
drain
N-MOS
Shorted
drain
N-MOS
4 MICROWIND
Microwind is an EDA tool to design Stick diagram of the CMOS circuits,
technically saying this software is used by Back End Designers to design a
digital CMOS circuit on a silicon wafer. We will be using Microwind v-3.5 and
22n rule to design the circuits.
This part of designing will be limited to simulation only because it not possible
to design an IC anywhere.
All the tools of the Micro-wind are same except its pallet, Pallet is a
replacement of symbol library in DSCH. Every option of Pallet is described
below: Starting from Down to up the functions are explained below: N-well: -When on the P substrate we create a hole of N type layer then it is
known as N well.
N+ diffusion: - Highly doped N element use to make N-MOS.
P+ diffusion: - Highly doped P element use to make P-MOS.
16
Figure 19 Pallet
17
Poly-silicon: - Used to make gate of CMOS device, 1 and 2 refers to the layers of gates.
Contact: -
Metal contacts.
Metal1-6: -
The above symbols are for VDD, VSS, CLOCK and OUTPUT respectively. Out of all these things there one
more thing we need to know is about rules of VLSI. The rules of designing are categories by the level of
miniaturization of design. The latest is 22nm design rule and others are 45nm, 6m etc.
The latest version of Micro-Wind supports 22nm design rules. In Micro-Wind design rules are scaled by
lambda, Lambda is scaled such that it fulfill the requirement of all design rules. Design rules can be
changed as technology improved.
Now its the time for our first design, for that follow some screenshots and it is done.
Note in upper left corner of fig 20 under the white circle there is rating of lambda, which informs about
current scale we are using, this changes as design rule changes. And besides that notice each and every
part of the design. The metal contacts on the left side of the gate of both N-MOS and P-MOS are source
and we are taking output from the drain which is short by the metal layer and now watch the design of
NOT GATE shown in Figure 17 and then co relate them in terms of source and drain this is the easiest way
to understand this as far as I think.
17
18
NAND gate
A NAND gate is shown on the diagram
and its stick diagram is shown below
in Figure 22, note that how drain of
two PMOS is considered in one metal
contact, this is how space can be
reduces to the lowest level.
Drai
n
18
19
4.1.2
AND gate
An AND gate using CMOS, its
layout is simple, though there are
some extra learnings to design
the layout as short as possible,
however there can be more ways
to make it more miniature then
the one is shown in Figure 24
19
20
Now lets look out its response and for that we have to configure the clock as shown below: -
5 W/L RATIO
We can optimize this design too by varying W/L ratio of P and N MOS, this is the only factor a designer
can vary.
20
21
W/L is the transistor length to width ratio. It basically the only transistor parameter that an IC designer
will ever be able to change. Its hard for me to write here the detailed equations so I will just give you
some rules of thumb
This is enough for back end designing, the thing worth notice is, and we make all our back end by
referencing DSCH designs (front end), in every case we had our front end and then we design back end,
but sometimes it becomes very hard to implement the logic and even if we did then no guarantee it is
going to work or not, so for sorting out this problem here is a software which implement hardware for us,
all we have to do is to write the logic. The logics are written in VHDL language, which is based in C script.
VHDL stands for (VLSI hardware description language).
21