CHAPTER-4

LOW POWER COMPUTING

Sources of Energy Consumptions:
Power consumption is, in some situations, as important as execution time. In this section,
we study the characteristics of CPUs that influence power consumption and mechanisms provided
by CPUs to control how much power they consume. First, it is important to distinguish between
energy and power. Power is, of course, energy consumption per unit time. Heat generation
depends on power consumption. Battery life, on the other hand, most directly depends on energy
consumption. Generally, we will use the term power as shorthand for energy and power
consumption, distinguishing between them only when necessary. The high-level power
consumption characteristics of CPUs and other system components are derived from the circuits
used to build those components. Today, virtually all digital systems are built with complementary
metal oxide semiconductor (CMOS) circuitry. The detailed circuit characteristics are best left to
a study of VLSI design [Wol08], but the basic sources of CMOS power consumption are easily
identified and briefly described below.
Toggling: A CMOS circuit uses most of its power when it is changing its output value.
This provides two ways to reduce power consumption. By reducing the speed at which the circuit
operates, we can reduce its power consumption (although not the total energy required for the
operation, since the result is available later).We can actually reduce energy consumption by
eliminating unnecessary changes to the inputs of a CMOS circuiteliminating unnecessary
glitches at the circuit outputs eliminates unnecessary power consumption.
Leakage: Even when a CMOS circuit is not active, some charge leaks out of the circuits
nodes through the substrate. The only way to eliminate leakage current is to remove the power
supply. Completely disconnecting the power supply eliminates power consumption, but it usually
takes a significant amount of time to reconnect the system to the power supply and reinitialize its
internal state so that it once again performs properly.
Instruction level strategies for power management:
Power consumption in embedded applications can be reduced either by hardware, software or
both. Each instruction of a given program activates specific parts of the microprocessor.
Therefore, the election of the correct instruction can generate a reduction of the power consumed
by the processor.
1) The first technique is based on Instruction Reordering to Reduce Switching. The energy
consumed during the execution of an instruction will vary depending on what the previous
instruction was. Thus, an appropriate reordering of instructions in a program can result in
a lower energy. The application of this technique in the Intel 486 processor reveals that a
reduction in switching activity can be achieved by this technique does not translate into
very significant overall energy reduction. The results showed a variation of only 2% in the
energy cost. Nevertheless, in certain DSP processor, this technique can achieve a reduction
in the power consumption between 30% to 65% .
2) Another technique using Code Generation through Pattern Matching. This technique
modifies the cost function in the compiler (normally the number of execution cycles), to
obtain a code generator that targets energy reduction. The results show that the resulting
code was similar to the code generated when targeting cycles. The reason for this is that
the energy cost of an instruction pattern is obtained as the average power times the number
of clock cycles.
3) A Memory Operand Reduction technique. This approach was based on the hypothesis that
instructions with memory operands have very high-energy cost compared to instructions
with register operands. Thus, reduction in the number of memory operands can lead to

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large energy savings. The best way to achieve power reduction is an efficient register
management. This entails optimal register allocation of temporaries and global register
allocation for the most frequently used variables. Hand tuning of the code for shorter
running time leads to a 13.5% reduction in energy. So far only temporary variables have
been allocated to registers and the appropriate memory operands are replaced by register
operands. Even though redundant instructions are not removed, there is a 5% reduction in
current and a 7% reduction in running time. Finally, more variables are allocated to
registers and all redundant instructions are removed. Compared to the original program it
had a 40.6% lower energy consumption.
Memory System Power Consumption:
Memory bandwidth and on chip memory capacity are limiting factors for many multimedia
applications. Today, in many designs, onchip memory has already occupied more than 50% of
total chip area. Good memory management and are-,power- and yieldefficient memory
implementation.
The memory management is to provide an efficient memory hierarchy that consists of off
chip memory, onchip memory, and registers as shown below.

Fig: Memory hierarchy: tradeoff and characteristics

Different types of memories having different features. Off-chip memory, usually DRAM, offers a
large amount of storage size but consumes the most power. The off-chip memory and I/O access
may dominate the power budget. The embedded DRAM is developed to reduce the I/O access by
integrating large on-chip DRAM. However, the embedded DRAM technology is not very mature
because the yield issue, design methodology, and many physical design challenges still need to be
solved.
Besides, embedded compression (EC) technique can be applied to reduce the off-chip
memory bandwidth and size. Then, the on-chip memory, usually implemented by SRAM,
provides faster access and less power consumption than the off-chip memory, but the memory cell
size is much larger. Registers can be faster than on-chip memory and provide more flexible data
storage. However, the size of a register is the largest. Registers are more suitable for the
implementation of smaller-size buffers.
Memory management can be organized from different levels:
1) Algorithm-level: it is used to modify the coding system algorithm to improve some system
parameter, like power or area and some other parameters, like coding performance,
become the trade-off. The EC belongs to algorithm-level memory optimization.
2) Architecture-level: it is one kind of memory organization can optimize the memory
hierarchy from modifying hardware architecture.

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Cache:
To reduce overall power consumption, we can add cache memory to the low power
system. Actually, the cache cuts down on main memory cycles, often allowing them to be nearly
equivalent in number to the minimum number of allowable refresh cycles. This in itself reduces
the DRAMs power consumptions drastically in comparison to the consumed when they are
accessed for every memory cycle, nearly offsetting the power dissipation of an equal number of
SRAMs. further, if the number of DRAMs which are accessed at any one time is larger than the
number of SRAMs which are turned on for cache, the power consumed will necessarily be lower
When the processor operates from cache than when it operates from main memory. Lastly, the
fewer waits incurred by the CPU between its shutdown periods, the lower the CPUs overall
power consumption will be.
In certain handheld systems, the processors internal can be used in conjunction with
hand-tailored software to reduce power consumption. First of all, software is chopped up to fit
into the cache in modules, so that an entire module will reside in the cache when it is needed.
When the module is being loaded into the cache, the main memory (sometimes a ROM or Other
non volatile memory) runs at normal power. When the module is executed within the cache, the
main memory need not be powered up, so it is either put into a reduced-power mode, or it is
turned off completely. In this way, the power consumption can be reduced through the use of the
cache, and if the software is properly tuned to minimize accesses, power consumption can be
minimized.
System Level Power Management: The below are the power-saving strategies used in CMOS
CPUs:
CPUs can be used at reduced voltage levels. For example, reducing the power supply from 1 to
0.9 V causes the power consumption to drop by 12 0.92 _1.2X.
The CPU can be operated at a lower clock frequency to reduce power (but not energy)
consumption.
The CPU may internally disable certain function units that are not required for the currently
executing function. This reduces energy consumption.
Some CPUs allow parts of the CPU to be totally disconnected from the power supply to
eliminate leakage currents.
There are two types of power management features provided by CPUs.
1) A static power management mechanism is invoked by the user but does not otherwise
depend on CPU activities. An example of a static mechanism is a power down mode
intended to save energy. This mode provides a high-level way to reduce unnecessary
power consumption. The mode is typically entered with an instruction. If the mode stops
the interpretation of instructions, then it clearly cannot be exited by execution of another
instruction. Power-down modes typically end upon receipt of an interrupt or other event.
2) A dynamic power management mechanism takes actions to control power based upon the
dynamic activity in the CPU. For example, the CPU may turn off certain sections of the
CPU when the instructions being executed do not need them.

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