Unit 8 - IT

DMA Controller 8257

The Direct Memory Access or DMA mode of data transfer is the fastest amongst
all the modes of data transfer. In this mode, the device may transfer data directly to/from
memory without any interference from the CPU. The device requests the CPU (through a
DMA controller) to hold its data, address and control bus, so that the device may transfer
data directly to/from memory.
The DMA data transfer is initiated only after receiving HLDA signal from the CPU.
Intels 8257 is a four channel DMA controller designed to be interfaced with their family
of microprocessors. The 8257, on behalf of the devices, requests the CPU for bus access
using local bus request input i.e. HOLD in minimum mode. In maximum mode of the
microprocessor RQ/GT pin is used as bus request input.
On receiving the HLDA signal (in minimum mode) or RQ/GT signal (in maximum
mode) from the CPU, the requesting devices gets the access of the bus, and it completes
the required number of DMA cycles for the data transfer and then hands over the control
of the bus back to the CPU.

Internal Architecture of 8257

The internal architecture of 8257 is shown in figure. The chip support four DMA
channels, i.e. four peripheral devices can independently request for DMA data transfer
through these channels at a time. The DMA controller has 8-bit internal data buffer, a
read/write unit, a control unit, a priority resolving unit along with a set of registers.
Register Organization of 8257

The 8257 performs the DMA operation over four independent DMA channels.
Each of four channels of 8257 has a pair of two 16-bit registers, viz. DMA address
register and terminal count register.

There are two common registers for all the channels, namely, mode set register and status
register. Thus there are a total of ten registers. The CPU selects one of these ten registers
using address lines Ao-A3. Table shows how the Ao-A3 bits may be used for selecting
one of these registers.
DMA Address Register
Each DMA channel has one DMA address register. The function of this register is
to store the address of the starting memory location, which will be accessed by the DMA
channel. Thus the starting address of the memory block which will be accessed by the
device is first loaded in the DMA address register of the channel.
The device that wants to transfer data over a DMA channel, will access the block of the
memory with the starting address stored in the DMA Address Register.

Terminal Count Register

Each of the four DMA channels of 8257 has one terminal count register (TC).
This 16-bit register isused for ascertaining that the data transfer through a DMA channel
ceases or stops after the required number of DMA cycles. The low order 14-bits of the
terminal count register are initialised with the binary equivalent of the number of required
DMA cycles minus one.
After each DMA cycle, the terminal count register content will be decremented by one
and finally it becomes zero after the required number of DMA cycles are over. The bits
14 and 15 of this register indicate the type of the DMA operation (transfer). If the device
wants to write data into the memory, the DMA operation is called DMA write operation.
Bit 14 of the register in this case will be set to one and bit 15 will be set to zero.
Table gives detail of DMA operation selection and corresponding bit configuration of bits
14 and 15 of the TC register.

Mode Set Register

The mode set register is used for programming the 8257 as per the requirements
of the system. The function of the mode set register is to enable the DMA channels
individually and also to set the various modes of operation.
The DMA channel should not be enabled till the DMA address register and the terminal
count register contain valid information, otherwise, an unwanted DMA request may
initiate a DMA cycle, probably destroying the valid memory data. The bits Do-D3 enable
one of the four DMA channels of 8257. for example, if Do is 1, channel 0 is enabled. If

bit 4 is set, rotating priority is enabled, otherwise, the normal, i.e. fixed priority is
enabled.

If the TC STOP bit is set, the selected channel is disabled after the terminal count
condition is reached, and it further prevents any DMA cycle on the channel. To enable
the channel again, this bit must be reprogrammed. If the TC STOP bit is programmed to
be zero, the channel is not disabled, even after the count reaches zero and further request
are allowed on the same channel.
The auto load bit, if set, enables channel 2 for the repeat block chaining operations,
without immediate software intervention between the two successive blocks. The channel
2 registers are used as usual, while the channel 3 registers are used to store the block
reinitialisation parameters, i.e. the DMA starting address and terminal count. After the
first block is transferred using DMA, the channel 2 registers are reloaded with the
corresponding channel 3 registers for the next block transfer, if the update flag is set. The
extended write bit, if set to 1, extends the duration of MEMW and IOW signals by
activating them earlier, this is useful in interfacing the peripherals with different access
times.
If the peripheral is not accessed within the stipulated time, it is expected to give the NOT
READY indication to 8257, to request it to add one or more wait states in the DMA
CYCLE. The mode set register can only be written into.
Status Register
The status register of 8257 is shown in figure. The lower order 4-bits of this
register contain the terminal count status for the four individual channels. If any of these
bits is set, it indicates that the specific channel has reached the terminal count condition.

These bits remain set till either the status is read by the CPU or the 8257 is reset. The
update flag is not affected by the read operation. This flag can only be cleared by
resetting 8257 or by resetting the auto load bit of the mode set register. If the update flag
is set, the contents of the channel 3 registers are reloaded to the corresponding registers of
channel 2 whenever the channel 2 reaches a terminal count condition, after transferring
one block and the next block is to be transferred using the autoload feature of 8257.
The update flag is set every time, the channel 2 registers are loaded with contents of the
channel 3 registers. It is cleared by the completion of the first DMA cycle of the new
block. This register can only read.

Data Bus Buffer, Read/Write Logic, Control Unit and Priority Resolver
The 8-bit. Tristate, bidirectional buffer interfaces the internal bus of 8257 with the
external system bus under the control of various control signals.
In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals, decodes
the Ao-A3 lines and either writes the contents of the data bus to the addressed internal
register or reads the contents of the selected register depending upon whether IOW or
IOR signal is activated.
In master mode, the read/write logic generates the IOR and IOW signals to control the
data flow to or from the selected peripheral. The control logic controls the sequences of
operations and generates the required control signals like AEN, ADSTB, MEMR,
MEMW, TC and MARK along with the address lines A4-A7, in master mode. The
priority resolver resolves the priority of the four DMA channels depending upon whether
normal priority or rotating priority is programmed.

Signal Description of 8257

DRQo-DRQ3 :
These are the four individual channel DMA request inputs, used by the peripheral
devices for requesting the DMA services. The DRQo has the highest priority while
DRQ3 has the lowest one, if the fixed priority mode is selected.
DACKo-DACK3 :
These are the active-low DMA acknowledge output lines which inform the
requesting peripheral that the request has been honoured and the bus is relinquished by
the CPU. These lines may act as strobe lines for the requesting devices.

Pin Diagram of 8257

Do-D7:
These are bidirectional, data lines used to interface the system bus with the
internal data bus of 8257. These lines carry command words to 8257 and status word
from 8257, in slave mode, i.e. under the control of CPU.
The data over these lines may be transferred in both the directions. When the 8257 is the
bus master (master mode, i.e. not under CPU control), it uses Do-D7 lines to send higher
byte of the generated address to the latch. This address is further latched using ADSTB
signal. the address is transferred over Do-D7 during the first clock cycle of the DMA
cycle. During the rest of the period, data is available on the data bus.
IOR:
This is an active-low bidirectional tristate input line that acts as an input in the
slave mode. In slave mode, this input signal is used by the CPU to read internal registers
of 8257.this line acts output in master mode. In master mode, this signal is used to read
data from a peripheral during a memory write cycle.
IOW :
This is an active low bidirection tristate line that acts as input in slave mode to
load the contents of the data bus to the 8-bit mode register or upper/lower byte of a 16-bit

DMA address register or terminal count register. In the master mode, it is a control output
that loads the data to a peripheral during DMA memory read cycle (write to peripheral).
CLK:
This is a clock frequency input required to derive basic system timings for the
internal operation of 8257.
RESET :
This active-high asynchronous input disables all the DMA channels by clearing
the mode register and tristates all the control lines.
Ao-A3:
These are the four least significant address lines. In slave mode, they act as input
which select one of the registers to be read or written. In the master mode, they are the
four least significant memory address output lines generated by 8257.
CS:
This is an active-low chip select line that enables the read/write operations
from/to 8257, in slave mode. In the master mode, it is automatically disabled to prevent
the chip from getting selected (by CPU) while performing the DMA operation.
A4-A7 :
This is the higher nibble of the lower byte address generated by 8257 during the
master mode of DMA operation.
READY:
This is an active-high asynchronous input used to stretch memory read and write
cycles of 8257 by inserting wait states. This is used while interfacing slower peripherals..
HRQ:
The hold request output requests the access of the system bus. In the noncascaded 8257 systems, this is connected with HOLD pin of CPU. In the cascade mode,
this pin of a slave is connected with a DRQ input line of the master 8257, while that of
the master is connected with HOLD input of the CPU.
HLDA :
The CPU drives this input to the DMA controller high, while granting the bus to
the device. This pin is connected to the HLDA output of the CPU. This input, if high,
indicates to the DMA controller that the bus has been granted to the requesting peripheral
by the CPU.
MEMR:
This active low memory read output is used to read data from the addressed
memory locations during DMA read cycles.
MEMW :

This active-low three state output is used to write data to the addressed memory
location during DMA write operation.
ADST :
This output from 8257 strobes the higher byte of the memory address generated
by the DMA controller into the latches.
AEN:
This output is used to disable the system data bus and the control the bus driven
by the CPU, this may be used to disable the system address and data bus by using the
enable input of the bus drivers to inhibit the non-DMA devices from responding during
DMA operations. If the 8257 is I/O mapped, this should be used to disable the other I/O
devices, when the DMA controller addresses is on the address bus.
TC:
Terminal count output indicates to the currently selected peripherals that the
present DMA cycle is the last for the previously programmed data block. If the TC STOP
bit in the mode set register is set, the selected channel will be disabled at the end of the
DMA cycle.
The TC pin is activated when the 14-bit content of the terminal count register of the
selected channel becomes equal to zero. The lower order 14 bits of the terminal count
register are to be programmed with a 14-bit equivalent of (n-1), if n is the desired
number of DMA cycles.
MARK :
The modulo 128 mark output indicates to the selected peripheral that the current
DMA cycle is the 128th cycle since the previous MARK output. The mark will be
activated after each 128 cycles or integral multiples of it from the beginning if the data
block (the first DMA cycle), if the total number of the required DMA cycles (n) is
completely divisible by 128.
Vcc :
This is a +5v supply pin required for operation of the circuit.
GND :
This is a return line for the supply (ground pin of the IC).

Interfacing 8257 with 8086

Once a DMA controller is initialised by a CPU property, it is ready to take control of the
system bus on a DMA request, either from a peripheral or itself (in case of memory-tomemory transfer). The DMA controller sends a HOLD request to the CPU and waits for
the CPU to assert the HLDA signal. The CPU relinquishes the control of the bus before
asserting the HLDA signal.
A conceptual implementation of the system is shown in Figure

Once the HLDA signal goes high, the DMA controller activates the DACK signal to the
requesting peripheral and gains the control of the system bus. The DMA controller is the
sole master of the bus, till the DMA operation is over. The CPU remains in the HOLD
status (all of its signals are tristate except HOLD and HLDA), till the DMA controller is
the master of the bus.
In other words, the DMA controller interfacing circuit implements a switching
arrangement for the address, data and control busses of the memory and peripheral
subsystem from/to the CPU to/from the DMA controller.

8.2 SERIAL COMMUNICATION USING 8251

8251 is a Universal Synchronous and Asynchronous Receiver and Transmitter
compatible with Intels processors. This chip converts the parallel data into a serial
stream of bits suitable for serial transmission. It is also able to receive a serial stream of
bits and convert it into parallel data bytes to be read by a microprocessor.
8.2.1 Basic Modes of data transmission
a) Simplex
b) Duplex
c) Half Duplex
a) Simplex mode
Data is transmitted only in one direction over a single communication channel. For
example, the processor may transmit data for a CRT display unit in this mode.
b) Duplex Mode
In duplex mode, data may be transferred between two transreceivers in both directions
simultaneously.

c) Half Duplex mode

In this mode, data transmission may take place in either direction, but at a time data may
be transmitted only in one direction. A computer may communicate with a terminal in
this mode. It is not possible to transmit data from the computer to the terminal and
terminal to computer simultaneously.

8.2.2 Architecture of 8251A

Fig. 8.1 Internal architecture of 8251

The data buffer interfaces the internal bus of the circuit with the system bus. The
read / write control logic controls the operation of the peripheral depending upon the
operations initiated by the CPU. C /

D decides whether the address on internal data

bus is control address / data address. The modem control unit handles the modem
handshake signals to coordinate the communication between modem and USART.
The transmit control unit transmits the data byte received by the data buffer from
the CPU for serial communication. The transmission rate is controlled by the input
frequency. Transmit control unit also derives two transmitter status signals namely
TXRDY and TXEMPTY which may be used by the CPU for handshaking. The
transmit buffer is a parallel to serial converter that receives a parallel byte for
conversion into a serial signal for further transmission.

The receive control unit decides the receiver frequency as controlled by the RXC
input frequency. The receive control unit generates a receiver ready (RXRDY) signal
that may be used by the CPU for handshaking. This unit also detects a break in the
data string while the 8251 is in asynchronous mode. In synchronous mode, the 8251
detects SYNC characters using SYNDET/BD pin.

8.2.3 Signal Description of 8251

Fig. 8.2 Pin Configuration of 8251

D0 D7 : This is an 8-bit data bus used to read or write status, command word or data
from or to the 8251A.
C / D : (Control Word/Data): This input pin, together with RD and WR inputs,
informs the 8251A that the word on the data bus is either a data or control word/status
information. If this pin is 1, control / status is on the bus, otherwise data is on the bus.
RD : This active-low input to 8251A is used to inform it that the CPU is reading either
data or status information from its internal registers.

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This active-low input to 8251A is used to inform it that the CPU is writing data or control
word to 8251A.

WR : This is an active-low chip select input of 825lA. If it is high, no read or write

operation can be carried out on 8251. The data bus is tristated if this pin is high.
CLK : This input is used to generate internal device timings and is normally connected to
clock generator output. This input frequency should be at least 30 times greater than the
receiver or transmitter data bit transfer rate.
RESET : A high on this input forces the 8251A into an idle state. The device will remain
idle till this input signal again goes low and a new set of control word is written into it.
The minimum required reset pulse width is 6 clock states, for the proper reset operation.

TXC (Transmitter Clock Input) : This transmitter clock input controls the rate at which
the character is to be transmitted. The serial data is shifted out on the successive negative
edge of the TXC

TXD (Transmitted Data Output) : This output pin carries serial stream of the
transmitted data bits along with other information like start bit, stop bits and parity bit,
etc.

RXC (Receiver Clock Input) : This receiver clock input pin controls the rate at which
the character is to be received.
RXD (Receive Data Input) : This input pin of 8251A receives a composite stream of the
data to be received by 8251 A.
RXRDY (Receiver Ready Output) : This output indicates that the 8251A contains a
character to be read by the CPU.
TXRDY - Transmitter Ready : This output signal indicates to the CPU that the internal
circuit of the transmitter is ready to accept a new character for transmission from the
CPU.

DSR - Data Set Ready : This is normally used to check if data set is ready when
communicating with a modem.
DTR

- Data Terminal Ready : This is used to indicate that the device is ready to

accept data when the 8251 is communicating with a modem.

RTS - Request to Send Data : This signal is used to communicate with a modem.

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TXE- Transmitter Empty : The TXE signal can be used to indicate the end of a
transmission mode.

8.2.4 Operating Modes of 8251

1.

Asynchronous mode

2.

Synchronous mode

Asynchronous Mode (Transmission)

When a data character is sent to 8251A by the CPU, it adds start bits prior to the
serial data bits, followed by optional parity bit and stop bits using the asynchronous mode
instruction control word format. This sequence is then transmitted using TXD output pin
on the falling edge of TXC.
Asynchronous Mode (Receive)
A falling edge on RXD input line marks a start bit. The receiver requires only one stop
bit to mark end of the data bit string, regardless of the stop bit programmed at the
transmitting end. The 8-bit character is then loaded into the into parallel I/O buffer of
8251. RXRDY pin is raised high to indicate to the CPU that a character is ready for it. If
the previous character has not been read by the CPU, the new character replaces it, and
the overrun flag is set indicating that the previous character is lost.

Mode instruction format for Asynchronous mode

Fig. 8.3 Mode Instruction Format Asynchronous Mode

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Asynchronous Mode Transmit and Receive Formats

Fig. 8.4 Asynchronous Mode Transmit and Receive Formats

Synchronous mode
Synchronous Mode Instruction Format

Fig. 8.5 Synchronous Mode Instruction Format

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Synchronous Mode (Transmission)

The TXD output is high until the CPU sends a character to 8251 which usually is a
SYNC character. When CTS

line goes low, the first character is serially transmitted

out. Characters are shifted out on the falling edge of TXC .Data is shifted out at the same
rate as TXC , over TXD output line. If the CPU buffer becomes empty, the SYNC
character or characters are inserted in the data stream over TXD output.
Synchronous Mode (Receiver)
In this mode, the character synchronization can be achieved internally or externally. The
data on RXD pin is sampled on rising edge of the RXC . The content of the receiver
buffer is compared with the first SYNC character at every edge until it matches. If 8251
is programmed for two SYNC characters, the subsequent received character is also
checked. When the characters match, the hunting stops.
The SYNDET pin set high and is reset automatically by a status read operation. In the
external SYNC mode, the synchronization is achieved by applying a high level on the
SYNDET input pin that forces 8251 out of HUNT mode. The high level can be removed
after one RXC cycle. The parity and overrun error both are checked in the same way as
in asynchronous mode.
Synchronous mode Transmit and Receive data format

Fig. 8.6 Data Formats of Synchronous Mode

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Command Instruction Definition

The command instruction controls the actual operations of the selected format like
enable transmit/receive, error reset and modem control. A reset operation returns 8251
back to mode instruction format.
Command Instruction format

Fig. 8.7 Command Instruction Format

Status Read Definition

This definition is used by the CPU to read the status of the active 8251 to confirm if any
error condition or other conditions like the requirement of processor service has been
detected during the operation.

Fig. 8.8 Status Read Instruction Format

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8.2.5 Interfacing 8251 with 8086

Design the hardware interface circuit for interfacing 8251 with 8086. Set the 8251 in
asynchronous mode as a transmitter and receiver with even parity enabled, 2 stop bits, 8bit character length, frequency 160 kHz and baud rate 10 K.
(a) Write an ALP to transmit 100 bytes of data string starting at location
2000:5000H.
(b) Write an ALP to receive 100 bytes of data string and store it at 3000:4000.

Solution :
Asynchronous mode control word for transmitting 100 bytes of data :
D7

D6

D5

D4

D3

D2

2 Stop bits

Even Parity 8-bit

Enabled

D1
1

D0
0 = FEH

CLK scaled

format

a) ALP to initialize 8251 and transmit 100 bytes of data

ASSUME CS:CODE
CODE SEGMENT
START : MOV AX,2000H
MOV DS,AX ; DS points to byte string segment
MOV SI,5000H ; SI points to byte string
MOV CL,64H ; Length of string in CL (hex)
MOV AL,0FEH ; Mode control word to D0 D7
OUT 0FEH,AL
MOV AX,11H

; Load command word

OUT 0FE,AL ; to transmit enable and error reset

WAIT : IN AL,0FEH ; Read status
AND AL,01H ; Check transmitter enable
JZ WAIT

; bit, if zero wait for the transmitter to be ready

MOV AL,[SI] ; If ready, first byte of string data

OUT 0FCH, AL ; is transmitted

16

INC SI

; Point to next byte

DEC CL

; Decrement counter

JNZ WAIT

; If CL is not zero, go for next byte

MOV AH,4CH
INT 21H
CODE ENDS
END START

b) An ALP to initialize 8251 and receive 100 bytes of data

ASSUME CS:CODE
CODE SEGMENT
START : MOV AX,3000H
MOV DS,AX

; Data segment set to 3000H

MOV SI,4000H

; Pointer to destination offset

MOV CL,64H

; Byte count in CL

MOV AL,7EH

; Only one stop bit for

OUT OFEH,AL

; receiver is set

MOV AL,14H

; Load command word to enable

OUT 0FEH,AL ; the receiver and disable transmitter

NXTBT : IN AL,OFEH ; Read status
AND AL,38H ; Check FE, OE and PE
JZ READY

; If zero, jump to READY

MOV AL,14H

; If not zero, clear them

OUT OFEH,AL
READY: IN AL,0FEH ; Check RXRDY, if receiver is not ready
AND AL,02H
JZ READY

; wait

IN AL,0FCH ; If it is ready,
MOV [SI],AL ; receive the character
INC SI

; Increment pointer to next byte

DEC CL

; Decrement counter

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JNZ NXTBT ; Repeat, if CL is not zero

MOV AH,4CH
INT 21H
CODE ENDS
END START

Fig. 8.9 Interfacing of 8251 with 8086

8.3 NUMERIC DATA PROCESSOR 8087

The numeric data processor is a coprocessor which has been designed to work under the
control of the 8086 processor. It offers additional numeric processing capabilities. It is
available in 5 MHz, 8 MHz and 10 MHz versions 8086 will perform the opcode fetch
cycles and identify the instructions for 8087. Once the instruction is identified by 8086,
it is allotted to 8087 for further execution.
8086-8087 couplet implements instruction level master-slave configuration. After
the completion of the 8087 execution cycle, the results may be referred back to the CPU.
The 8087 instructions may lie interleaved in the 8086 program as if they belong to the
8086 instruction set. It is the task of 8086 to identify the 8087 instructions from the

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program, send it to the 8087 for execution and get back the results. The 8087 adds 68
new instructions to the instruction set of 8086.

8.3.1 Architecture of 8087

Fig. 8.10 8087 Architecture

8087 is divided internally into two sections namely Control unit and Numeric
Extension Unit. The numeric extension unit executes all the numeric processor
instructions. The control unit receives, decodes instructions, reads and writes memory
operands executes the 8087 control instructions. The control unit is responsible for
establishing communication between the CPU and memory and also for coordinating
the data bus to check for the 8087 instructions.
The 8087 control unit internally maintains a parallel queue, identical to the status
queue of the main CPU. The control unit automatically monitors the BHE / S7 line to

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detect the CPU type and accordingly adjusts the queue length. The 8087 uses the QS0
and QS1 pins to obtain and identify the instructions fetched by the host CPU (8086).
8086 identifies the coprocessor instructions using the ESCAPE code bits in them. Once
the CPU recognizes the ESCAPE code, it triggers the execution of the numeric processor
instruction in 8087.
The Numeric Extension Unit (NEU) executes all the instructions including arithmetic,
logical, transcendental, and data transfer instructions. The internal data bus is 84 bits
wide including 68 bit fraction, 15 bit exponent and a sign bit. When the NEU begins the
execution, it pulls up the BUSY signal. This BUSY signal is connected to the TEST
input of 8086. 8086 waits till the BUSY pin of 8087 goes low. i.e. 8086 waits till the
8087 executes instruction completely.
The microcode control unit generates the control signals required for execution of
instructions. 8087 contains a programmable shifter which is responsible for shifting the
operands during the execution of instructions like FMUL and FDIV. The data bus
interface connects the internal data bus of 8087 with the CPU system data bus.

8.3.2 Signal Descriptions of 8087

Fig. 8.11 Pin Diagram of 8087

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AD0 AD15 : These are the time multiplexed address / data lines. These lines carry
addresses during T1 and data during T2, T3, Tw and T4 states.
A19 / S6 A16/S3 : These lines are the time multiplexed address / status lines. These
function in a similar way to the corresponding pins of 8086. The S6, S4 and S3 are
permanently high, while the S5 is permanently low.
BHE / S7 : During T1, the BHE / S7 is used to enable data on to the higher byte of the
8086 data bus. During T2, T3, Tw and T4 this is a status line S7.
QS1 , QS0 : The queue status input signals QS1 and QS0 enable 8087 to keep track of the
instruction prefetch queue status of the CPU, to maintain synchronism with it.
QS1

QS0

Queue Status

No operation

First byte of opcode from queue

Empty queue

Subsequent byte from queue

INT : The interrupt output is used by 8087 to indicate that an unmasked exception has
been received during execution. This is usually handled by 8259.
BUSY : This output signal, when high, indicates to the CPU that it is busy with the
execution of allotted instruction. This is usually connected to the TEST pin of 8086.
READY : This input signal may be used to inform the coprocessor that the addressed
device with complete the data the transfer from inside and the bus is likely to be free for
the next cycle.
RESET : This input signal is used to abandon the internal activities of the coprocessor
and prepare it for further execution whenever asked by the main CPU.
CLK : The CLK input provides the basic timings for the processor operation.
VCC : A +5 V supply line required for operation of the circuit.
GND : A return line for the power supply.

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S 2 , S1 and S 0 : These can either be 8087 driven (output) or externally driven (input)
by the CPU. If

S 2 , S1 and S 0 are driven by 8087, they can be decode as shown

below :

S 2 , S1 and

S2

S1

S0

Queue Status

Unused

Unused

Memory read

Memory write

Passive

S 0 becomes active during T4 (of previous bus cycle) and becomes

suspended during T3 of the next bus cycle S 2 , S1 and S 0 acts as input signals if the
CPU is executing a task.

RQ / GT0 : The Request / Grant pin is used by the 8087 to gain control of the bus from
the host 8086 / 8088 for operand transfers. It must be connected to the one of the request /
grant pin of the host.An active low pulse of one clock duration is generated by 8087 for
the host to inform that it wants to gain control of the local bus for itself or for other
coprocessor connected to RQ / GT1 pin of the 8087. When 8087 receives a grant pulse,

it either initiates a bus cycle if the request is for itself or else, it passes the grant pulse to
RQ / GT1 , if the request is for the other coprocessor.
RQ / GT1 : This bidirectional pin is used by the other bus masters to convey their need
of the local bus access to 8087. This request is conveyed to the host CPU using RQ /
GT 0 pin. The requesting bus master gains the control of the bus till it needs. At the end,

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the requesting bus master issues an active low pulse to 8087, to indicate that the task is
over and 8087 may regain the control of the bus.

8.3.3 Register Set of 8087

The 8087 has a set of eight 80-bit registers that can be used be used as a stack or a set of
general registers. When operating as a stack, it operates from the top on one or two
registers. When operating as a register set, they may be used only with the instructions
designed for them. Registers of 8087 are divided into three fields namely : sign (1-bit) ,
exponent (15-bits) and significand (64 bits).
Corresponding to each of the 8 registers, there is a two bit TAG field to indicate the
status of contents as shown below:
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TAG (7) TAG (6) TAG (5) TAG (4) TAG (3) TAG (2) TAG (1) TAG (0)

Fig. 8.12 Tag Word of 8087

TAG VALUES :
00 = VALID ,

01 = ZERO ,

10 = SPECIAL ,

11 = EMPTY

The TAG word register presents all the TAG fields to CPU. The instructions may
address data registers either implicitly or explicitly. An internal status register field,
TOP is used to address any one of the 8 registers implicitly. While explicitly addressing
the registers, they may be addressed relative to TOP.

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Status word of 8087

Fig. 8.13 Status word of 8087

The bit definitions of status field are as follows :
B0 B5 : These bits indicate that an exception has been detected. These 6 bits are used to
indicate the 6 types of previously generated exceptions.
B7 : This bit is set if any unmasked exception has been detected ; otherwise this is
cleared.
B8 B10 and B14 : These 4 condition code bits reflect the status of the results calculated
by the 8087.
B15 : The BUSY bit shows the status of NEU (Numeric Execution Unit).
Instruction and Data Pointers
The instruction and data pointers are used to enable the programmers to write their own
exception handling subroutines. Before executing a mathematical instruction, the
instruction pointer and the data pointer contain the current address of the instruction and
the corresponding data.

24

Control Word Register

The control word register of 8087 allows the programmer to select the required
processing options out of available ones. In other words, the 16-bit control word register
is used to control the operation of the 8087.
15

12

IC RC

PC

IEM

PM

UM OM ZM DM

IM

Fig. 8.14 Control Word Register and the bit definitions

IM = Invalid operation

, DM = Denormalized operand

ZM = Zero Divide

, OM = Overflow

UM = Underflow,

PM = Precision

IEM = Interrupt Enable Mask, PC = precision Control (2 bits)

RC = Rounding Control (2 bits) , IC = Infinity Control
The bits B0 B5 are used for masking the different exceptions. If the bit is 1, exception is
masked. The infinity control bit IC provides control over the number size on both sides.
i.e. either +

or -

8.3.4 Exception Handling

The 8087, while executing an instruction, may generate 6 different exceptions. Any of
these exceptions, if generated, causes an interrupt to the CPU provided it is not masked.
The CPU will respond if the interrupt flag of the CPU is set.
Invalid Operation : These are the exceptions generated due to stack overflow, or stack
underflow, indeterminate form as result, or, non-number as operand.
Overflow : A too big result to fit in the format generates this exception.
Underflow : If a small (in magnitude) result is generated, to fit in the specified format,
8087 generates this exception.
Zero Divide : If any non-zero finite operand is divided by zero, this exception is
generated.
Denormalized Operand : This exception is generated, if at least one of the operands is
denormalized.
25

Inexact Result : if it is impossible to fit the actual result in the specified format, this
exception is generated.

8.3.5 Instruction Set of 8087

The 8087 adds 68 instructions to the instruction set of 8086, all of which may lie
interleaved in an 8086 ALP. The 8087 instructions are fetched by 8086 but are executed
by 8087. Whenever the 8086 comes across 8087 instruction, it executes the ESCAPE
instruction code to pass over the instruction opcode and control of the local bus to 8087.
The additional instructions supported by 8087 can categorized into the following types:
1. Data Transfer Instructions.
2. Arithmetic Instructions.
3. Comparison Instructions.
4. Transcendental Operations.
5. Constant Operations.
6. Coprocessor Control Operations.
Data Transfer Instructions
Depending upon the data types handled, these are further grouped into 3 types.

Floating Point Data Transfer.

Integer Data Transfer.

BCD Data Transfer.

Floating Point Data Transfer Instructions

FLD (Load Real to Top of Stack) : This instruction loads a real operand to the top of
the stack of the 80-bit registers.
FLD ST( 7 )

; Stack Top

FLD MEM

; Stack Top

[ Reg 7 ]
[ MEM ]

FST (Store Top of Stack to the operand) : This instruction stores current content of the
top of the stack register to the specified operand.
FST ST ( 7 ) ; Stack Top

[ST ( 7 ) ]

FST MEM

[ MEM ]

; Stack Top

FSTP (Store Floating Point Number and Pop) : This instruction stores a copy of top of
stack into memory or any coprocessor register and then pops the top of the stack.

26

FXCH (Exchange with Top of Stack) : This instruction exchanges the contents of the
top of stack with the specified operand register.
Integer Data Transfer Instructions
FILD (Load Integer to Stack Top : This instruction loads the specified integer data
operand to the top of stack.
FIST / FISTP : Both the instructions work in an exactly similar manner as FST / FSTP
except the fact that the operands are integer operands.

BCD Data Transfer Instructions

The 8087 instruction set has two instructions of this type, namely, FBLD and FBSTP.
Both the instructions work in an exactly similar as FLD and FSTP except for the operand
type BCD.
Arithmetic Instructions
The 8087 instruction set contains 11 instructions that can either be directly used to
perform arithmetic operations or supporting operations like scaling, rounding, negation,
absolute value, etc.
FADD
The instruction FADD performs real or integer addition of the specified operand with the
stack top. The results are stored in destination operand controlled by the D-bit. The
operand may be any of the stack registers or a memory location.
FSQRT : This instruction finds out the square root of the content of the stack top and
stores the result on stack top again.
FSUB : The instruction FSUB performs real or integer subtraction of the specified
operand from the stack top.
FMUL : This instruction performs real or integer multiplication of the specified operand
with stack top.
FDIV : This instruction performs real or integer division.
FSCAL : This instruction multiplies the content of the stack top by 2n, where n is the
integer part of ST (1) and stores the result in ST.
FPREM : This instruction divides the stack top by ST (1) and stores the remainder to
stack top.

27

FRNDINT : This instruction rounds the contents of ST (0) to its integer value. The
rounding is controlled by the RC field of the control word.
FXTRACT : This instruction extracts the exponent and fraction of the stack top and
stores them in the stack registers.
FABS : This instruction replaces the content of the stack top by its absolute value
(magnitude).
FCSH ; This instruction changes the sign of the content of the stack top.
Transcendental Instructions
The 8087 provides 5 instructions for transcendental calculations. The operands are
usually ST (0) and ST (1) or only ST (0).
FPTAN : This instruction calculates the partial tangent of an angle , where must be in
the range from 0 < 900 .
FPATAN :

This instruction calculates the arctangent (inverse tangent) of a ratio

ST / ST (1).
F2XMI : This instruction calculates the expression (2x-1). The value of x is stored at the
top of the stack. The result is stored back at the top of the stack.
FLY2X : This instruction calculates the expression ST(1)*log2 ST. A pop operation is
carried out on the top of Stack. The ST must be in the range 0 to +, while the ST(1)
must be in the range - to +.
FLY2XPI : This instruction is used to calculate the expression ST(1) *log2 [(ST)+1].
The result is stored back on the stack top after a pop operation. The value of |ST| must lie
between 0 and (1-21/2/2) and the value of ST(1) must be between - to +.
Comparison Instructions : All the comparison instructions Compare the operands and
modify condition code flags as shown below :
Comparison

C3

C0

Stack Top > Source

Stack Top < Source

Stack Top = Source

Not Comparable

28

FCOM :
This instruction compares real or integer operands specified by stack registers or
memory. This instruction has the top of stack as an implicit operand. The content of the
top of stack is compared either with the contents of a memory location or with the
contents of another stack register. The conditional code flags bits (C3 and C0) are
accordingly modified.
FCOMP and FCOMPP:
These instructions also work in an exactly similar manner as FCOM does. But the
FCOMP instruction carries out one pop operation after the execution of the FCOM
instruction. FCOMPP carries out two pop operations after the execution of the FCOM
instruction. The FCOMP and FCOMPP instructions have the top of the stack as an
implicit operand.
FIST : This instruction tests if the contents of the stack top is zero. Here, the contents of
the stack top is compared with zero and the condition code flags are accordingly
modified. The zero is considered as the source operand.
FXAM : This instruction examines the contents of the stack top and modifies the
contents of the condition flags.
Constant Returning Instructions : These instructions load the specific constants to the
top of the register stack. The stack top is an implicit operand in this type of instructions.
FLDZ : Load +0.0 to stack top.
FLDI : Load +1.0 to stack top.
FLDPI : Load to stack top.
FLD2T : Load the constant log2 10 to stack top.
FLDL2E : Load the constant log2 e to stack top.
FLDLG2 : Load the constant log10 2 to stack top.
FLDLN2 : Load the constant loge 2 to stack top.
Coprocessor Control Instructions
The coprocessor control instructions are either used to program the numeric processor.
These are also used to handle the functions like exception handling, flags manipulations,
processor environment maintenance and preparation.

29

FINIT : This instruction prepares the 8087 for further execution. It performs the same
function as the hardware reset. All flags are cleared and stack top is initialized at ST(0).
FENI : This instruction enables the interrupt structure and response mechanism of 8087.
i.e. The interrupt mask flag is cleared.
FDISI : This instruction sets the interrupt mask flag to disable the interrupt response
mechanism of 8087.
FLDCW : This instruction loads the control word of 8087 from the specified source
operand. Any addressing mode allowed in 8086 may be used to refer the memory
operand.
FSTCW : This instruction may be used to store the contents of the 8087 control word
register to a memory location, addressed using any of the 8086 addressing modes.
FSTSW : This instruction stores the current contents of the status word register to a
memory location, addressed using any of the 8086 addressing modes.
FCLEX : This instruction clears all the previously set exception flags in the status
register. This also clears the BUSY and IR flags of the status word.
FINCSTP : This instruction modifies the TOP bits of the status register so as to point to
the next stack register.
FDECSTP : This instruction updates the TOP bits of the stack register so as to point to
the previous register in stack.
FFREE : This instruction marks the TAG field of the operand stack register to be empty.
FNOP : This is a NOP instruction of the coprocessor. No internal status or control flag
bits change. This requires up to 16 clock cycles for execution.
FWAIT : This instruction is used by 8087 to make 8086 wait till it completes the current
operation. The BUSY pin of 8087 is tied high by 8087 to inform the host CPU that the
allotted task is still under execution.
FSTENV : This instruction is used to store the environment of the coprocessor to a
destination memory location specified in the instruction using any of the 8086 addressing
modes.
FLDENV : This instruction loads the environment (that may be previously stored in the
memory using FSTENV instruction) of the coprocessor into it.

30

FSAVE : This instruction saves the complete processor status into the memory, at the
address specified by the destination operand. The complete status of the processor
requires 94 bytes of memory.
FRSTOR : Using this instruction it is possible to restore the previous status of the
coprocessor from a source memory operand.

8.3.6 Interfacing 8087 with 8086 / 8088

Fig. 8.15 Interfacing 8087 with 8086 / 8088

8087 can be connected to 8086 / 8088 only in their maximum mode of operation. In the
maximum mode, all the control signals are derived using a separate chip called as a bus
controller. The 8288 is a bus controller compatible with 8086 / 8088. The BUSY pin of
8087 is connected to the TEST pin of the CPU. The QS0 and QS1 lines may be directly
connected to the corresponding pins in the case of 8086 /8088 based systems.
The clock pin of 8087 is connected to clock input of CPU. The interrupt output of
8087 is connected to the CPU through a Programmable Interrupt Controller 8259. The
pins AD0 AD15,

BHE / S7, RESET, A19 / S6 A16 / S3 of 8087 are connected to

corresponding pins of the CPU.

31

Addressing Modes and Data Types

8087 supports all the addressing modes supported by 8086. The data types supported by
8087 are :
Data Formats

Range

Precision

Word Integer

104

16 bits

Short Integer

104

32 bits

Long Integer

1018

64 bits

Packed BCD

1018

18 bits

Short Real

10 +38

24 bits

Long Real

10 +308

53 bits

Temporary Real

10 +4932

64 bits

Write a procedure to calculate the volume of a sphere.

This procedure utilizes service of the register stack of 8087 to store the data temporarily
.8087
DATA SEGMENT
RADIUS DD 5.0233
CONS EQU 1.333
VOLUME DD 1 DUP (?)
DATA ENDS
ASSUME CS:CODE, DS:DATA
VOL PROC NEAR
CODE SEGMENT
START : MOV AX,DATA
MOV DS,AX

; Initialize Data Segment

FINIT

; Initialize 8087

FLD RADIUS

; Read radius into stack top

FST ST(4)

; Store stack top

FMUL ST(4)
FMUL ST(4)

32

FLD CONST

; Get constant 1.333

FMUL

; Multiply with (r3)

FLDPI

; Get PI (p)

FMUL

; Multiply with PI

FST VOLUME

; Store volume in VOLUME

RETP
RETP
VOL ENDP
CODE ENDS
END START

8.4 RS 232 Serial Communication Standards

In serial I/O, data can be transmitted as either current or voltage. When data is
transmitted as voltage, the commonly used standard is known as RS-232C. This standard
was developed by Electronic Industries Association (EIA), USA and adopted by IEEE.
RS-232 standard proposes a maximum of 25 signals for the bus used for serial data
transfer.

8.4.1 RS-232 Pin Names and Signal Descriptions

Pin Number

Common Name

RS-232 Name

Description

AA

Protective Ground

TxD

BA

Transmitted Data

RxD

BB

Received Data

RTS

CA

Request to Send

CTS

CB

Clear to Send

DSR

CC

Data Set Ready

33

GND

AB

Signal Ground

CD

CF

Received Line signal detector

Reserved for Data set testing

10

Reserved for Data set testing

12

SCF

Secondary Receiver Line

Signal Detector

13

SCB

Secondary Clear to Send

14

SBA

Secondary Transmitted Data

15

DB

Transmission signal element

timing

16

SBF

Secondary Received Data

17

DD

Receiver Signal element timing

18

Unassigned

19

SCA

Secondary request to send

20

DTR

CD

Data terminal ready

21

CG

Signal quality detector

22

CE

Ring indicator

23

CH / CI

Data signal rate selector

24

DA

Transmitted Signal element

timing

25

Unassigned

34

In practice, the first 9-signals are sufficient for most of the serial data transmission
scheme. Hence, the RS-232C bus signals are transmitted on a D-type 9-pin connector.
When all the 25 signals are used, then RS-232C serial bus is terminated on a 25-pin
connector.

Fig. 8.16 Connections used for terminating RS-232C bus

The voltage levels used for all RS-232C signals are :

Logic Low = -3V to -15V under load (-25V on no load)
Logic High = +3V to +15V under load (+25V on no load)

Commonly used voltage levels are,

+12V (Logic high) and -12V (Logic low)

The RS-232C signal levels are not compatible with TTL logic levels.

For interfacing TTL devices, level converters or RS-232C line drivers are
employed.

The popularly used level converters are :

1. MC 1488 - TTL to RS-232C level converter.

2. MC 1489 RS-232C to TTL level converter.

35

Fig1.9.
8259A in
Cascaded
Mode

Fig. 8.17 TTL to RS-232C and RS-232C to TTL signal conversion

Fig. 8.18 TTL to RS-232C and RS-232C to TTL signal conversion using RS-232C

MAX 232 is a bidirectional level converter. It is equivalent to a combination of MC 1488

and MC 1489 in single IC

36