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PIC18 (L) F2X/4XK22 Data Sheet: 28/40/44-Pin, Low-Power, High-Performance Microcontrollers With XLP Technology
PIC18 (L) F2X/4XK22 Data Sheet: 28/40/44-Pin, Low-Power, High-Performance Microcontrollers With XLP Technology
PIC18 (L) F2X/4XK22 Data Sheet: 28/40/44-Pin, Low-Power, High-Performance Microcontrollers With XLP Technology
Data Sheet
28/40/44-Pin, Low-Power,
High-Performance Microcontrollers
with XLP Technology
DS41412F
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2010-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620763131
== ISO/TS 16949 ==
DS41412F-page 2
PIC18(L)F2X/4XK22
28/40/44-Pin, Low-Power, High-Performance
Microcontrollers with XLP Technology
High-Performance RISC CPU:
C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
Up to 1024 Bytes Data EEPROM
Up to 64 Kbytes Linear Program Memory
Addressing
Up to 3896 Bytes Linear Data Memory Addressing
Up to 16 MIPS Operation
16-bit Wide Instructions, 8-bit Wide Data Path
Priority Levels for Interrupts
31-Level, Software Accessible Hardware Stack
8 x 8 Single-Cycle Hardware Multiplier
Analog Features:
Analog-to-Digital Converter (ADC) module:
- 10-bit resolution, up to 30 external channels
- Auto-acquisition capability
- Conversion available during Sleep
- Fixed Voltage Reference (FVR) channel
- Independent input multiplexing
Analog Comparator module:
- Two rail-to-rail analog comparators
- Independent input multiplexing
Digital-to-Analog Converter (DAC) module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
Charge Time Measurement Unit (CTMU) module:
- Supports capacitive touch sensing for touch
screens and capacitive switches
Peripheral Highlights:
Up to 35 I/O Pins plus 1 Input-Only Pin:
- High-Current Sink/Source 25 mA/25 mA
- Three programmable external interrupts
- Four programmable interrupt-on-change
- Nine programmable weak pull-ups
- Programmable slew rate
SR Latch:
- Multiple Set/Reset input options
Two Capture/Compare/PWM (CCP) modules
Three Enhanced CCP (ECCP) modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
- PWM steering
Two Master Synchronous Serial Port (MSSP)
modules:
- 3-wire SPI (supports all 4 modes)
- I2C Master and Slave modes with address
mask
DS41412F-page 3
PIC18(L)F2X/4XK22
Two Enhanced Universal Synchronous
Asynchronous Receiver Transmitter (EUSART)
modules:
- Supports RS-485, RS-232 and LIN
- RS-232 operation using internal oscillator
- Auto-Wake-up on Break
- Auto-Baud Detect
SRAM
(Bytes)
EEPROM
(Bytes)
I/O(1)
10-bit
A/D Channels(2)
CCP
ECCP
(Full-Bridge)
ECCP
(Half-Bridge)
SPI
I2C
EUSART
Comparator
CTMU
BOR/LVD
SR Latch
8-bit Timer
16-bit Timer
MSSP
# Single-Word
Instructions
Data Memory
Flash
(Bytes)
Program
Memory
PIC18(L)F23K22
8K
4096
512
256
25
19
PIC18(L)F24K22
16K
8192
768
256
25
19
PIC18(L)F25K22
32K
16384
1536
256
25
19
PIC18(L)F26K22
64k
32768
3896
1024
25
19
PIC18(L)F43K22
8K
4096
512
256
36
30
PIC18(L)F44K22
16K
8192
768
256
36
30
PIC18(L)F45K22
32K
16384
1536
256
36
30
PIC18(L)F46K22
64k
32768
3896
1024
36
30
Device
Note 1:
2:
DS41412F-page 4
PIC18(L)F2X/4XK22
Pin Diagrams (28-pin)
28-pin PDIP, SOIC, SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIC18(L)F2XK22
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RB7/PGD
RB6/PGC
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
RA1
RA0
MCLR/VPP/RE3
RB7/PGD
RB6/PGC
RB5
RB4
28 27 26 25 24 23 22
1
2
3
4 PIC18(L)F2XK22
5
6
7
8 9 10 11 12 13 14
21
20
19
18
17
16
15
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RA2
RA3
RA4
RA5/
VSS
RA7
RA6
Note
1:
The 28-pin UQFN package is available only for PIC18(L)F23K22 and PIC18(L)F24K22.
DS41412F-page 5
PIC18(L)F2X/4XK22
Pin Diagrams (40-pin)
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
VDD
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RD0
RD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18(L)F4XK22
40-pin PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
40
39
38
37
36
35
34
33
32
31
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
40-pin UQFN
1
2
3
4
5 PIC18(L)F4XK22
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RB3
RB4
RB5
PGC/RB6
PGD/RB7
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
11
12
13
14
15
16
17
18
19
20
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
DS41412F-page 6
PIC18(L)F2X/4XK22
Pin Diagrams (44-pin)
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
44-pin TQFP
1
2
3
4
5
6 PIC18(L)F4XK22
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
NC
NC
RB4
RB5
PGC/RB6
PGD/RB7
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
22
21
20
19
18
17
16
15
14
13
12
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
1
2
3
4
5
6 PIC18(L)F4XK22
7
8
9
10
11
33 RA6
32 RA7
31 VSS
30 VSS
29 VDD
28 VDD
27 RE2
26 RE1
25 RE0
24 RA5
23 RA4
RB3
NC
RB4
RB5
PGC/RB6
PGD/RB7
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
22
21
20
19
18
17
16
15
14
13
12
RC7
RD4
RD5
RD6
RD7
VSS
VDD
VDD
RB0
RB1
RB2
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
44-pin QFN
DS41412F-page 7
PIC18(L)F2X/4XK22
C2IN+
AN3
RA3
RA4
AN4
Basic
AN2
Pull-up
RA2
Interrupts
Timers
C12IN1-
MSSP
C12IN0-
AN1
EUSART
AN0
RA1
(E)CCP
Comparator
RA0
28
Reference
Analog
27
SR Latch
I/O
CTMU
28-QFN, UQFN
28-SSOP, SOIC
28-SPDIP
TABLE 1:
VREFDACOUT
C1IN+
VREF+
C1OUT
SRQ
C2OUT
SRNQ
CCP5
T0CKI
RA5
10
RA6
OSC2
CLKO
RA7
OSC1
CLKI
21
18
RB0
AN12
22
19
RB1
AN10
23
20
RB2
AN8
24
21
RB3
AN9
SRI
SS1
CCP4
FLT0
SS2
INT0
P1C
SCK2
SCL2
INT1
CTED1
P1B
SDI2
SDA2
INT2
CTED2
CCP2
P2A(1)
SDO2
C12IN3-
C12IN2-
HLVDIN
25
22
RB4
AN11
P1D
T5G
IOC
26
23
RB5
AN13
CCP3
P3A(4)
P2B(3)
T1G
T3CKI(2)
IOC
27
24
RB6
TX2/CK2
IOC
PGC
28
25
RB7
RX2/DT2
IOC
PGD
11
RC0
P2B(3)
SOSCO
T1CKI
T3CKI(2)
T3G
12
RC1
CCP2
P2A(1)
SOSCI
13
10
RC2
AN14
CCP1
P1A
T5CKI
14
11
RC3
AN15
SCK1
SCL1
15
12
RC4
AN16
SDI1
SDA1
CTPLS
16
13
RC5
AN17
17
14
RC6
AN18
CCP3
P3A(4)
TX1/CK1
SDO1
18
15
RC7
AN19
P3B
RX1/DT1
26
RE3
MCLR
VPP
VSS
19
16
VSS
20
17
Note 1:
2:
3:
4:
VDD
CCP2/P2A multiplexed in fuses.
T3CKI multiplexed in fuses.
P2B multiplexed in fuses.
CCP3/P3A multiplexed in fuses.
DS41412F-page 8
PIC18(L)F2X/4XK22
21
21
RA2
AN2
C2IN+
AN3
Basic
19
Pull-up
C12IN1-
Interrupts
C12IN0-
AN1
Timers
AN0
RA1
MSSP
Comparator
RA0
20
EUSART
Analog
19
20
(E)CCP
I/O
19
18
Reference
44-QFN
17
SR Latch
44-TQFP
CTMU
40-UQFN
40-PDIP
TABLE 2:
VREFDACOUT
20
22
22
RA3
21
23
23
RA4
22
24
24
RA5
14
29
31
33
RA6
OSC2
CLKO
13
28
30
32
RA7
OSC1
CLKI
33
RB0
AN12
34
10
RB1
AN10
35
10
10
11
RB2
AN8
36
11
11
12
RB3
AN9
37
12
14
14
RB4
AN11
38
13
15
15
RB5
AN13
39
14
16
16
RB6
IOC
PGC
40
15
17
17
RB7
IOC
PGD
15
30
32
34
RC0
P2B(4)
SOSCO
T1CKI
T3CKI(2)
T3G
16
31
35
35
RC1
CCP2(1)
P2A
SOSCI
17
32
36
36
RC2
AN14
CCP1
P1A
T5CKI
18
33
37
37
RC3
AN15
SCK1
SCL1
23
38
42
42
RC4
AN16
SDI1
SDA1
AN4
C1IN+
VREF+
C1OUT
SRQ
C2OUT
SRNQ
SRI
T0CKI
HLVDIN
SS1
FLT0
INT0
C12IN3CTED1
C12IN2-
CTED2
Y
Y
24
39
43
43
RC5
AN17
25
40
44
44
RC6
AN18
TX1
CK1
26
RC7
AN19
RX1
DT1
19
34
38
38
RD0
AN20
20
35
39
39
RD1
AN21
CCP4
21
36
40
40
RD2
AN22
P2B(4)
22
37
41
41
RD3
AN23
P2C
SS2
27
RD4
AN24
P2D
SD02
T5G
IOC
T1G
T3CKI(2)
IOC
SDO1
SCK2
SCL2
SDI2
SDA2
28
RD5
AN25
P1B
29
RD6
AN26
P1C
TX2
CK2
30
RD7
AN27
P1D
RX2
DT2
23
25
25
RE0
AN5
CCP3
P3A(3)
Note 1:
2:
3:
4:
INT2
CCP2
P2A(1)
CCP3
P3A(3)
CTPLS
INT1
DS41412F-page 9
PIC18(L)F2X/4XK22
Interrupts
P3B
10
25
27
27
RE2
AN7
CCP5
16
18
18
RE3
11
32
7, 26
7
28
7,8
28, 29
VDD
12
31
6, 27
6
29
6
30, 31
VSS
12, 13
33, 34
13
Note 1:
2:
3:
4:
Basic
AN6
Pull-up
RE1
Timers
26
MSSP
26
EUSART
Analog
24
(E)CCP
I/O
Reference
44-QFN
SR Latch
44-TQFP
CTMU
40-UQFN
Comparator
40-PDIP
TABLE 2:
MCLR
VPP
NC
DS41412F-page 10
PIC18(L)F2X/4XK22
Table of Contents
1.0 Device Overview ....................................................................................................................................................................... 13
2.0 Oscillator Module (With Fail-Safe Clock Monitor)) .................................................................................................................... 27
3.0 Power-Managed Modes ............................................................................................................................................................ 47
4.0 Reset ......................................................................................................................................................................................... 59
5.0 Memory Organization ................................................................................................................................................................ 69
6.0 Flash Program Memory............................................................................................................................................................. 95
7.0 Data EEPROM Memory .......................................................................................................................................................... 105
8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 111
9.0 Interrupts .................................................................................................................................................................................. 113
10.0 I/O Ports .................................................................................................................................................................................. 135
11.0 Timer0 Module ........................................................................................................................................................................ 159
12.0 Timer1/3/5 Module with Gate Control...................................................................................................................................... 163
13.0 Timer2/4/6 Module .................................................................................................................................................................. 175
14.0 Capture/Compare/PWM Modules ........................................................................................................................................... 179
15.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module .............................................................................................. 211
16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................................................. 267
17.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 297
18.0 Comparator Module.................................................................................................................................................................. 311
19.0 Charge Time Measurement Unit (CTMU)................................................................................................................................ 321
20.0 SR LATCH................................................................................................................................................................................. 337
21.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 343
22.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................. 345
23.0 High/Low-Voltage Detect (HLVD) ............................................................................................................................................ 349
24.0 Special Features of the CPU ................................................................................................................................................... 355
25.0 Instruction Set Summary ......................................................................................................................................................... 373
26.0 Development Support.............................................................................................................................................................. 423
27.0 Electrical Characteristics ......................................................................................................................................................... 427
28.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 467
29.0 Packaging Information............................................................................................................................................................. 523
Appendix A: Revision History............................................................................................................................................................ 545
Appendix B: Device Differences........................................................................................................................................................ 546
Index ................................................................................................................................................................................................. 547
The Microchip Web Site .................................................................................................................................................................... 557
Customer Change Notification Service ............................................................................................................................................. 557
Customer Support ............................................................................................................................................................................. 557
Reader Response ............................................................................................................................................................................. 558
Product Identification System ........................................................................................................................................................... 559
DS41412F-page 11
PIC18(L)F2X/4XK22
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS41412F-page 12
PIC18(L)F2X/4XK22
1.0
DEVICE OVERVIEW
PIC18LF23K22
PIC18F24K22
PIC18LF24K22
PIC18F25K22
PIC18LF25K22
PIC18F26K22
PIC18LF26K22
PIC18F43K22
PIC18LF43K22
PIC18F44K22
PIC18LF44K22
PIC18F45K22
PIC18LF45K22
PIC18F46K22
PIC18LF46K22
1.1
1.1.1
1.1.2
DS41412F-page 13
PIC18(L)F2X/4XK22
1.2
DS41412F-page 14
1.3
Devices in the PIC18(L)F2X/4XK22 family are available in 28-pin and 40/44-pin packages. The block diagram for the device family is shown in Figure 1-1.
The devices have the following differences:
1.
2.
3.
4.
5.
6.
7.
A, B, C, E(1)
A, B, C, E(1)
Yes
Yes
Yes
Programmable
High/Low-Voltage Detect (HLVD)
Note
1:
Operating Frequency
Instruction Set
DC - 64 MHz
75 Instructions;
83 with Extended Instruction Set enabled
POR, BOR,
RESET Instruction,
Stack Overflow,
Stack Underflow
(PWRT, OST),
MCLR, WDT
Yes
40-pin PDIP
40-pin UQFN
44-pin QFN
44-pin TQFP
2 internal
28 input
A, B, C, D, E
256
512
4096
8192
PIC18F43K22
PIC18LF43K22
2 MSSP,
2 EUSART
SR Latch
Serial Communications
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
2 internal
17 input
A, B, C, E(1)
33
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
2 internal
17 input
3896
1024
Timers (16-bit)
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin UQFN
2 internal
17 input
A, B, C, E(1)
256
1536
32768
65536
PIC18F26K22
PIC18LF26K22
Interrupt Sources
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin UQFN
Packages
768
16384
32768
PIC18F25K22
PIC18LF25K22
40-pin PDIP
40-pin UQFN
44-pin QFN
44-pin TQFP
2 internal
28 input
A, B, C, D, E
256
768
8192
16384
PIC18F44K22
PIC18LF44K22
40-pin PDIP
40-pin UQFN
44-pin QFN
44-pin TQFP
2 internal
28 input
A, B, C, D, E
256
1536
16384
32768
PIC18F45K22
PIC18LF45K22
40-pin PDIP
40-pin UQFN
44-pin QFN
44-pin TQFP
2 internal
28 input
A, B, C, D, E
1024
3896
32768
65536
PIC18F46K22
PIC18LF46K22
TABLE 1-1:
I/O Ports
256
512
256
8192
4096
16384
8192
PIC18F24K22
PIC18LF24K22
Program Memory
(Instructions)
PIC18F23K22
PIC18LF23K22
Features
PIC18(L)F2X/4XK22
DEVICE FEATURES
DS41412F-page 15
PIC18(L)F2X/4XK22
FIGURE 1-1:
Table Pointer<21>
Data Latch
inc/dec logic
Data Memory
PCLATU PCLATH
21
PORTA
Address Latch
20
PCU PCH PCL
Program Counter
RA0:RA7
12
Data Address<12>
31-Level Stack
4
BSR
Address Latch
Program Memory
(8/16/32/64 Kbytes)
STKPTR
12
FSR0
FSR1
FSR2
Data Latch
8
4
Access
Bank
PORTB
12
RB0:RB7
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
Instruction Bus <16>
PORTC
RC0:RC7
IR
8
Instruction
Decode and
Control
State machine
control signals
PRODH PRODL
PORTD
8 x 8 Multiply
8
W
BITOP
8
Internal
Oscillator
Block
OSC1(2)
(2)
OSC2
LFINTOSC
Oscillator
SOSCI
16 MHz
Oscillator
SOSCO
Single-Supply
Programming
In-Circuit
Debugger
MCLR(1)
BOR
HLVD
FVR
DAC
Note
Comparators
C1/C2
Data
EEPROM
ECCP1
ECCP2(3)
ECCP3
Power-up
Timer
RD0:RD7
PORTE
Oscillator
Start-up Timer
Power-on
Reset
ALU<8>
RE0:RE2
RE3(1)
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
Precision
Band Gap
Reference
FVR
Timer0
Timer1
Timer3
Timer5
Timer2
Timer4
Timer6
CTMU
DAC
CCP4
CCP5
MSSP1
MSSP2
EUSART1
EUSART2
SR Latch
ADC
10-bit
FVR
1:
2:
OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 Oscillator Module (With Fail-Safe Clock Monitor) for additional information.
3:
DS41412F-page 16
PIC18(L)F2X/4XK22
TABLE 1-2:
Pin Number
PDIP,
SOIC
QFN,
UQFN
27
28
10
Legend:
Note 1:
2:
Pin Name
Pin
Type
Buffer
Type
Description
RA0/C12IN0-/AN0
RA0
I/O
TTL
C12IN0-
Analog
Digital I/O.
AN0
Analog
Analog input 0.
RA1/C12IN1-/AN1
RA1
I/O
TTL
C12IN1-
Analog
Digital I/O.
AN1
Analog
Analog input 1.
RA2/C2IN+/AN2/DACOUT/VREFRA2
I/O
TTL
C2IN+
Analog
Digital I/O.
Comparator C2 non-inverting input.
AN2
Analog
Analog input 2.
DACOUT
Analog
VREF-
Analog
RA3/C1IN+/AN3/VREF+
RA3
I/O
TTL
C1IN+
Analog
Digital I/O.
Comparator C1 non-inverting input.
AN3
Analog
Analog input 3.
VREF+
Analog
RA4
I/O
ST
RA4/CCP5/C1OUT/SRQ/T0CKI
Digital I/O.
CCP5
I/O
ST
C1OUT
CMOS
SRQ
TTL
SR latch Q output.
T0CKI
ST
Comparator C1 output.
RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4
RA5
I/O
TTL
C2OUT
CMOS
SRNQ
TTL
SR latch Q output.
Comparator C2 output.
SS1
TTL
HLVDIN
Analog
AN4
Analog
Analog input 4.
TTL
RA6/CLKO/OSC2
RA6
I/O
CLKO
Digital I/O.
In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
OSC2
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
DS41412F-page 17
PIC18(L)F2X/4XK22
TABLE 1-2:
Pin Number
PDIP,
SOIC
QFN,
UQFN
21
18
22
19
23
20
24
21
Legend:
Note 1:
2:
Pin Name
Pin
Type
Buffer
Type
Description
RA7/CLKI/OSC1
RA7
I/O
TTL
CLKI
CMOS
Digital I/O.
OSC1
ST
RB0/INT0/CCP4/FLT0/SRI/SS2/AN12
RB0
I/O
TTL
Digital I/O.
INT0
ST
External interrupt 0.
CCP4
I/O
ST
FLT0
ST
SRI
ST
SR latch input.
SS2
TTL
AN12
Analog
RB1/INT1/P1C/SCK2/SCL2/C12IN3-/AN10
RB1
I/O
TTL
Digital I/O.
INT1
ST
External interrupt 1.
P1C
CMOS
SCK2
I/O
ST
SCL2
I/O
ST
C12IN3-
Analog
AN10
Analog
RB2/INT2/CTED1/P1B/SDI2/SDA2/AN8
RB2
I/O
TTL
Digital I/O.
INT2
ST
External interrupt 2.
CTED1
ST
P1B
CMOS
SDI2
ST
SDA2
I/O
ST
AN8
Analog
Analog input 8.
RB3/CTED2/P2A/CCP2/SDO2/C12IN2-/AN9
RB3
I/O
TTL
CTED2
ST
Digital I/O.
P2A
CMOS
CCP2(2)
I/O
ST
SDO2
C12IN2-
Analog
AN9
Analog
Analog input 9.
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
DS41412F-page 18
PIC18(L)F2X/4XK22
TABLE 1-2:
Pin Number
PDIP,
SOIC
QFN,
UQFN
25
22
26
23
Pin Name
24
28
25
11
12
Note 1:
2:
Description
RB4
I/O
TTL
Digital I/O.
IOC0
TTL
Interrupt-on-change pin.
P1D
CMOS
T5G
ST
AN11
Analog
RB5/IOC1/P2B/P3A/CCP3/T3CKI/T1G/AN13
I/O
TTL
Digital I/O.
Interrupt-on-change pin.
IOC1
TTL
P2B(1)
CMOS
P3A(1)
CMOS
CCP3(1)
I/O
ST
T3CKI(2)
ST
T1G
ST
AN13
Analog
RB6/IOC2/TX2/CK2/PGC
RB6
I/O
TTL
Digital I/O.
IOC2
TTL
Interrupt-on-change pin.
TX2
CK2
I/O
ST
PGC
I/O
ST
RB7/IOC3/RX2/DT2/PGD
RB7
I/O
TTL
Digital I/O.
IOC3
TTL
Interrupt-on-change pin.
RX2
ST
DT2
I/O
ST
PGD
I/O
ST
RC0/P2B/T3CKI/T3G/T1CKI/SOSCO
RC0
I/O
TTL
P2B(2)
CMOS
T3CKI(1)
ST
T3G
ST
T1CKI
ST
SOSCO
I/O
TTL
RC1/P2A/CCP2/SOSCI
RC1
Legend:
Buffer
Type
RB4/IOC0/P1D/T5G/AN11
RB5
27
Pin
Type
P2A
CMOS
CCP2(1)
I/O
ST
SOSCI
Analog
Digital I/O.
Enhanced CCP2 PWM output.
Capture 2 input/Compare 2 output/PWM 2 output.
Secondary oscillator input.
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
DS41412F-page 19
PIC18(L)F2X/4XK22
TABLE 1-2:
Pin Number
PDIP,
SOIC
QFN,
UQFN
Pin Name
13
10
RC2/CTPLS/P1A/CCP1/T5CKI/AN14
14
11
15
12
16
13
17
14
15
26
Legend:
Note 1:
2:
Buffer
Type
Description
RC2
I/O
TTL
CTPLS
P1A
CMOS
Digital I/O.
CCP1
I/O
ST
T5CKI
ST
AN14
Analog
RC3/SCK1/SCL1/AN15
RC3
I/O
TTL
Digital I/O.
SCK1
I/O
ST
SCL1
I/O
ST
AN15
Analog
RC4/SDI1/SDA1/AN16
RC4
I/O
TTL
Digital I/O.
SDI1
ST
SDA1
I/O
ST
AN16
Analog
RC5/SDO1/AN17
RC5
I/O
TTL
SDO1
AN17
Analog
Digital I/O.
SPI data out (MSSP).
Analog input 17.
RC6/P3A/CCP3/TX1/CK1/AN18
RC6
I/O
TTL
P3A(2)
CMOS
CCP3
18
Pin
Type
(2)
Digital I/O.
Enhanced CCP3 PWM output.
I/O
ST
TX1
CK1
I/O
ST
AN18
Analog
RC7/P3B/RX1/DT1/AN19
RC7
I/O
TTL
P3B
CMOS
Digital I/O.
RX1
ST
DT1
I/O
ST
AN19
Analog
RE3
ST
VPP
MCLR
RE3/VPP/MCLR
Digital input.
Programming voltage input.
ST
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
DS41412F-page 20
PIC18(L)F2X/4XK22
TABLE 1-2:
Pin Number
QFN,
UQFN
Pin Name
Pin
Type
Buffer
Type
20
17
VDD
8, 19
5, 16
VSS
PDIP,
SOIC
Legend:
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
Note 1:
2:
TABLE 1-3:
Pin Number
Pin Name
PDIP
TQFP
QFN
UQFN
19
19
17
20
21
22
23
Legend:
Note
Description
20
21
22
23
18
19
20
21
Pin
Type
Buffer
Type
Description
RA0/C12IN0-/AN0
RA0
I/O
C12IN0-
TTL
Digital I/O.
AN0
RA1/C12IN1-/AN1
RA1
I/O
C12IN1-
TTL
Digital I/O.
AN1
RA2/C2IN+/AN2/DACOUT/VREFRA2
I/O
C2IN+
TTL
Digital I/O.
AN2
DACOUT
VREF-
RA3/C1IN+/AN3/VREF+
RA3
I/O
C1IN+
TTL
Digital I/O.
AN3
VREF+
RA4/C1OUT/SRQ/T0CKI
RA4
I/O
C1OUT
ST
Digital I/O.
SRQ
TTL
SR latch Q output.
T0CKI
ST
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.
DS41412F-page 21
PIC18(L)F2X/4XK22
TABLE 1-3:
Pin Number
Pin Name
PDIP
TQFP
QFN
UQFN
24
24
22
14
13
33
34
35
36
31
30
32
10
10
11
Legend:
Note
33
11
12
29
28
10
11
Pin
Type
Buffer
Type
Description
RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4
RA5
I/O
TTL
Digital I/O.
C2OUT
SRNQ
TTL
SR latch Q output.
SS1
TTL
HLVDIN
AN4
RA6/CLKO/OSC2
RA6
I/O
TTL
CLKO
Digital I/O.
OSC2
RA7/CLKI/OSC1
RA7
I/O
CLKI
TTL
Digital I/O.
OSC1
ST
RB0/INT0/FLT0/SRI/AN12
RB0
I/O
TTL
Digital I/O.
INT0
ST
External interrupt 0.
FLT0
ST
SRI
ST
SR latch input.
AN12
RB1/INT1/C12IN3-/AN10
RB1
I/O
TTL
Digital I/O.
INT1
ST
External interrupt 1.
C12IN3-
AN10
RB2/INT2/CTED1/AN8
RB2
I/O
TTL
INT2
ST
Digital I/O.
External interrupt 2.
CTED1
ST
AN8
RB3/CTED2/P2A/CCP2/C12IN2-/AN9
RB3
I/O
TTL
Digital I/O.
CTED2
ST
P2A(2)
CCP2(2)
I/O
C12IN2-
AN9
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.
DS41412F-page 22
PIC18(L)F2X/4XK22
TABLE 1-3:
Pin Number
Pin
Type
Buffer
Type
RB4
I/O
TTL
Digital I/O.
IOC0
TTL
Interrupt-on-change pin.
T5G
ST
AN11
Pin Name
PDIP
TQFP
QFN
UQFN
37
14
14
12
38
15
15
13
RB4/IOC0/T5G/AN11
40
15
16
16
17
32
35
16
17
34
35
14
15
30
31
RB5
I/O
TTL
Digital I/O.
IOC1
TTL
Interrupt-on-change pin.
P3A(1)
CCP3(1)
I/O
ST
(2)
36
Legend:
Note
36
32
ST
T1G
ST
AN13
RB6/IOC2/PGC
RB6
I/O
TTL
Digital I/O.
IOC2
TTL
Interrupt-on-change pin.
PGC
I/O
ST
RB7/IOC3/PGD
RB7
I/O
TTL
Digital I/O.
IOC3
TTL
Interrupt-on-change pin.
PGD
I/O
ST
ST
Digital I/O.
RC0/P2B/T3CKI/T3G/T1CKI/SOSCO
RC0
I/O
P2B(2)
T3CKI(1)
ST
T3G
ST
T1CKI
ST
SOSCO
I/O
ST
Digital I/O.
RC1/P2A/CCP2/SOSCI
RC1
17
RB5/IOC1/P3A/CCP3/T3CKI/T1G/AN13
T3CKI
39
Description
P2A(1)
CCP2(1)
I/O
SOSCI
RC2/CTPLS/P1A/CCP1/T5CKI/AN14
RC2
I/O
ST
Digital I/O.
CTPLS
P1A
CCP1
I/O
T5CKI
AN14
ST
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.
DS41412F-page 23
PIC18(L)F2X/4XK22
TABLE 1-3:
Pin Number
Pin
Type
Buffer
Type
RC3
I/O
ST
Digital I/O.
SCK1
I/O
ST
SCL1
I/O
ST
AN15
Pin Name
PDIP
TQFP
QFN
UQFN
18
37
37
33
23
24
25
26
19
20
42
43
44
43
44
38
39
Legend:
Note
42
38
39
38
39
40
34
35
Description
RC3/SCK1/SCL1/AN15
RC4/SDI1/SDA1/AN16
RC4
I/O
ST
Digital I/O.
SDI1
ST
SDA1
I/O
ST
AN16
RC5/SDO1/AN17
RC5
I/O
ST
Digital I/O.
SDO1
AN17
RC6/TX1/CK1/AN18
RC6
I/O
ST
Digital I/O.
TX1
CK1
I/O
ST
AN18
RC7/RX1/DT1/AN19
RC7
I/O
ST
Digital I/O.
RX1
ST
DT1
I/O
ST
AN19
RD0/SCK2/SCL2/AN20
RD0
I/O
ST
Digital I/O.
SCK2
I/O
ST
SCL2
I/O
ST
AN20
RD1/CCP4/SDI2/SDA2/AN21
RD1
I/O
ST
Digital I/O.
CCP4
I/O
ST
SDI2
ST
SDA2
I/O
ST
AN21
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.
DS41412F-page 24
PIC18(L)F2X/4XK22
TABLE 1-3:
Pin Number
Pin
Type
Buffer
Type
RD2
I/O
ST
P2B(1)
AN22
Pin Name
PDIP
TQFP
QFN
UQFN
21
40
40
36
22
27
28
29
30
41
Note
25
26
Legend:
41
25
26
37
23
24
Description
RD2/P2B/AN22
Digital I/O
RD3/P2C/SS2/AN23
RD3
I/O
P2C
SS2
AN23
ST
Digital I/O.
RD4/P2D/SDO2/AN24
RD4
I/O
P2D
SDO2
AN24
ST
Digital I/O.
RD5/P1B/AN25
RD5
I/O
P1B
ST
Digital I/O.
AN25
RD6/P1C/TX2/CK2/AN26
RD6
I/O
P1C
ST
Digital I/O.
TX2
CK2
I/O
ST
AN26
RD7/P1D/RX2/DT2/AN27
RD7
I/O
P1D
ST
Digital I/O.
RX2
ST
DT2
I/O
ST
AN27
RE0/P3A/CCP3/AN5
RE0
I/O
P3A(2)
CCP3(2)
I/O
AN5
ST
Digital I/O.
RE1/P3B/AN6
RE1
I/O
P3B
ST
Digital I/O.
AN6
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.
DS41412F-page 25
PIC18(L)F2X/4XK22
TABLE 1-3:
Pin Number
Pin
Type
Buffer
Type
RE2
I/O
ST
Digital I/O.
CCP5
I/O
ST
AN7
Pin Name
PDIP
TQFP
QFN
UQFN
10
27
27
25
18
18
16
Description
RE2/CCP5/AN7
RE3/VPP/MCLR
RE3
ST
Digital input.
VPP
MCLR
ST
11,32
7, 28
7, 8,
28, 29
7, 26
VDD
12,31
6, 29
6,30,
31
6, 27
VSS
12,13,
33,34
13
Legend:
Note
NC
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.
DS41412F-page 26
PIC18(L)F2X/4XK22
2.0
2.1
Overview
RC
LP
XT
INTOSC
HS
EC
External Resistor/Capacitor
Low-Power Crystal
Crystal/Resonator
Internal Oscillator
High-Speed Crystal/Resonator
External Clock
PRICLKEN (CONFIG1H<5>)
PRISD (OSCCON2<2>)
PLLCFG (CONFIG1H<4>)
PLLEN (OSCTUNE<6>)
HFOFST (CONFIG3H<3>)
IRCF<2:0> (OSCCON<6:4>)
MFIOSEL (OSCCON2<4>)
INTSRC (OSCTUNE<7>)
DS41412E-page 27
PIC18(L)F2X/4XK22
FIGURE 2-1:
Secondary Oscillator(1)
SOSCO
Secondary
Oscillator
(SOSC)
SOSCI
Low-Power Mode
Event Switch
(SCS<1:0>)
SOSCOUT
Secondary
Oscillator
PRICLKEN
PRISD
OSC1
FOSC<3:0>(5)
Primary
Oscillator(2)
( OSC)
Primary Oscillator
INTOSC
4xPLL
Primary
Clock
00
INTOSC
EN
OSC2
01
PLL_Select(3) (4)
1x
Internal Oscillator
IRCF<2:0>
MFIOSEL
INTSRC
3
INTOSC
Divide
Circuit
HF-16 MHZ
HF-8 MHZ
HF-4 MHZ
HF-2 MHZ
HF-1 MHZ
HF-500 kHZ
HF-250 kHZ
HF-31.25 kHZ
MFINTOSC
(500 kHz)
MF-500 kHZ
MF-250 kHZ
MF-31.25 kHZ
LFINTOSC
HFINTOSC
(16 MHz)
INTOSC
LF-31.25 kHz
(31.25 kHz)
DS41412E-page 28
PIC18(L)F2X/4XK22
2.2
Oscillator Control
2.2.1
2.2.3
2.2.4
POWER MANAGEMENT
2.2.2
INTERNAL FREQUENCY
SELECTION
DS41412E-page 29
PIC18(L)F2X/4XK22
FIGURE 2-2:
INTERNAL OSCILLATOR
MUX BLOCK DIAGRAM
FIGURE 2-3:
FOSC<3:0> = 100x
PLLCFG
IRCF<2:0>
MFIOSEL
INTSRC
3
HF-16 MHZ
HF-8 MHZ
HF-4 MHZ
HF-2 MHZ
HF-1 MHZ
PLLEN
PLL_Select
111
110
101
100
011
MF-500 KHZ
HF-500 KHZ
500 kHZ
010
250 kHZ
001
INTOSC
MF-250 KHZ
HF-250 KHZ
HF-31.25 KHZ 11
MF-31.25 KHZ 10
LF-31.25 KHZ
0X
TABLE 2-1:
PLL_SELECT BLOCK
DIAGRAM
31.25 kHZ
000
FOSC<3:0>
PLLCFG
PLLEN
PLL_Select
0000-1111
0000-0111
1010-1111
1000-1001
DS41412E-page 30
PIC18(L)F2X/4XK22
FIGURE 2-4:
SOSCEN
EN
SOSCOUT
Secondary
Oscillator
SOSCO
T1CKI
T3G
T3CKI
T1CLK_EXT_SRC
SOSCEN
0
T1SOSCEN
SOSCEN
T3G
SOSCEN
1
T3CLK_EXT_SRC
0
0
T3CKI
T1G
T3SOSCEN
T3CMX
T1G
T5CLK_EXT_SRC
0
T5CKI
T5SOSCEN
T5G
T5G
DS41412E-page 31
PIC18(L)F2X/4XK22
2.3
REGISTER 2-1:
R/W-0
IDLEN
R/W-1
R/W-1
IRCF<2:0>
R-q
R-0
OSTS(1)
HFIOFS
R/W-0
R/W-0
SCS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
q = depends on condition
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
bit 3
bit 2
bit 1-0
Note 1:
2:
3:
DS41412E-page 32
PIC18(L)F2X/4XK22
REGISTER 2-2:
R-0/0
R-0/q
U-0
R/W-0/0
R/W-0/u
R/W-1/1
R-x/u
R-0/0
PLLRDY
SOSCRUN
MFIOSEL
SOSCGO(1)
PRISD
MFIOFS
LFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
q = depends on condition
bit 6
bit 5
Unimplemented: Read as 0.
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS41412E-page 33
PIC18(L)F2X/4XK22
2.4
2.5
2.5.1
TABLE 2-2:
Switch From
Switch To
Frequency
Oscillator Delay
Sleep/POR
LFINTOSC
MFINTOSC
HFINTOSC
31.25 kHz
31.25 kHz to 500 kHz
31.25 kHz to 16 MHz
Sleep/POR
EC, RC
DC 64 MHz
2 instruction cycles
EC, RC
DC 64 MHz
1 cycle of each
Sleep/POR
LP, XT, HS
32 kHz to 40 MHz
Sleep/POR
4xPLL
32 MHz to 64 MHz
LFINTOSC
HFINTOSC
2.5.2
EC MODE
1 s (approx.)
FIGURE 2-5:
Clock from
Ext. System
PIC MCU
I/O
Note 1:
OSC2/CLKOUT(1)
DS41412E-page 34
PIC18(L)F2X/4XK22
2.5.3
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, refer to the
following Microchip Application Notes:
AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC and PIC
Devices (DS00826)
AN849, Basic PIC Oscillator Design
(DS00849)
AN943, Practical PIC Oscillator
Analysis and Design (DS00943)
AN949, Making Your Oscillator Work
(DS00949)
FIGURE 2-6:
FIGURE 2-7:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC MCU
OSC1/CLKIN
C1
To Internal
Logic
PIC MCU
RP(3)
OSC1/CLKIN
C1
Note 1:
2:
Sleep
To Internal
Logic
Quartz
Crystal
C2
RF(2)
RS(1)
RF(2)
Sleep
OSC2/CLKOUT
C2 Ceramic
RS(1)
Resonator
OSC2/CLKOUT
DS41412E-page 35
PIC18(L)F2X/4XK22
2.5.4
EXTERNAL RC MODES
2.6
2.5.4.1
FIGURE 2-8:
EXTERNAL RC MODES
VDD
PIC MCU
REXT
OSC1/CLKIN
Internal
Clock
CEXT
VSS
FOSC/4 or
I/O(2)
OSC2/CLKOUT(1)
2.5.4.2
RC Mode
RCIO Mode
2.
3.
2.6.1
DS41412E-page 36
PIC18(L)F2X/4XK22
2.6.1.1
OSCTUNE Register
2.7
REGISTER 2-3:
R/W-0
R/W-0
INTSRC
PLLEN(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-0
TUN<5:0>: Frequency Tuning bits use to adjust MFINTOSC and HFINTOSC frequencies
011111 = Maximum frequency
011110 =
000001 =
000000 = Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated
frequency.
111111 =
Note 1:
The PLLEN bit is active for all the primary clock sources (internal or external) and is designed to operate
with clock frequencies between 4 MHz and 16 MHz.
DS41412E-page 37
PIC18(L)F2X/4XK22
2.7.1
LFINTOSC
2.7.2
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz (default after Reset)
500 kHz (MFINTOSC or HFINTOSC)
250 kHz (MFINTOSC or HFINTOSC)
31 kHz (LFINTOSC, MFINTOSC or HFINTOSC)
2.7.3
2.7.3.1
2.7.3.2
2.7.3.3
DS41412E-page 38
PIC18(L)F2X/4XK22
2.8
2.8.1
2.8.2
DS41412E-page 39
PIC18(L)F2X/4XK22
2.9
DS41412E-page 40
2.10
Power-up Delays
PIC18(L)F2X/4XK22
TABLE 2-3:
OSC Mode
OSC1 Pin
OSC2 Pin
RC, INTOSC with CLKOUT Floating, external resistor should pull high
RC with IO
INTOSC with IO
EC with IO
EC with CLKOUT
LP, XT, HS
Note:
2.11
See Table 4-2 in Section 4.0 Reset for time-outs due to Sleep and MCLR Reset.
Clock Switching
2.11.1
2.11.2
DS41412E-page 41
PIC18(L)F2X/4XK22
2.11.3
4.
5.
6.
7.
2.12
2.12.1
DS41412E-page 42
PIC18(L)F2X/4XK22
2.12.2
1.
2.
3.
4.
5.
6.
TWO-SPEED START-UP
SEQUENCE
2.12.3
FIGURE 2-9:
High Speed
Old Clock
Start-up Time(1)
Clock Sync
Running
New Clock
New Clk Ready
IRCF <2:0> Select Old
Select New
System Clock
Low Speed
High Speed
Old Clock
Start-up Time(1)
Clock Sync
Running
New Clock
New Clk Ready
IRCF <2:0> Select Old
Select New
System Clock
Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.
DS41412E-page 43
PIC18(L)F2X/4XK22
2.13
2.13.3
FIGURE 2-10:
External
Clock
LFINTOSC
Oscillator
64
31 kHz
(~32 s)
488 Hz
(~2 ms)
2.13.1
Note:
Note:
When the device is configured for FailSafe clock monitoring in either HS, XT, or
LS Oscillator modes then the IESO configuration bit should also be set so that the
clock will automatically switch from the
internal clock to the external oscillator
when the OST times out.
Clock
Failure
Detected
FAIL-SAFE DETECTION
2.13.2
Any Reset
By toggling the SCS1 bit of the OSCCON register
Sample Clock
2.13.4
FAIL-SAFE OPERATION
DS41412E-page 44
PIC18(L)F2X/4XK22
FIGURE 2-11:
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
TABLE 2-4:
Name
INTCON
IPR2
OSCCON
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Bit 6
GIE/GIEH PEIE/GIEL
OSCFIP
C1IP
IDLEN
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP CCP2IP
129
OSTS
HFIOFS
SCS<1:0>
32
PRISD
MFIOFS LFIOFS
33
IRCF<2:0>
MFIOSEL SOSCGO
OSCCON2
PLLRDY SOSCRUN
OSCTUNE
INTSRC
PLLEN
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE CCP2IE
125
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF CCP2IF
120
TUN<5:0>
37
Legend: = unimplemented locations, read as 0. Shaded bits are not used by clock sources.
TABLE 2-5:
Name
Bit 6
Bit 5
CONFIG1H
IESO
CONFIG2L
CONFIG3H
MCLRE
P2BMX
Bit 4
Bit 3
Bit 1
Bit 0
FOSC<3:0>
BORV<1:0>
T3CMX
Bit 2
BOREN<1:0>
Register
on Page
357
PWRTEN
358
360
Legend: = unimplemented locations, read as 0. Shaded bits are not used for clock sources.
DS41412E-page 45
PIC18(L)F2X/4XK22
NOTES:
DS41412E-page 46
PIC18(L)F2X/4XK22
3.0
POWER-MANAGED MODES
3.1.1
CLOCK SOURCES
3.1.2
Run modes
Idle modes
Sleep mode
3.1
ENTERING POWER-MANAGED
MODES
TABLE 3-1:
POWER-MANAGED MODES
OSCCON Bits
Mode
(1)
IDLEN
Module Clocking
Available Clock and Oscillator Source
SCS<1:0>
CPU
Peripherals
N/A
Off
Off
PRI_RUN
N/A
00
Clocked
Clocked
SEC_RUN
N/A
01
Clocked
Clocked
RC_RUN
N/A
1x
Clocked
Clocked
PRI_IDLE
00
Off
Clocked
SEC_IDLE
01
Off
Clocked
RC_IDLE
1x
Off
Clocked
Sleep
Note 1:
2:
DS41412F-page 47
PIC18(L)F2X/4XK22
3.1.3
3.2
Run Modes
3.2.1
PRI_RUN MODE
3.2.2
SEC_RUN MODE
Note:
3.2.3
RC_RUN MODE
DS41412F-page 48
PIC18(L)F2X/4XK22
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-3). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
FIGURE 3-1:
Q2
1
SOSCI
n-1
Q3
Q4
Q1
Q2
Q3
Clock Transition(1)
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-2:
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
SOSC
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
n-1 n
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter
SCS<1:0> bits Changed
PC + 2
PC
PC + 4
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
DS41412F-page 49
PIC18(L)F2X/4XK22
TABLE 3-2:
IRCF<2:0>
INTSRC
MFIOSEL
Selected Oscillator
000
LFINTOSC
LFIOFS = 1
000
HFINTOSC
HFIOFS = 1
000
MFINTOSC
MFIOFS = 1
010 or 001
HFINTOSC
HFIOFS = 1
010 or 001
MFINTOSC
MFIOFS = 1
011 111
HFINTOSC
HFIOFS = 1
FIGURE 3-3:
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTOSC
Multiplexer
OSC1
TOST(1)
TPLL(1)
1
PLL Clock
Output
n-1 n
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC
SCS<1:0> bits Changed
PC + 4
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
DS41412F-page 50
PIC18(L)F2X/4XK22
3.3
Sleep Mode
3.4
Idle Modes
If the WDT is selected, the LFINTOSC source will continue to operate. If the SOSC oscillator is enabled, it will
also continue to run.
FIGURE 3-4:
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
DS41412F-page 51
PIC18(L)F2X/4XK22
FIGURE 3-5:
Q1
OSC1
TOST(1)
PLL Clock
Output
TPLL(1)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
PC + 2
PC + 4
PC + 6
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
3.4.1
3.4.2
PRI_IDLE MODE
FIGURE 3-6:
SEC_IDLE MODE
Q3
Q2
Q4
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
DS41412F-page 52
PC
PC + 2
PIC18(L)F2X/4XK22
FIGURE 3-7:
Q2
Q3
Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
3.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator
block from the HFINTOSC multiplexer output. This
mode allows for controllable power conservation during
Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. It is recommended
that SCS0 also be cleared, although its value is
ignored, to maintain software compatibility with future
devices. The HFINTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the HFINTOSC multiplexer,
the primary oscillator is shut down and the OSTS bit is
cleared.
DS41412F-page 53
PIC18(L)F2X/4XK22
3.5
3.5.1
EXIT BY INTERRUPT
3.5.2
3.5.3
EXIT BY RESET
3.5.4
DS41412F-page 54
PIC18(L)F2X/4XK22
3.6
3.7
REGISTER 3-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
UART2MD
UART1MD
TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 55
PIC18(L)F2X/4XK22
REGISTER 3-2:
R/W-0
R/W-0
MSSP2MD
MSSP1MD
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 56
PIC18(L)F2X/4XK22
REGISTER 3-3:
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMUMD
CMP2MD
CMP1MD
ADCMD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS41412F-page 57
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 58
PIC18(L)F2X/4XK22
4.0
RESET
FIGURE 4-1:
4.1
RCON Register
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD
Detect
POR
VDD
Brown-out
Reset
BOREN
OST/PWRT
OST(2) 1024 Cycles
10-bit Ripple Counter
Chip_Reset
R
OSC1
32 s
LFINTOSC
PWRT(2) 65.5 ms
11-bit Ripple Counter
Enable PWRT
Enable OST(1)
Note 1:
2:
DS41412F-page 59
PIC18(L)F2X/4XK22
4.2
REGISTER 4-1:
R/W-0/0
IPEN
SBOREN
(1)
U-0
R/W-1/q
RI
R-1/q
R-1/q
TO
PD
R/W-q/u
(2)
POR
bit 7
R/W-0/q
BOR
bit 0
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
u = unchanged
q = depends on condition
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
Note 1: Brown-out Reset is indicated when BOR is 0 and POR is 1 (assuming that both POR and BOR were set
to 1 by firmware immediately after POR).
2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
DS41412F-page 60
PIC18(L)F2X/4XK22
4.3
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
VDD
PIC MCU
D
4.4
R1
MCLR
C
Note 1:
2:
3:
DS41412F-page 61
PIC18(L)F2X/4XK22
4.5
4.5.1
DETECTING BOR
DS41412F-page 62
4.5.2
4.5.3
4.5.4
PIC18(L)F2X/4XK22
TABLE 4-1:
BOR CONFIGURATIONS
BOR Configuration
BOREN1
BOREN0
Status of
SBOREN
(RCON<6>)
Unavailable
Available
BOR Operation
BOR disabled; must be enabled by reprogramming the Configuration bits.
BOR enabled by software; operation controlled by SBOREN.
Unavailable
BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode.
Unavailable
4.6
4.6.1
4.6.2
4.6.3
4.6.4
TIME-OUT SEQUENCE
DS41412F-page 63
PIC18(L)F2X/4XK22
TABLE 4-2:
Oscillator
Configuration
HSPLL
Exit from
Power-Managed Mode
PWRTEN = 0
66 ms
(1)
+ 1024 TOSC + 2
ms(2)
HS, XT, LP
1024 TOSC
1024 TOSC
EC, ECIO
(1)
66 ms
RC, RCIO
66 ms(1)
(1)
INTIO1, INTIO2
66 ms
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4:
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS41412F-page 64
PIC18(L)F2X/4XK22
FIGURE 4-5:
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS41412F-page 65
PIC18(L)F2X/4XK22
FIGURE 4-7:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
DS41412F-page 66
PIC18(L)F2X/4XK22
4.7
TABLE 4-3:
Condition
RCON Register
SBOREN
RI
TO
PD
STKPTR Register
POR BOR STKFUL
STKUNF
Power-on Reset
0000h
RESET Instruction
0000h
u(2)
0000h
u(2)
0000h
u(2)
0000h
u(2)
0000h
u(2)
0000h
u(2)
0000h
u(2)
0000h
(2)
0000h
u(2)
PC + 2
u(2)
PC + 2(1)
u(2)
Brown-out Reset
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is 1 for SBOREN and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is 0.
TABLE 4-4:
Name
RCON
STKPTR
Bit 6
Bit 5
Bit 4
Bit 3
IPEN
SBOREN
RI
TO
STKFUL
STKUNF
Bit 2
Bit 1
Bit 0
PD
POR
BOR
STKPTR<4:0>
Register
on Page
60
72
Legend: = unimplemented locations, read as 0. Shaded bits are not used for Resets.
DS41412F-page 67
PIC18(L)F2X/4XK22
TABLE 4-5:
Name
Bit 7
Bit 6
Bit 5
CONFIG2L
CONFIG2H
Bit 4
Bit 3
BORV<1:0>
Bit 2
BOREN<1:0>
WDPS<3:0>
CONFIG3H
MCLRE
P2BMX
T3CMX
CONFIG4L
DEBUG
XINST
Bit 0
Register
on Page
PWRTEN
358
WDTEN<1:0>
HFOFST CCP3MX
Bit 1
LVP
359
PBADEN
CCP2MX
360
STRVEN
361
Legend: = unimplemented locations, read as 0. Shaded bits are not used for Resets.
DS41412F-page 68
PIC18(L)F2X/4XK22
5.0
MEMORY ORGANIZATION
5.1
DS41412F-page 69
PIC18(L)F2X/4XK22
FIGURE 5-1:
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 31
2000h
0000h
0008h
0018h
On-Chip
Program Memory
3FFFh
4000h
PIC18(L)F23K22
On-Chip
Program Memory
PIC18(L)F43K22
On-Chip
Program Memory
1FFFh
Reset Vector
On-Chip
Program Memory
PIC18(L)F24K22
PIC18(L)F44K22
7FFFh
8000h
PIC18(L)F25K22
PIC18(L)F45K22
Read 0
Read 0
Read 0
FFFFh
10000h
PIC18(L)F26K22
PIC18(L)F46K22
Read 0
5.1.1
PROGRAM COUNTER
DS41412F-page 70
1FFFFFh
200000h
5.1.2
PIC18(L)F2X/4XK22
A CALL type instruction causes a push onto the stack;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to 00000 after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of 00000; this
is only a Reset value. Status bits indicate if the stack is
full or has overflowed or has underflowed.
FIGURE 5-2:
5.1.2.1
Top-of-Stack Access
Top-of-Stack Registers
TOSU
00h
TOSH
1Ah
5.1.2.2
STKPTR<4:0>
00010
TOSL
34h
Top-of-Stack
Stack Pointer
001A34h
000D58h
00011
00010
00001
00000
DS41412F-page 71
PIC18(L)F2X/4XK22
5.1.2.3
5.2
The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.
REGISTER 5-1:
R/C-0
(1)
STKFUL
STKUNF
U-0
(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STKPTR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4-0
Note 1:
5.2.0.1
5.2.1
DS41412F-page 72
PIC18(L)F2X/4XK22
EXAMPLE 5-1:
RETURN, FAST
SUB1
5.2.2
5.2.2.2
5.2.2.1
Computed GOTO
EXAMPLE 5-2:
ORG
TABLE
MOVF
CALL
nn00h
ADDWF
RETLW
RETLW
RETLW
.
.
.
DS41412F-page 73
PIC18(L)F2X/4XK22
5.3
5.3.2
5.3.1
CLOCKING SCHEME
FIGURE 5-3:
INSTRUCTION FLOW/PIPELINING
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 2
PC + 4
OSC2/CLKOUT
(RC mode)
Execute INST (PC 2)
Fetch INST (PC)
EXAMPLE 5-3:
1. MOVLW 55h
4. BSF
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. BRA
SUB_1
PORTA, BIT3 (Forced NOP)
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is flushed from the pipeline while the new instruction is being fetched and then executed.
DS41412F-page 74
PIC18(L)F2X/4XK22
5.3.3
INSTRUCTIONS IN PROGRAM
MEMORY
FIGURE 5-4:
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Program Memory
Byte Locations
5.3.4
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
Instruction 3:
MOVFF
123h, 456h
TWO-WORD INSTRUCTIONS
EXAMPLE 5-4:
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
0110 0110 0000
1100 0001 0010
1111 0100 0101
0010 0100 0000
0000
0011
0110
0000
Source Code
TSTFSZ
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
ADDWF
REG3
; continue code
0000
0011
0110
0000
Source Code
TSTFSZ
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
CASE 2:
Object Code
0110 0110 0000
1100 0001 0010
1111 0100 0101
0010 0100 0000
DS41412F-page 75
PIC18(L)F2X/4XK22
5.4
Note:
5.4.1
DS41412F-page 76
PIC18(L)F2X/4XK22
FIGURE 5-5:
BSR<3:0>
= 0000
00h
Access RAM
FFh
00h
GPR
Bank 0
= 0001
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
000h
05Fh
060h
0FFh
100h
GPR
Bank 1
= 0010
When a = 0:
FFh
00h
1FFh
200h
FFh
00h
2FFh
300h
FFh
00h
3FFh
400h
FFh
00h
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
6FFh
700h
FFh
00h
7FFh
800h
Bank 2
Bank 3
Bank 4
Bank 5
When a = 1:
The BSR specifies the Bank
used by the instruction.
Bank 6
Bank 7
Bank 8
Bank 9
FFh
00h
Unused
Read 00h
9FFh
A00h
FFh
00h
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
Bank 13 00h
CFFh
D00h
FFh
00h
DFFh
E00h
FFh
00h
EFFh
F00h
F37h
F38h
F5Fh
F60h
Bank 11
Bank 12
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
8FFh
900h
FFh
00h
Bank 10
Access Bank
Bank 14
Bank 15
Unused
SFR(1)
SFR
FFh
FFFh
Note 1:
DS41412F-page 77
PIC18(L)F2X/4XK22
FIGURE 5-6:
BSR<3:0>
= 0000
00h
Access RAM
FFh
00h
GPR
Bank 0
= 0001
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
Bank 2
Bank 4
Bank 5
GPR
FFh
00h
2FFh
300h
FFh
00h
3FFh
400h
FFh
00h
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
6FFh
700h
When a = 1:
The BSR specifies the Bank
used by the instruction.
Bank 6
Access Bank
Access RAM Low
Bank 7
Bank 8
Bank 9
FFh
00h
Unused
Read 00h
8FFh
900h
FFh
00h
9FFh
A00h
FFh
00h
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
Bank 13 00h
CFFh
D00h
FFh
00h
DFFh
E00h
Bank 10
Bank 11
Bank 12
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
7FFh
800h
FFh
00h
Bank 14
FFh
00h
Unused
Bank 15
SFR(1)
EFFh
F00h
F37h
F38h
F5Fh
F60h
SFR
FFh
DS41412F-page 78
1FFh
200h
FFh
00h
Bank 3
000h
05Fh
060h
0FFh
100h
GPR
Bank 1
= 0010
When a = 0:
FFFh
Note 1:
PIC18(L)F2X/4XK22
FIGURE 5-7:
BSR<3:0>
= 0000
00h
Access RAM
FFh
00h
GPR
Bank 0
= 0001
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
Bank 2
Bank 4
Bank 5
1FFh
200h
FFh
00h
Bank 3
000h
05Fh
060h
0FFh
100h
GPR
Bank 1
= 0010
When a = 0:
GPR
FFh
00h
2FFh
300h
When a = 1:
The BSR specifies the Bank
used by the instruction.
GPR
3FFh
400h
FFh
00h
GPR
4FFh
500h
FFh
00h
GPR
FFh
00h
5FFh
600h
FFh
00h
6FFh
700h
Bank 6
Access Bank
Access RAM Low
Bank 7
Bank 8
Bank 9
Bank 10
FFh
00h
7FFh
800h
FFh
00h
8FFh
900h
FFh
00h
Unused
Read 00h
9FFh
A00h
FFh
00h
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
Bank 13 00h
CFFh
D00h
FFh
00h
DFFh
E00h
Bank 11
Bank 12
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
Bank 14
FFh
00h
Bank 15
Unused
SFR(1)
EFFh
F00h
F37h
F38h
F5Fh
F60h
SFR
FFh
Note 1:
FFFh
DS41412F-page 79
PIC18(L)F2X/4XK22
FIGURE 5-8:
BSR<3:0>
= 0000
00h
Access RAM
FFh
00h
GPR
Bank 0
= 0001
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
Bank 2
Bank 4
Bank 5
2FFh
300h
GPR
4FFh
500h
FFh
00h
GPR
5FFh
600h
GPR
Bank 7
Bank 11
Bank 12
Access Bank
6FFh
700h
GPR
00h
5Fh
Access RAM High 60h
(SFRs)
FFh
7FFh
800h
FFh
00h
GPR
8FFh
900h
FFh
00h
GPR
9FFh
A00h
FFh
00h
GPR
AFFh
B00h
FFh
00h
GPR
FFh
00h
FFh
Bank 13 00h
BFFh
C00h
GPR
CFFh
D00h
GPR
DFFh
E00h
FFh
00h
GPR
Bank 14
FFh
00h
Bank 15
GPR
SFR(1)
F00h
F37h
F38h
F5Fh
F60h
SFR
FFh
DS41412F-page 80
3FFh
400h
FFh
00h
FFh
00h
Bank 10
When a = 1:
GPR
Bank 6
Bank 9
GPR
FFh
00h
FFh
00h
Bank 8
1FFh
200h
FFh
00h
Bank 3
000h
05Fh
060h
0FFh
100h
GPR
Bank 1
= 0010
When a = 0:
FFFh
Note 1:
PIC18(L)F2X/4XK22
FIGURE 5-9:
Data Memory
BSR(1)
000h
00h
Bank 0
100h
Bank 1
Bank Select(2)
FFh
00h
From Opcode(2)
FFh
00h
200h
Bank 2
300h
FFh
00h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
F00h
Bank 15
FFFh
Note 1:
2:
FFh
00h
FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
The MOVFF instruction embeds the entire 12-bit address in the instruction.
DS41412F-page 81
PIC18(L)F2X/4XK22
5.4.2
ACCESS BANK
5.4.3
5.4.4
DS41412F-page 82
PIC18(L)F2X/4XK22
TABLE 5-1:
Address
Address
Name
Address
Name
Address
Name
Address
(2)
F5Fh
Name
FFFh
TOSU
FD7h
TMR0H
FAFh
SPBRG1
F87h
FFEh
TOSH
FD6h
TMR0L
FAEh
RCREG1
F86h
(2)
F5Eh
CCPR3L
FFDh
TOSL
FD5h
T0CON
FADh
TXREG1
F85h
(2)
F5Dh
CCP3CON
FFCh
STKPTR
FD4h
(2)
FACh
TXSTA1
F84h
PORTE
F5Ch
PWM3CON
F5Bh
ECCP3AS
F5Ah
PSTR3CON
CCPR3H
FFBh
PCLATU
FD3h
OSCCON
FABh
RCSTA1
F83h
PORTD(3)
FFAh
PCLATH
FD2h
OSCCON2
FAAh
EEADRH(4)
F82h
PORTC
FF9h
PCL
FD1h
WDTCON
FA9h
EEADR
F81h
PORTB
F59h
CCPR4H
FF8h
TBLPTRU
FD0h
RCON
FA8h
EEDATA
F80h
PORTA
F58h
CCPR4L
(1)
FF7h
TBLPTRH
FCFh
TMR1H
FA7h
F7Fh
IPR5
F57h
CCP4CON
FF6h
TBLPTRL
FCEh
TMR1L
FA6h
EECON1
F7Eh
PIR5
F56h
CCPR5H
FF5h
TABLAT
FCDh
T1CON
FA5h
IPR3
F7Dh
PIE5
F55h
CCPR5L
FF4h
PRODH
FCCh
T1GCON
FA4h
PIR3
F7Ch
IPR4
F54h
CCP5CON
TMR4
EECON2
FF3h
PRODL
FCBh SSP1CON3
FA3h
PIE3
F7Bh
PIR4
F53h
FF2h
INTCON
FCAh
SSP1MSK
FA2h
IPR2
F7Ah
PIE4
F52h
PR4
FF1h
INTCON2
FC9h
SSP1BUF
FA1h
PIR2
F79h
CM1CON0
F51h
T4CON
FF0h
INTCON3
FC8h
SSP1ADD
FA0h
PIE2
F78h
CM2CON0
F50h
TMR5H
FEFh
INDF0(1)
FC7h
SSP1STAT
F9Fh
IPR1
F77h
CM2CON1
F4Fh
TMR5L
FEEh
POSTINC0(1)
FC6h SSP1CON1
F9Eh
PIR1
F76h
SPBRGH2
F4Eh
T5CON
FEDh POSTDEC0(1)
FC5h SSP1CON2
F9Dh
PIE1
F75h
SPBRG2
F4Dh
T5GCON
FECh
PREINC0(1)
FC4h
F9Ch
HLVDCON
F74h
RCREG2
F4Ch
TMR6
(1)
ADRESH
FEBh
PLUSW0
FC3h
ADRESL
F9Bh
OSCTUNE
F73h
TXREG2
F4Bh
PR6
FEAh
FSR0H
FC2h
ADCON0
F9Ah
(2)
F72h
TXSTA2
F4Ah
T6CON
FE9h
FSR0L
FC1h
ADCON1
F99h
(2)
F71h
RCSTA2
F49h
CCPTMRS0
FE8h
WREG
FC0h
ADCON2
F98h
(2)
F70h
BAUDCON2
F48h
CCPTMRS1
FE7h
INDF1(1)
FBFh
CCPR1H
F97h
(2)
F6Fh
SSP2BUF
F47h
SRCON0
FE6h
POSTINC1(1)
FBEh
CCPR1L
F96h
TRISE
F6Eh
SSP2ADD
F46h
SRCON1
FE5h POSTDEC1(1)
FBDh
CCP1CON
F95h
TRISD(3)
F6Dh
SSP2STAT
F45h
CTMUCONH
FBCh
TMR2
F94h
TRISC
F6Ch
SSP2CON1
F44h
CTMUCONL
FE4h
PREINC1(1)
FE3h
PLUSW1(1)
FBBh
PR2
F93h
TRISB
F6Bh
SSP2CON2
F43h
CTMUICON
FE2h
FSR1H
FBAh
T2CON
F92h
TRISA
F6Ah
SSP2MSK
F42h
VREFCON0
FE1h
FSR1L
FB9h PSTR1CON
F91h
(2)
F69h
SSP2CON3
F41h
VREFCON1
FE0h
BSR
FB8h BAUDCON1
F90h
(2)
F68h
CCPR2H
F40h
VREFCON2
(2)
PMD0
FDFh
(1)
INDF2
FB7h PWM1CON
F8Fh
F67h
CCPR2L
F3Fh
FDEh POSTINC2(1)
FB6h
ECCP1AS
F8Eh
(2)
F66h
CCP2CON
F3Eh
PMD1
FDDh POSTDEC2(1)
FB5h
(2)
F8Dh
LATE(3)
F65h
PWM2CON
F3Dh
PMD2
FB4h
T3GCON
F8Ch
LATD(3)
F64h
ECCP2AS
F3Ch
ANSELE
FDCh
PREINC2(1)
FDBh
PLUSW2
(1)
FB3h
TMR3H
F8Bh
LATC
F63h
PSTR2CON
F3Bh
ANSELD
FDAh
FSR2H
FB2h
TMR3L
F8Ah
LATB
F62h
IOCB
F3Ah
ANSELC
FD9h
FSR2L
FB1h
T3CON
F89h
LATA
F61h
WPUB
F39h
ANSELB
FD8h
STATUS
FB0h
SPBRGH1
F88h
(2)
F60h
SLRCON
F38h
ANSELA
Note 1:
2:
3:
4:
DS41412F-page 83
PIC18(L)F2X/4XK22
TABLE 5-2:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FFFh
TOSU
FFEh
TOSH
0000 0000
FFDh
TOSL
0000 0000
FFCh
STKPTR
STKFUL
STKUNF
STKPTR<4:0>
00-0 0000
FFBh
PCLATU
---0 0000
FFAh
PCLATH
FF9h
PCL
FF8h
TBLPTRU
Value on
POR, BOR
---0 0000
0000 0000
0000 0000
--00 0000
FF7h
TBLPTRH
0000 0000
FF6h
TBLPTRL
0000 0000
FF5h
TABLAT
0000 0000
FF4h
PRODH
xxxx xxxx
FF3h
PRODL
FF2h
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
FF1h
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
TMR0IP
RBIP
1111 -1-1
FF0h
INTCON3
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
11-0 0-00
xxxx xxxx
0000 000x
FEFh
INDF0
Uses contents of FSR0 to address data memory value of FSR0 not changed (not a physical register)
---- ----
FEEh
POSTINC0
Uses contents of FSR0 to address data memory value of FSR0 post-incremented (not a physical register)
---- ----
FEDh
POSTDEC0
Uses contents of FSR0 to address data memory value of FSR0 post-decremented (not a physical register)
---- ----
FECh
PREINC0
Uses contents of FSR0 to address data memory value of FSR0 pre-incremented (not a physical register)
---- ----
FEBh
PLUSW0
Uses contents of FSR0 to address data memory value of FSR0 pre-incremented (not a physical register)
value of FSR0 offset by W
---- ----
FEAh
FSR0H
FE9h
FSR0L
FE8h
WREG
FE7h
INDF1
Uses contents of FSR1 to address data memory value of FSR1 not changed (not a physical register)
FE6h
POSTINC1
Uses contents of FSR1 to address data memory value of FSR1 post-incremented (not a physical register) ---- ----
FE5h
POSTDEC1
Uses contents of FSR1 to address data memory value of FSR1 post-decremented (not a physical register) ---- ----
FE4h
PREINC1
FE3h
PLUSW1
FE2h
FSR1H
FE1h
FSR1L
FE0h
BSR
FDFh
INDF2
Uses contents of FSR2 to address data memory value of FSR2 not changed (not a physical register)
FDEh
POSTINC2
Uses contents of FSR2 to address data memory value of FSR2 post-incremented (not a physical register) ---- ----
FDDh
POSTDEC2
Uses contents of FSR2 to address data memory value of FSR2 post-decremented (not a physical register) ---- ----
FDCh
PREINC2
FDBh
PLUSW2
xxxx xxxx
Uses contents of FSR1 to address data memory value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory value of FSR1 pre-incremented (not a physical register)
value of FSR1 offset by W
---- ----
---- 0000
---- ----
Uses contents of FSR2 to address data memory value of FSR2 pre-incremented (not a physical register) ---- ---Uses contents of FSR2 to address data memory value of FSR2 pre-incremented (not a physical register)
value of FSR2 offset by W
FDAh
FSR2H
FD9h
FSR2L
FD8h
STATUS
FD7h
TMR0H
FD6h
TMR0L
FD5h
T0CON
FD3h
OSCCON
IDLEN
FD2h
OSCCON2
PLLRDY
Legend:
Note 1:
2:
3:
4:
xxxx xxxx
Working Register
---- 0000
TMR0ON
T08BIT
T0CS
T0SE
IRCF<2:0>
SOSCRUN
MFIOSEL
OV
DC
---x xxxx
0000 0000
xxxx xxxx
PSA
T0PS<2:0>
OSTS
HFIOFS
SOSCGO
PRISD
1111 1111
SCS<1:0>
MFIOFS
LFIOFS
0011 q000
00-0 01x0
DS41412F-page 84
PIC18(L)F2X/4XK22
TABLE 5-2:
Address
Name
FD1h
WDTCON
FD0h
RCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
IPEN
SBOREN
RI
TO
Bit 2
Bit 0
SWDTEN
---- ---0
PD
POR
BOR
01-1 1100
FCFh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
FCEh
TMR1L
FCDh
T1CON
FCCh
T1GCON
TMR1GE
T1GPOL
T1GTM
FCBh
SSP1CON3
ACKTIM
PCIE
SCIE
FCAh
SSP1MSK
FC9h
SSP1BUF
FC8h
SSP1ADD
FC7h
SSP1STAT
SMP
CKE
D/A
FC6h
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
FC5h
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
FC4h
ADRESH
FC3h
ADRESL
FC2h
ADCON0
FC1h
ADCON1
TRIGSEL
FC0h
ADCON2
ADFM
TMR1CS<1:0>
T1CKPS<1:0>
T1SOSCEN
T1SYNC
T1GSPM
T1GGO/
DONE
T1GVAL
BOEN
SDAHT
SBCDE
xxxx xxxx
xxxx xxxx
T1RD16
TMR1ON
T1GSS<1:0>
AHEN
DHEN
R/W
PEN
UA
BF
RSEN
SEN
0000 0000
0000 0000
0000 0000
xxxx xxxx
GO/DONE
0000 0000
xxxx xxxx
CHS<4:0>
0000 0000
xxxx xxxx
SSPM<3:0>
RCEN
0000 0000
0000 xx00
1111 1111
SSP1 Address Register in I2C Slave Mode. SSP1 Baud Rate Reload Register in I2C Master Mode
S
Value on
POR, BOR
Bit 1
PVCFG<1:0>
ADON
NVCFG<1:0>
ACQT<2:0>
ADCS<2:0>
--00 0000
0--- 0000
0-00 0000
FBFh
CCPR1H
xxxx xxxx
FBEh
CCPR1L
xxxx xxxx
FBDh
CCP1CON
FBCh
TMR2
FBBh
PR2
FBAh
T2CON
FB9h
PSTR1CON
STR1SYNC
STR1D
STR1C
STR1B
STR1A
---0 0001
FB8h
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
0100 0-00
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
0000 0000
Timer2 Register
0000 0000
FB7h
PWM1CON
P1RSEN
FB6h
ECCP1AS
CCP1ASE
FB4h
T3GCON
TMR3GE
T2OUTPS<3:0>
1111 1111
TMR2ON
T2CKPS<1:0>
P1DC<6:0>
CCP1AS<2:0>
T3GPOL
T3GTM
0000 0000
PSS1AC<1:0>
T3GSPM
T3GGO/
DONE
-000 0000
PSS1BD<1:0>
0000 0000
T3GSS<1:0>
0000 0x00
T3GVAL
FB3h
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
FB2h
TMR3L
FB1h
T3CON
FB0h
SPBRGH1
0000 0000
FAFh
SPBRG1
0000 0000
FAEh
RCREG1
0000 0000
FADh
TXREG1
FACh
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
FABh
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
FAAh
EEADRH(5)
FA9h
EEADR
FA8h
EEDATA
FA7h
EECON2
FA6h
EECON1
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
xx-0 x000
FA5h
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
0000 0000
FA4h
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
0000 0000
FA3h
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
0000 0000
Legend:
Note 1:
2:
3:
4:
TMR3CS<1:0>
T3CKPS<1:0>
T3SOSCEN
T3SYNC
xxxx xxxx
xxxx xxxx
T3RD16
TMR3ON
0000 0000
0000 0000
EEADR<9:8>
EEADR<7:0>
0000 0010
0000 000x
---- --00
0000 0000
0000 0000
---- --00
DS41412F-page 85
PIC18(L)F2X/4XK22
TABLE 5-2:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
FA2h
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
1111 1111
FA1h
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
0000 0000
FA0h
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
0000 0000
F9Fh
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
-111 1111
F9Eh
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
-000 0000
F9Dh
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
-000 0000
F9Ch
HLVDCON
VDIRMAG
BGVST
IRVST
HLVDEN
F9Bh
OSCTUNE
INTSRC
PLLEN
F96h
TRISE
WPUE3
F95h
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
F94h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
F93h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
HLVDL<3:0>
0000 0000
TUN<5:0>
00xx xxxx
TRISE2(1)
TRISE1(1)
TRISE0(1)
1--- -111
TRISD1
TRISD0
1111 1111
TRISC1
TRISC0
1111 1111
TRISB1
TRISB0
1111 1111
F92h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
F8Dh
LATE(1)
LATE2
LATE1
LATE0
---- -xxx
F8Ch
LATD(1)
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx xxxx
F8Bh
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx
F8Ah
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx xxxx
F89h
LATA
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx xxxx
PORTE(2)
RE3
---- x---
PORTE(1)
RE3
RE2
RE1
RE0
---- x000
F84h
F83h
PORTD(1)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
0000 0000
F82h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
0000 00xx
F81h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxx0 0000
F80h
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xx0x 0000
F7Fh
IPR5
TMR6IP
TMR5IP
TMR4IP
---- -111
F7Eh
PIR5
TMR6IF
TMR5IF
TMR4IF
---- -111
F7Dh
PIE5
TMR6IE
TMR5IE
TMR4IE
---- -000
F7Ch
IPR4
CCP5IP
CCP4IP
CCP3IP
---- -000
F7Bh
PIR4
CCP5IF
CCP4IF
CCP3IF
---- -000
F7Ah
PIE4
CCP5IE
CCP4IE
CCP3IE
---- -000
F79h
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH<1:0>
0000 1000
F78h
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH<1:0>
0000 1000
F77h
CM2CON1
MC1OUT
MC2OUT
C1RSEL
C2RSEL
C1HYS
C2HYS
F76h
SPBRGH2
0000 0000
F75h
SPBRG2
0000 0000
F74h
RCREG2
0000 0000
F73h
TXREG2
F72h
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
F71h
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
F70h
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
01x0 0-00
F6Fh
SSP2BUF
F6Eh
SSP2ADD
C2SYNC
xxxx xxxx
SSP2 Address Register in I2C Slave Mode. SSP2 Baud Rate Reload Register in I2C Master Mode
SSP2STAT
SMP
CKE
D/A
F6Ch
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
F6Bh
SSP2CON2
GCEN
ACKSTAT
ACKDT
ACKEN
F6Ah
SSP2MSK
F69h
SSP2CON3
R/W
0000 0000
UA
BF
PEN
RSEN
SEN
SBCDE
AHEN
DHEN
SSPM<3:0>
RCEN
PCIE
SCIE
BOEN
SDAHT
0000 0000
0000 0000
0000 0000
0000 0000
F6Dh
Legend:
Note 1:
2:
3:
4:
C1SYNC
0000 0000
1111 1111
0000 0000
DS41412F-page 86
PIC18(L)F2X/4XK22
TABLE 5-2:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
F68h
CCPR2H
F67h
CCPR2L
F66h
CCP2CON
F65h
PWM2CON
P2RSEN
F64h
ECCP2AS
CCP2ASE
F63h
PSTR2CON
F62h
F61h
P2M<1:0>
DC2B<1:0>
Bit 1
Bit 0
xxxx xxxx
xxxx xxxx
CCP2M<3:0>
0000 0000
P2DC<6:0>
CCP2AS<2:0>
Value on
POR, BOR
0000 0000
PSS2AC<1:0>
PSS2BD<1:0>
0000 0000
STR2SYNC
STR2D
STR2C
STR2B
STR2A
---0 0001
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
1111 ----
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
1111 1111
SLRCON(2)
SLRC
SLRB
SLRA
---- -111
F60h
SLRCON(1)
SLRE
SLRD
SLRC
SLRB
SLRA
F5Fh
CCPR3H
F5Eh
CCPR3L
F5Dh
CCP3CON
F5Ch
PWM3CON
P3RSEN
F5Bh
ECCP3AS
CCP3ASE
F5Ah
PSTR3CON
F59h
CCPR4H
F58h
CCPR4L
F57h
CCP4CON
xxxx xxxx
xxxx xxxx
P3M<1:0>
DC3B<1:0>
CCP3M<3:0>
0000 0000
P3DC<6:0>
CCP3AS<2:0>
0000 0000
PSS3AC<1:0>
STR3SYNC
STR3D
STR3C
PSS3BD<1:0>
STR3B
STR3A
DC4B<1:0>
0000 0000
---0 0001
xxxx xxxx
---1 1111
xxxx xxxx
CCP4M<3:0>
--00 0000
F56h
CCPR5H
xxxx xxxx
F55h
CCPR5L
xxxx xxxx
F54h
CCP5CON
F53h
TMR4
F52h
PR4
F51h
T4CON
F50h
TMR5H
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
F4Fh
TMR5L
F4Eh
T5CON
F4Dh
T5GCON
F4Ch
TMR6
Timer6 Register
F4Bh
PR6
F4Ah
T6CON
F49h
CCPTMRS0
DC5B<1:0>
CCP5M<3:0>
--00 0000
Timer4 Register
0000 0000
TMR5CS<1:0>
TMR5GE
1111 1111
T4OUTPS<3:0>
T5GPOL
T5CKPS<1:0>
T5GTM
TMR4ON
T5SOSCEN
T5SYNC
T5GGO/
DONE
T5GVAL
T5GSPM
CCPTMRS1
F47h
SRCON0
SRLEN
F46h
SRCON1
SRSPE
SRSCKE
SRSC2E
F45h
CTMUCONH
CTMUEN
CTMUSIDL
F44h
CTMUCONL
EDG2POL
EDG2SEL<1:0>
F43h
CTMUICON
F42h
VREFCON0
FVREN
FVRST
F41h
VREFCON1
DACEN
DACLPS
F40h
VREFCON2
F3Fh
PMD0
UART2MD
UART1MD
TMR6MD
TMR5MD
TMR4MD
F3Eh
PMD1
MSSP2MD
MSSP1MD
CCP5MD
F3Dh
PMD2
SRCLK<2:0>
0000 0000
0000 0000
T5RD16
T5GSS<1:0>
0000 0000
0000 0x00
TMR6ON
T6CKPS<1:0>
-000 0000
C1TSEL<1:0>
00-0 0-00
C4TSEL<1:0>
---- 0000
C5TSEL<1:0>
SRQEN
SRNQEN
SRPS
SRPR
SRSC1E
SRRPE
SRRCKE
SRRC2E
SRRC1E
0000 0000
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
0000 0000
EDG1POL
EDG1SEL<1:0>
FVRS<1:0>
0000 0000
EDG2STAT EDG1STAT
0000 0000
IRNG<1:0>
0000 0000
ITRIM<5:0>
DACOE
TMR5ON
1111 1111
C2TSEL<1:0>
F48h
-000 0000
0000 0000
T6OUTPS<3:0>
C3TSEL<1:0>
T4CKPS<1:0>
0001 ----
DACNSS
000- 00-0
TMR3MD
TMR2MD
TMR1MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
00-0 0000
CTMUMD
CMP2MD
CMP1MD
ADCMD
---- 0000
DACPSS<1:0>
DACR<4:0>
---0 0000
0000 0000
F3Ch
ANSELE(1)
ANSE2
ANSE1
ANSE0
---- -111
F3Bh
ANSELD(1)
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
1111 1111
Legend:
Note 1:
2:
3:
4:
DS41412F-page 87
PIC18(L)F2X/4XK22
TABLE 5-2:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
F3Ah
ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
1111 11--
F39h
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
F38h
ANSELA
ANSA5
ANSA3
ANSA2
ANSA1
ANSA0
--1- 1111
Legend:
Note 1:
2:
3:
4:
DS41412F-page 88
PIC18(L)F2X/4XK22
5.4.5
STATUS REGISTER
5.5
REGISTER 5-2:
U-0
U-0
R/W-x
N
R/W-x
OV
R/W-x
R/W-x
R/W-x
(1)
C(1)
DC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as 0
bit 4
N: Negative bit
This bit is used for signed arithmetic (twos complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS41412F-page 89
PIC18(L)F2X/4XK22
5.6
Note:
Inherent
Literal
Direct
Indirect
5.6.3
5.6.1
Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 5-5:
NEXT
5.6.2
INDIRECT ADDRESSING
LFSR
CLRF
DIRECT ADDRESSING
BTFSS
BRA
CONTINUE
In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.4.3 General
Purpose Register File) or a location in the Access
Bank (Section 5.4.2 Access Bank) as the data
source for the instruction.
DS41412F-page 90
PIC18(L)F2X/4XK22
5.6.3.1
5.6.3.2
At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair
of 8-bit registers, FSRnH and FSRnL. Each FSR pair
holds a 12-bit value, therefore, the four upper bits of the
FSRnH register are not used. The 12-bit FSR value can
address the entire range of the data memory in a linear
fashion. The FSR register pairs, then, serve as pointers
to data memory locations.
FIGURE 5-10:
INDIRECT ADDRESSING
000h
Bank 0
ADDWF, INDF1, 1
100h
Bank 1
200h
Bank 2
300h
FSR1H:FSR1L
7
x x x x 1 1 1 0
Bank 3
through
Bank 13
1 1 0 0 1 1 0 0
E00h
Bank 14
F00h
Bank 15
FFFh
Data Memory
DS41412F-page 91
PIC18(L)F2X/4XK22
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
5.6.3.3
5.7
5.7.1
5.7.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
DS41412F-page 92
PIC18(L)F2X/4XK22
FIGURE 5-11:
000h
060h
Bank 0
100h
00h
Bank 1
through
Bank 14
60h
Valid range
for f
Access RAM
F00h
FFh
Bank 15
F60h
SFRs
FFFh
Data Memory
000h
060h
Bank 0
100h
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
BSR
00000000
000h
060h
Bank 0
100h
Bank 1
through
Bank 14
001001da ffffffff
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
DS41412F-page 93
PIC18(L)F2X/4XK22
5.7.3
FIGURE 5-12:
Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is 1) will continue
to use direct addressing as before.
5.8
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
000h
Bank 0
100h
120h
17Fh
200h
Bank 1
Window
Bank 1
00h
Bank 1 Window
5Fh
60h
Bank 2
through
Bank 14
SFRs
FFh
Access Bank
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
DS41412F-page 94
PIC18(L)F2X/4XK22
6.0
6.1
FIGURE 6-1:
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Program Memory
(TBLPTR)
DS41412F-page 95
PIC18(L)F2X/4XK22
FIGURE 6-2:
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Holding Registers
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR<MSBs>)
Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL
actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine where the write block will eventually be written. The process for writing the holding registers to the
program memory array is discussed in Section 6.6 Writing to Flash Program Memory.
6.2
Control Registers
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
6.2.1
DS41412F-page 96
PIC18(L)F2X/4XK22
6.3
REGISTER 6-1:
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
0 = Bit is cleared
1 = Bit is set
x = Bit is unknown
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
DS41412F-page 97
PIC18(L)F2X/4XK22
6.3.1
6.3.2
6.3.3
TABLE 6-1:
Example
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
21
16
15
TBLPTRH
TABLE ERASE/WRITE
TBLPTR<21:n+1>(1)
TBLPTRL
TABLE WRITE
TBLPTR<n:0>(1)
DS41412F-page 98
PIC18(L)F2X/4XK22
6.4
FIGURE 6-4:
Program Memory
TBLPTR = xxxxx1
Instruction Register
(IR)
EXAMPLE 6-1:
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVFW
MOVF
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
DS41412F-page 99
PIC18(L)F2X/4XK22
6.5
6.5.1
3.
4.
5.
6.
7.
8.
EXAMPLE 6-2:
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
EECON1,
EECON1,
EECON1,
EECON1,
INTCON,
55h
EECON2
0AAh
EECON2
EECON1,
INTCON,
;
;
;
;
;
ERASE_BLOCK
Required
Sequence
DS41412F-page 100
EEPGD
CFGS
WREN
FREE
GIE
; write 55h
WR
GIE
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
PIC18(L)F2X/4XK22
6.6
FIGURE 6-5:
Note:
8
TBLPTR = xxxx00
TBLPTR = xxxx01
Holding Register
8
TBLPTR = xxxxYY(1)
TBLPTR = xxxx02
Holding Register
Holding Register
Holding Register
Program Memory
Note 1: YY = 3F for 64 byte write blocks.
6.6.1
8.
9.
10.
11.
12.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in Example 6-3.
Note:
DS41412F-page 101
PIC18(L)F2X/4XK22
EXAMPLE 6-3:
D'64
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
TABLAT, W
POSTINC0
COUNTER
READ_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
TBLRD*MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
MOVLW
MOVWF
MOVLW
MOVWF
BlockSize
COUNTER
D64/BlockSize
COUNTER2
MOVF
MOVWF
TBLWT+*
POSTINC0, W
TABLAT
; point to buffer
READ_BLOCK
;
;
;
;
;
MODIFY_WORD
ERASE_BLOCK
Required
Sequence
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
;
;
;
;
;
; write 55h
;
;
;
;
;
write 0AAh
start erase (CPU stall)
re-enable interrupts
dummy read decrement
point to buffer
WRITE_BUFFER_BACK
; number of bytes in holding register
; number of write blocks in 64 bytes
WRITE_BYTE_TO_HREGS
DS41412F-page 102
;
;
;
;
PIC18(L)F2X/4XK22
EXAMPLE 6-3:
COUNTER
WRITE_WORD_TO_HREGS
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DCFSZ
BRA
BSF
BCF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
COUNTER2
WRITE_BYTE_TO_HREGS
INTCON, GIE
EECON1, WREN
;
;
;
;
PROGRAM_MEMORY
Required
Sequence
6.6.2
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
TABLE 6-2:
Name
TBLPTRU
; write 55h
;
;
;
;
;
;
write 0AAh
start program (CPU stall)
repeat for remaining write blocks
re-enable interrupts
disable write to memory
6.6.4
6.6.3
PROTECTION AGAINST
SPURIOUS WRITES
6.7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
page
TBLPTRH
TBLPTRL
TABLAT
INTCON
PEIE/GIEL
EECON1
EEPGD
CFGS
FREE
WRERR
IPR2
OSCFIP
C1IP
C2IP
EEIP
PIR2
OSCFIF
C1IF
C2IF
EEIF
PIE2
OSCFIE
C1IE
C2IE
EEIE
EECON2
Legend:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
WREN
WR
RD
97
BCL1IP
HLVDIP
TMR3IP
CCP2IP
129
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
= unimplemented, read as 0. Shaded bits are not used during Flash/EEPROM access.
DS41412F-page 103
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 104
PIC18(L)F2X/4XK22
7.0
EECON1
EECON2
EEDATA
EEADR
EEADRH
7.1
7.2
DS41412F-page 105
PIC18(L)F2X/4XK22
REGISTER 7-1:
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
0 = Bit is cleared
1 = Bit is set
x = Bit is unknown
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
DS41412F-page 106
PIC18(L)F2X/4XK22
7.3
7.4
7.5
EXAMPLE 7-1:
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
EXAMPLE 7-2:
Required
Sequence
Write Verify
;
;
;
;
;
;
DATA_EE_ADDR_LOW
EEADR
DATA_EE_ADDR_HI
EEADRH
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BCF
EECON1, WREN
DS41412F-page 107
PIC18(L)F2X/4XK22
7.6
7.7
7.8
EXAMPLE 7-3:
CLRF
BCF
BCF
BCF
BSF
EEADR
EECON1,
EECON1,
INTCON,
EECON1,
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
LOOP
BCF
BSF
EECON1, WREN
INTCON, GIE
CFGS
EEPGD
GIE
WREN
Loop
DS41412F-page 108
;
;
;
;
;
;
;
;
;
;
;
;
;
Start at address 0
Set for memory
Set for Data EEPROM
Disable interrupts
Enable writes
Loop to refresh array
Read current address
Write 55h
Write 0AAh
Set WR bit to begin write
Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
PIC18(L)F2X/4XK22
TABLE 7-1:
Name
Bit 6
INTCON
GIE/GIEH
PEIE/GIEL
EEADR
EEADR7
EEADR6
(1)
EEADRH
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
EEDATA
EECON2
EEADR9 EEADR8
EECON1
EEPGD
CFGS
FREE
WRERR
WREN
WR
RD
106
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
129
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
Legend: = unimplemented, read as 0. Shaded bits are not used during EEPROM access.
Note 1: PIC18(L)F26K22 and PIC18(L)F46K22 only.
DS41412F-page 109
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 110
PIC18(L)F2X/4XK22
8.0
8 x 8 HARDWARE MULTIPLIER
8.1
Introduction
8.2
EXAMPLE 8-1:
MOVF
MULWF
ARG1, W
ARG2
EXAMPLE 8-2:
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
;
;
;
;
;
Operation
TABLE 8-1:
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Program
Memory
(Words)
13
Time
Cycles
(Max) @ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz
69
4.3 s
6.9 s
27.6 s
69 s
Hardware multiply
62.5 ns
100 ns
400 ns
1 s
33
91
5.7 s
9.1 s
36.4 s
91 s
Hardware multiply
375 ns
600 ns
2.4 s
6 s
21
242
15.1 s
24.2 s
96.8 s
242 s
Hardware multiply
28
28
1.8 s
2.8 s
11.2 s
28 s
52
254
15.9 s
25.4 s
102.6 s
254 s
Hardware multiply
35
40
2.5 s
4.0 s
16.0 s
40 s
DS41412F-page 111
PIC18(L)F2X/4XK22
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES<3:0>).
EQUATION 8-1:
RES3:RES0
=
=
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
EQUATION 8-2:
EXAMPLE 8-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
ARG1L * ARG2H->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L->
PRODH:PRODL
Add cross
products
DS41412F-page 112
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
MOVF
MULWF
;
;
;
;
;
;
;
;
;
16 x 16 SIGNED
MULTIPLY ROUTINE
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
;
;
;
;
;
;
;
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
PIC18(L)F2X/4XK22
9.0
INTERRUPTS
It is recommended that the Microchip header files supplied with MPLAB IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
Flag bit to indicate that an interrupt event
occurred
Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Priority bit to select high priority or low priority
9.1
Mid-Range Compatibility
9.2
Interrupt Priority
9.3
Interrupt Response
DS41412F-page 113
PIC18(L)F2X/4XK22
Note:
FIGURE 9-1:
INT0IF
INT0IE
PIR1<6:0>
PIE1<6:0>
IPR1<6:0>
PIR2<7:0>
PIE2<7:0>
IPR2<7:0>
PIR3<7:0>
PIE3<7:0>
IPR3<7:0>
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
(1)
Interrupt to CPU
Vector to Location
0008h
GIEH/GIE
IPEN
PIR4<2:0>
PIE4<2:0>
IPR4<2:0>
PIR5<2:0>
PIE5<2:0>
IPR5<2:0>
IPEN
GIEL/PEIE
IPEN
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
(1)
GIEH/GIE
GIEL/PEIE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Note
1:
The RBIF interrupt also requires the individual pin IOCB enables.
DS41412F-page 114
PIC18(L)F2X/4XK22
9.4
INTCON Registers
9.5
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are five Peripheral Interrupt
Request Flag registers (PIR1, PIR2, PIR3, PIR4 and
PIR5).
9.6
PIE Registers
9.7
IPR Registers
The IPR registers contain the individual priority bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are five Peripheral Interrupt
Priority registers (IPR1, IPR2, IPR3, IPR4 and IPR5).
Using the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
DS41412F-page 115
PIC18(L)F2X/4XK22
9.8
REGISTER 9-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
Note:
A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
RB port change interrupts also require the individual pin IOCB enables.
DS41412F-page 116
PIC18(L)F2X/4XK22
REGISTER 9-2:
R/W-1
R/W-1
R/W-1
R/W-1
U-0
R/W-1
U-0
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
TMR0IP
RBIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
Note:
DS41412F-page 117
PIC18(L)F2X/4XK22
REGISTER 9-3:
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
Note:
DS41412F-page 118
PIC18(L)F2X/4XK22
REGISTER 9-4:
U-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
User software should ensure the appropriate interrupt flag bits are cleared prior
to enabling an interrupt and after servicing that interrupt.
DS41412F-page 119
PIC18(L)F2X/4XK22
REGISTER 9-5:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 120
PIC18(L)F2X/4XK22
REGISTER 9-6:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 121
PIC18(L)F2X/4XK22
REGISTER 9-7:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
CCP5IF
CCP4IF
CCP3IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS41412F-page 122
PIC18(L)F2X/4XK22
REGISTER 9-8:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
TMR6IF
TMR5IF
TMR4IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
x = Bit is unknown
DS41412F-page 123
PIC18(L)F2X/4XK22
REGISTER 9-9:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 124
x = Bit is unknown
PIC18(L)F2X/4XK22
REGISTER 9-10:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
x = Bit is unknown
DS41412F-page 125
PIC18(L)F2X/4XK22
REGISTER 9-11:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 126
x = Bit is unknown
PIC18(L)F2X/4XK22
REGISTER 9-12:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
REGISTER 9-13:
x = Bit is unknown
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
TMR6IE
TMR5IE
TMR4IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
x = Bit is unknown
DS41412F-page 127
PIC18(L)F2X/4XK22
REGISTER 9-14:
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
x = Bit is unknown
1 = High priority
0 = Low priority
bit 3
bit 2
bit 1
bit 0
DS41412F-page 128
PIC18(L)F2X/4XK22
REGISTER 9-15:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
x = Bit is unknown
DS41412F-page 129
PIC18(L)F2X/4XK22
REGISTER 9-16:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 130
x = Bit is unknown
PIC18(L)F2X/4XK22
REGISTER 9-17:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
REGISTER 9-18:
x = Bit is unknown
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
TMR6IP
TMR5IP
TMR4IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
x = Bit is unknown
DS41412F-page 131
PIC18(L)F2X/4XK22
9.9
9.10
TMR0 Interrupt
9.11
PORTB Interrupt-on-Change
9.12
EXAMPLE 9-1:
MOVWF
W_TEMP
MOVFF
STATUS, STATUS_TEMP
MOVFF
BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
MOVF
W_TEMP, W
MOVFF
STATUS_TEMP, STATUS
DS41412F-page 132
; Restore BSR
; Restore WREG
; Restore STATUS
PIC18(L)F2X/4XK22
TABLE 9-1:
Name
ANSELB
INTCON
Bit 6
GIE/GIEH PEIE/GIEL
Bit 2
Bit 1
Bit 0
Register
on Page
ANSB3
ANSB2
ANSB1
ANSB0
155
RBIE
TMR0IF
INT0IF
RBIF
116
TMR0IP
RBIP
117
INT1IE
INT2IF
INT1IF
118
Bit 5
Bit 4
Bit 3
ANSB5
ANSB4
TMR0IE
INT0IE
INTCON2
RBPU
INTEDG0
INTCON3
INT2IP
INT1IP
INTEDG1 INTEDG2
INT2IE
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
158
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
129
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
IPR4
CCP5IP
CCP4IP
CCP3IP
131
IPR5
TMR6IP
TMR5IP
TMR4IP
131
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
PIE4
PIE5
PIR1
ADIF
RC1IF
PIR2
OSCFIF
C1IF
C2IF
PIR3
SSP2IF
BCL2IF
RC2IF
PIR4
CCP5IF
PIR5
TMR6IF
130
126
CCP5IE
CCP4IE
CCP3IE
127
TMR6IE
TMR5IE
TMR4IE
127
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
EEIF
BCL1IF
HLVDIF
TMR3IF
TX2IF
CCP2IF
120
TMR1GIF
121
CCP4IF
CCP3IF
122
TMR5IF
TMR4IF
123
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
153
RCON
IPEN
SBOREN
RI
TO
PD
POR
BOR
60
Legend:
= unimplemented locations, read as 0. Shaded bits are not used for Interrupts.
TABLE 9-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
360
CONFIG4L
DEBUG
XINST
LVP
STRVEN
361
Legend:
= unimplemented locations, read as 0. Shaded bits are not used for Interrupts.
DS41412F-page 133
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 134
PIC18(L)F2X/4XK22
10.0
I/O PORTS
10.1
FIGURE 10-1:
RD LAT
Data
Bus
WR LAT
or Port
Q
I/O pin(1)
CK
Data Latch
D
WR TRIS
ANSELx
CK
TRIS Latch
Input
Buffer
RD TRIS
PORTA Registers
ENEN
EXAMPLE 10-1:
RD Port
Note 1:
MOVLB
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
0xF
PORTA
;
;
;
;
LATA
;
;
;
E0h
;
ANSELA ;
0CFh
;
;
;
TRISA
;
;
INITIALIZING PORTA
Set BSR for banked SFRs
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Configure I/O
for digital inputs
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
DS41412F-page 135
PIC18(L)F2X/4XK22
TABLE 10-1:
Pin Name
Function
RA0/C12IN0-/AN0
RA0
RA1/C12IN1-/AN1
RA2/C2IN+/AN2/
DACOUT/VREF-
RA3/C1IN+/AN3/
VREF+
RA4/CCP5/
C1OUT/SRQ/
T0CKI
TRIS ANSEL
Setting Setting
Legend:
Buffer
Type
Description
DIG
TTL
C12IN0-
AN
AN0
AN
Analog input 0.
RA1
DIG
TTL
C12IN1-
AN
AN1
AN
Analog input 1.
RA2
DIG
TTL
C2IN+
AN
AN2
AN
Analog output 2.
DACOUT
AN
VREF-
AN
RA3
DIG
TTL
C1IN+
AN
AN3
AN
Analog input 3.
VREF+
AN
RA4
DIG
CCP5
C1OUT
ST
DIG
SRQ
T0CKI
RA5
DIG
TTL
C2OUT
DIG
Comparator C2 output.
SRNQ
DIG
SR latch Q output.
RA5/C2OUT/
SRNQ/SS1/
HLVDIN/AN4
Pin
Type
ST
DIG
Comparator C1 output.
DIG
ST
SS1
TTL
HLVDIN
AN
AN4
AN
A/D input 4.
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal;
CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input
with I2C.
DS41412F-page 136
PIC18(L)F2X/4XK22
TABLE 10-1:
Pin Name
Function
RA6/CLKO/OSC2
Pin
Type
Buffer
Type
Description
DIG
TTL
CLKO
DIG
OSC2
XTAL
RA7
DIG
TTL
CLKI
AN
OSC1
XTAL
RA6
RA7/CLKI/OSC1
Legend:
TRIS ANSEL
Setting Setting
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal;
CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input
with I2C.
TABLE 10-2:
Name
ANSELA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSA1
ANSA0
ANSA5
ANSA3
ANSA2
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
LATA
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
VREFCON1
DACEN
DACLPS
DACOE
VREFCON2
VDIRMAG
BGVST
IRVST
HLVDEN
RA7
RA6
RA5
RA4
SLRCON
SLRE
SRCON0
SRLEN
CM1CON0
HLVDCON
PORTA
DACPSS<1:0>
SRCLK<2:0>
C2CH<1:0>
317
LATA1
LATA0
DACNSS
158
347
348
RA1
349
RA0
153
SLRD
SLRC
SLRB
SLRA
158
SRQEN
SRNQEN
SRPS
SRPR
340
WCOL
SSPOV
SSPEN
CKP
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
SSP1CON1
317
HLVDL<3:0>
RA2
154
C1CH<1:0>
DACR<4:0>
RA3
Register
on Page
SSPM<3:0>
260
T0PS<2:0>
TRISA2
TRISA1
159
TRISA0
156
Bit 0
Register
on Page
Legend: = unimplemented locations, read as 0. Shaded bits are not used for PORTA.
TABLE 10-3:
Name
Bit 7
Bit 6
CONFIG1H
IESO
FCMEN
Bit 5
Bit 4
PRICLKEN PLLCFG
Bit 3
Bit 2
Bit 1
FOSC<3:0>
357
Legend: = unimplemented locations, read as 0. Shaded bits are not used for PORTA.
DS41412F-page 137
PIC18(L)F2X/4XK22
10.1.1
TABLE 10-4:
Port bit
0
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
RA0
CCP4(1)
SOSCO
SCL2
CCP3(8)
RB0
P2B(6)
SCK2
P3A(8)
RC0
RD0
RE0
RA1
RA2
SCL2(1)
SOSCI
SDA2
P3B
SCK2(1)
CCP2(3)
CCP4
RE1
P1C(1)
P2A(3)
RD1
RB1
RC1
SDA2(1)
CCP1
P2B
CCP5
P1B(1)
P1A
RD2(4)
RE2
RB2
CTPLS
RC2
RA3
(1)
SCL1
P2C
MCLR
CCP2(6)
SCK1
RD3
VPP
SDO2
(6)
P2A
RC3
RE3
RB3
4
SRQ
P1D(1)
SDA1
SDO2
C1OUT
RB4
RC4
P2D
(1)
CCP5
RD4
RA4
Note 1:
2:
3:
4:
5:
6:
7:
8:
PIC18(L)F2XK22 devices.
PIC18(L)F4XK22 devices.
Function default pin.
Function default pin (28-pin devices).
Function default pin (40/44-pin devices).
Function alternate pin.
Function alternate pin (28-pin devices).
Function alternate pin (40/44-pin devices)
DS41412F-page 138
PIC18(L)F2X/4XK22
TABLE 10-4:
Port bit
5
PORTD(2)
PORTA
PORTB
PORTC
SRNQ
CCP3(3)
SDO1
P1B
C2OUT
P3A(3)
RC5
RD5
RA5
P2B(1)(4)
PORTE(2)
RB5
6
OSC2
PGC
TX1/CK1
TX2/CK2
CLKO
TX2/CK2(1)
CCP3(1)(7)
P1C
RB6
P3A(1)(7)
RD6
ICDCK
RC6
RA6
7
RA7
OSC1
RA7
PGD
RX2/DT2
RB7
RX1/DT1
(1)
RX2/DT2
P3B(1)
P1D
RC7
RD7
ICDDT
Note 1:
2:
3:
4:
5:
6:
7:
8:
PIC18(L)F2XK22 devices.
PIC18(L)F4XK22 devices.
Function default pin.
Function default pin (28-pin devices).
Function default pin (40/44-pin devices).
Function alternate pin.
Function alternate pin (28-pin devices).
Function alternate pin (40/44-pin devices)
DS41412F-page 139
PIC18(L)F2X/4XK22
10.2
PORTB Registers
EXAMPLE 10-2:
MOVLB
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
10.2.1
0xF
PORTB
;
;
;
;
LATB
;
;
;
0F0h
;
ANSELB ;
;
;
;
0CFh
;
;
;
TRISB
;
;
;
INITIALIZING PORTB
Set BSR for banked SFRs
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Value for init
Enable RB<3:0> for
digital input pins
(not required if config bit
PBADEN is clear)
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
DS41412F-page 140
10.3
10.3.1
WEAK PULL-UPS
10.3.2
INTERRUPT-ON-CHANGE
b)
Any read or write of PORTB to clear the mismatch condition (except when PORTB is the
source or destination of a MOVFF instruction).
Execute at least one instruction after reading or
writing PORTB, then clear the flag bit, RBIF.
PIC18(L)F2X/4XK22
10.3.3
ALTERNATE FUNCTIONS
TABLE 10-5:
Pin
RB0/INT0/CCP4/
FLT0/SRI/SS2/
AN12
RB0
DIG
TTL
INT0
ST
External interrupt 0.
CCP4(3)
DIG
ST
Capture 4 input.
FLT0
ST
SRI
SR latch input.
ST
(3)
TTL
AN12
AN
RB1
DIG
TTL
ST
External Interrupt 1.
DIG
DIG
ST
DIG
I2C
C12IN3-
AN
AN10
AN
P1C
(3)
SCL2(3)
2:
3:
Description
SCK2(3)
Note 1:
Buffer
Type
INT1
Legend:
Pin
Type
SS2
RB1/INT1/P1C/
SCK2/SCL2/
C12IN3-/AN10
TRIS ANSEL
Setting Setting
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =
CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
Function on PORTD and PORTE for PIC18(L)F4XK22 devices.
DS41412F-page 141
PIC18(L)F2X/4XK22
TABLE 10-5:
Pin
Function
RB2/INT2/CTED1/
P1B/SDI2/SDA2/
AN8
RB2
RB4/IOC0/P1D/
T5G/AN11
RB5/IOC1/P2B/
P3A/CCP3/T3CKI/
T1G/AN13
Legend:
Note 1:
2:
3:
Pin
Type
Buffer
Type
Description
DIG
TTL
INT2
ST
External interrupt 2.
CTED1
ST
P1B(3)
DIG
SDI2(3)
ST
(3)
DIG
I2C
SDA2
RB3/CTED2/P2A/
CCP2/SDO2/
C12IN2-/AN9
TRIS ANSEL
Setting Setting
AN8
AN
Analog input 8.
RB3
DIG
TTL
CTED2
ST
P2A
DIG
CCP2(2)
DIG
ST
Capture 2 input.
SDO2(2)
DIG
C12IN2-
AN
AN9
AN
Analog input 9.
RB4
DIG
TTL
IOC0
TTL
Interrupt-on-change pin.
P1D
DIG
T5G
ST
AN11
AN
RB5
DIG
TTL
IOC1
TTL
Interrupt-on-change pin 1.
P2B(1)(3)
DIG
P3A(1)
DIG
CCP3(1)
DIG
ST
Capture 3 input.
T3CKI(2)
ST
T1G
ST
AN13
AN
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =
CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
Function on PORTD and PORTE for PIC18(L)F4XK22 devices.
DS41412F-page 142
PIC18(L)F2X/4XK22
TABLE 10-5:
Pin
Function
RB6/KBI2/PGC
TRIS ANSEL
Setting Setting
RB6
0
1
IOC2
TX2(3)
CK2(3)
1
1
PGC
RB7/KBI3/PGD
RB7
0
1
IOC3
RX2(2), (3)
DT2(2), (3)
1
1
PGD
x
x
Legend:
Note 1:
2:
3:
ANSELB
ECCP2AS
DIG
TTL
Description
TTL
Interrupt-on-change pin.
DIG
DIG
ST
ST
DIG
TTL
TTL
Interrupt-on-change pin.
ST
DIG
ST
DIG
ST
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
155
CCP2ASE
CCP2CON
ECCP3AS
Buffer
Type
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =
CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
Function on PORTD and PORTE for PIC18(L)F4XK22 devices.
TABLE 10-6:
Name
Pin
Type
CCP2AS<2:0>
P2M<1:0>
CCP3ASE
CCP3CON
PSS2AC<1:0>
DC2B<1:0>
CCP3AS<2:0>
P3M<1:0>
PSS2BD<1:0>
CCP2M<3:0>
PSS3AC<1:0>
DC3B<1:0>
209
205
PSS3BD<1:0>
CCP3M<3:0>
209
205
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
TMR0IP
RBIP
117
INTCON3
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
118
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
158
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
157
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
153
SLRCON
SLRE(1)
SLRD(1)
SLRC
SLRB
SLRA
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/DONE
T1GVAL
INTCON
PORTB
GIE/GIEH PEIE/GIEL
T3SOSCEN
T3SYNC
T5GPOL
T5GTM
T5GSPM
T5GGO/DONE
T5GVAL
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
157
T5GCON
Legend:
Note 1:
TMR3CS<1:0>
T3RD16
TMR3ON
158
173
TMR5GE
T3CON
T3CKPS<1:0>
T1GSS<1:0>
T5GSS<1:0>
172
173
= unimplemented locations, read as 0. Shaded bits are not used for PORTB.
Available on PIC18(L)F4XK22 devices.
DS41412F-page 143
PIC18(L)F2X/4XK22
TABLE 10-7:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
360
CONFIG4L
DEBUG
XINST
LVP(1)
STRVEN
361
Legend:
Note 1:
10.4
= unimplemented locations, read as 0. Shaded bits are not used for PORTB.
Can only be changed when in high voltage programming mode.
PORTC Registers
EXAMPLE 10-3:
MOVLB
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
10.4.1
0xF
PORTC
;
;
;
;
LATC
;
;
;
0CFh
;
;
;
TRISC
;
;
;
30h
;
;
ANSELC ;
;
;
INITIALIZING PORTC
Set BSR for banked SFRs
Initialize PORTC by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
Value used to
enable digital inputs
RC<3:2> dig input enable
No ANSEL bits for RC<1:0>
RC<7:6> dig input enable
DS41412F-page 144
PIC18(L)F2X/4XK22
TABLE 10-8:
Pin Name
RC0/P2B/T3CKI/T3G/
T1CKI/SOSCO
RC1/P2A/CCP2/SOSCI
Function
TRIS
Setting
ANSEL
setting
Pin
Type
Buffer
Type
RC0
DIG
ST
DIG
ST
ST
ST
XTAL
DIG
ST
DIG
DIG
ST
Capture 2 input.
1
P2B(2)
T3CKI(1)
T3G
T1CKI
SOSCO
RC1
0
1
RC3/SCK1/SCL1/AN15
SOSCI
XTAL
RC2
DIG
ST
CTPLS
DIG
CCP2(1)
P1A
DIG
DIG
ST
Capture 1 input.
T5CKI
ST
AN14
AN
RC3
DIG
ST
DIG
ST
DIG
I2C
AN15
AN
RC4
DIG
ST
SCL1
SDI1
ST
SDA1
DIG
I2C
AN
AN16
Legend:
Note 1:
2:
3:
CCP1
SCK1
RC4/SDI1/SDA1/AN16
P2A
1
RC2/CTPLS/P1A/
CCP1/T5CKI/AN14
Description
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =
CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
Function on PORTD and PORTE for PIC18(L)F4XK22 devices.
DS41412F-page 145
PIC18(L)F2X/4XK22
TABLE 10-8:
Pin Name
RC5/SDO1/AN17
RC6/P3A/CCP3/TX1/
CK1/AN18
RC7/P3B/RX1/DT1/
AN19
Function
TRIS
Setting
ANSEL
setting
Pin
Type
Buffer
Type
Description
RC5
DIG
ST
SDO1
DIG
AN17
AN
RC6
DIG
ST
P3A(2), (3)
CCP3(2), (3)
DIG
ST
Capture 3 input.
TX1
DIG
CK1
DIG
ST
AN18
AN
RC7
DIG
ST
P3B
RX1
ST
DT1
DIG
ST
AN
AN19
Legend:
Note 1:
2:
3:
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =
CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
Function on PORTD and PORTE for PIC18(L)F4XK22 devices.
DS41412F-page 146
PIC18(L)F2X/4XK22
TABLE 10-9:
Name
ANSELC
ECCP1AS
Bit 7
Bit 6
ANSC7
ANSC6
CCP1ASE
CCP1CON
P1M<1:0>
CCP2CON
Bit 4
Bit 3
Bit 2
ANSC5
ANSC4
ANSC3
ANSC2
PSS1AC<1:0>
DC1B<1:0>
CCP2AS<2:0>
P2M<1:0>
CTMUCONH
Bit 5
CCP1AS<2:0>
CCP2ASE
ECCP2AS
LATC
Bit 0
Register
on Page
155
PSS1BD<1:0>
CCP1M<3:0>
205
PSS2AC<1:0>
DC2B<1:0>
209
PSS2BD<1:0>
CCP2M<3:0>
209
205
CTMUEN
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
333
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
157
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
153
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
SLRCON
SLRE(1)
SLRD(1)
SLRC
SLRB
SLRA
158
WCOL
SSPOV
SSPEN
CKP
SSP1CON1
SSPM<3:0>
260
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
T1SOSCEN
T1SYNC
T1RD16
TMR1ON
T3CON
TMR3CS<1:0>
T3CKPS<1:0>
T3SOSCEN
T3SYNC
T3RD16
TMR3ON
T3GCON
T5CON
TRISC
TXSTA1
Legend:
Note 1:
TMR3GE
T3GPOL
T3GTM
T3GSPM T3GGO/DONE
T3GSS<1:0>
172
173
T5SOSCEN
T5SYNC
T5RD16
TMR5ON
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
TMR5CS<1:0>
T5CKPS<1:0>
T3GVAL
172
172
= unimplemented locations, read as 0. Shaded bits are not used for PORTC.
Available on PIC18(L)F4XK22 devices.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
360
= unimplemented locations, read as 0. Shaded bits are not used for PORTC.
DS41412F-page 147
PIC18(L)F2X/4XK22
10.5
Note:
PORTD Registers
PORTD is only available on 40-pin and
44-pin devices.
10.5.1
EXAMPLE 10-4:
MOVLB
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
0xF
PORTD
;
;
;
;
LATD
;
;
;
0CFh
;
;
;
TRISD
;
;
;
30h
;
;
ANSELD ;
;
DS41412F-page 148
INITIALIZING PORTD
Set BSR for banked SFRs
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD<3:0> as inputs
RD<5:4> as outputs
RD<7:6> as inputs
Value used to
enable digital inputs
RD<3:0> dig input enable
RC<7:6> dig input enable
PIC18(L)F2X/4XK22
TABLE 10-11: PORTD I/O SUMMARY
Pin Name
Function
RD0/SCK2/SCL2/AN20
RD0
DIG
ST
DIG
ST
DIG
I2C
AN20
AN
RD1
DIG
ST
DIG
ST
Capture 4 input.
SDI2
ST
SDA2
DIG
I2C
AN21
AN
RD2
DIG
ST
DIG
SCL2
CCP4
RD2/P2B/AN22
P2B(1)
RD3/P2C/SS2/AN23
RD4/P2D/SDO2/AN24
RD5/P1B/AN25
Legend:
Note 1:
Description
SCK2
RD1/CCP4/SDI2/SDA2/
AN21
AN22
AN
RD3
DIG
ST
P2C
DIG
SS2
TTL
AN23
AN
RD4
DIG
ST
P2D
DIG
SDO2
DIG
AN24
AN
RD5
DIG
ST
P1B
DIG
AN25
AN
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
DS41412F-page 149
PIC18(L)F2X/4XK22
TABLE 10-11: PORTD I/O SUMMARY (CONTINUED)
Pin Name
Function
RD6/P1C/TX2/CK2/
AN26
RD6
DIG
ST
P1C
DIG
TX2
DIG
CK2
DIG
ST
AN26
AN
RD7
DIG
ST
P1D
DIG
RX2
ST
DT2
DIG
ST
AN
RD7/P1D/RX2/DT2/
AN27
AN27
Legend:
Note 1:
Description
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Bit 7
Bit 6
ANSELD(1)
ANSD7
BAUDCON2
ABDOVF
Bit 0
Register on
Page
ANSD1
ANSD0
155
WUE
ABDEN
279
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
RCIDL
DTRXP
CKTXP
BRG16
CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
205
CCP2CON
P2M<1:0>
DC2B<1:0>
CCP2M<3:0>
205
CCP4CON
LATD(1)
PORTD
(1)
RCSTA2
DC4B<1:0>
CCP4M<3:0>
205
LATD7
LATD6
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
153
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
SLRD
SLRC
SLRB
SLRA
LATD5
LATD4
SLRCON(1)
SLRE
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
TRISD(1)
TRISD7
TRISD6 TRISD5
TRISD4
LATD3
LATD2
LATD1
LATD0
SSPM<3:0>
TRISD3
TRISD2
TRISD1
157
158
260
TRISD0
156
Legend: = unimplemented locations, read as 0. Shaded bits are not used for PORTD.
Note 1: Available on PIC18(L)F4XK22 devices.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
Bit 2
Bit 1
Bit 0
Register
on Page
360
Legend: = unimplemented locations, read as 0. Shaded bits are not used for PORTD.
DS41412F-page 150
PIC18(L)F2X/4XK22
10.6
PORTE Registers
10.6.1
CLRF
CLRF
MOVLW
MOVWF
10.6.3
10.6.4
EXAMPLE 10-5:
CLRF
10.6.2
PORTE
;
;
;
LATE
;
;
;
ANSELE ;
;
05h
;
;
;
TRISE
;
;
;
INITIALIZING PORTE
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Configure analog pins
for digital only
Value used to
initialize data
direction
Set RE<0> as input
RE<1> as output
RE<2> as input
DS41412F-page 151
PIC18(L)F2X/4XK22
TABLE 10-14: PORTE I/O SUMMARY
Pin
Function
RE0/P3A/CCP3/AN5
RE0
DIG
ST
P3A(1)
DIG
CCP3(1)
DIG
RE2/CCP5/AN7
ST
Capture 3 input.
AN5
AN
Analog input 5.
RE1
DIG
ST
P3B
DIG
AN6
AN
Analog input 6.
RE2
DIG
ST
DIG
ST
Capture 5 input.
CCP5
RE3/VPP/MCLR
Note 1:
Description
RE1/P3B/AN6
Legend:
Buffer
Type
AN7
AN
Analog input 7.
RE3
ST
VPP
AN
MCLR
ST
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C.
Alternate pin assignment for P3A/CCP3 when Configuration bit CCP3MX is clear.
Bit 7
ANSELE(1)
INTCON2
RBPU
Bit 6
Bit 5
INTEDG0 INTEDG1
Bit 2
Bit 1
Bit 0
Reset
Values
on page
ANSE2
ANSE1
ANSE0
156
TMR0IP
RBIP
117
Bit 4
Bit 3
INTEDG2
(1)
LATE
LATE2
LATE1
LATE0
157
PORTE
RE3
RE2(1)
RE1(1)
RE0(1)
154
SLRCON
SLRE(1)
SLRD(1)
SLRC
SLRB
SLRA
158
TRISE
WPUE3
(1)
TRISE2
TRISE1
(1)
TRISE0
(1)
156
Legend: = unimplemented locations, read as 0. Shaded bits are not used for PORTE.
Note 1: Available on PIC18(L)F4XK22 devices.
DS41412F-page 152
PIC18(L)F2X/4XK22
TABLE 10-16: CONFIGURATION REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
CONFIG4L
DEBUG
XINST
Bit 2
Bit 1
Bit 0
LVP
STRVEN
Reset
Values
on page
360
361
Legend: = unimplemented locations, read as 0. Shaded bits are not used for Interrupts.
Note 1: Can only be changed when in high voltage programming mode.
10.7
10.8
10.9
REGISTER 10-1:
R/W-u/x
R/W-u/x
R/W-u/x
R/W-u/x
R/W-u/x
R/W-u/x
R/W-u/x
R/W-u/x
Rx7
Rx6
Rx5
Rx4
Rx3
Rx2
Rx1
Rx0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS41412F-page 153
PIC18(L)F2X/4XK22
REGISTER 10-2:
U-0
U-0
U-0
U-0
R/W-u/x
R/W-u/x
R/W-u/x
R/W-u/x
RE3(1)
RE2(2), (3)
RE1(2), (3)
RE0(2), (3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Unimplemented: Read as 0
bit 3
bit 2-0
Note 1:
2:
3:
REGISTER 10-3:
U-0
U-0
R/W-1
U-0
R/W-1
R/W-1
R/W-1
R/W-1
ANSA5
ANSA3
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4
Unimplemented: Read as 0
bit 3-0
DS41412F-page 154
x = Bit is unknown
PIC18(L)F2X/4XK22
REGISTER 10-4:
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 10-5:
x = Bit is unknown
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
U-0
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
Unimplemented: Read as 0
REGISTER 10-6:
x = Bit is unknown
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
DS41412F-page 155
PIC18(L)F2X/4XK22
REGISTER 10-7:
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
ANSE2(1)
ANSE1(1)
ANSE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2-0
Note 1:
x = Bit is unknown
REGISTER 10-8:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISx7
TRISx6
TRISx5
TRISx4
TRISx3
TRISx2
TRISx1
TRISx0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
REGISTER 10-9:
R/W-1
WPUE3
U-0
U-0
U-0
R/W-1
TRISE2
(1)
R/W-1
(1)
TRISE1
R/W-1
TRISE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-3
Unimplemented: Read as 0
bit 2-0
Note 1:
x = Bit is unknown
DS41412F-page 156
PIC18(L)F2X/4XK22
REGISTER 10-10: LATx: PORTx OUTPUT LATCH REGISTER(1)
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATx7
LATx6
LATx5
LATx4
LATx3
LATx2
LATx1
LATx0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
2:
x = Bit is unknown
U-0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
LATE2
LATE1
LATE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2-0
Note 1:
2:
x = Bit is unknown
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
DS41412F-page 157
PIC18(L)F2X/4XK22
REGISTER 10-13: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
U-0
U-0
U-0
U-0
IOCB7
IOCB6
IOCB5
IOCB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-4
Note 1:
x = Bit is unknown
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SLRE(1)
SLRD(1)
SLRC
SLRB
SLRA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
x = Bit is unknown
DS41412F-page 158
PIC18(L)F2X/4XK22
11.0
TIMER0 MODULE
The Timer0
features:
module
incorporates
the
following
11.1
REGISTER 11-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
R/W-1
R/W-1
R/W-1
TOPS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
DS41412F-page 159
PIC18(L)F2X/4XK22
11.2
Timer0 Operation
11.3
FIGURE 11-1:
0
1
1
T0CKI pin
T0SE
T0CS
T0PS<2:0>
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
8
3
8
PSA
Note:
Set
TMR0IF
on Overflow
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS41412F-page 160
PIC18(L)F2X/4XK22
FIGURE 11-2:
FOSC/4
0
1
Sync with
Internal
Clocks
1
Programmable
Prescaler
T0CKI pin
T0SE
T0CS
TMR0
High Byte
TMR0L
Set
TMR0IF
on Overflow
(2 TCY Delay)
Read TMR0L
T0PS<2:0>
Write TMR0L
PSA
TMR0H
8
8
Internal Data Bus
Note:
11.4
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
11.4.1
Prescaler
TABLE 11-1:
Name
INTCON
INTCON2
T0CON
SWITCHING PRESCALER
ASSIGNMENT
11.5
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit of the INTCON register. Before
re-enabling the interrupt, the TMR0IF bit must be
cleared by software in the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
TMR0IP
RBIP
T0CS
T0SE
PSA
T0PS<2:0>
117
159
TMR0H
TMR0L
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
156
Legend: = unimplemented locations, read as 0. Shaded bits are not used by Timer0.
DS41412F-page 161
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 162
PIC18(L)F2X/4XK22
12.0
FIGURE 12-1:
TxGSS<1:0>
TxGSPM
00
TxG
Timer2/4/6 Match
PR2/4/6
01
TxG_IN
TxGVAL
sync_C1OUT(7)
Single Pulse
10
sync_C2OUT(7)
CK
R
Q1
Acq. Control
11
TMRxON
Data Bus
D
Q
RD
TXGCON
EN
Interrupt
TxGGO/DONE
Set
TMRxGIF
det
TxGTM
TxGPOL
TMRxGE
Set flag bit
TMRxIF on
Overflow
TMRxON
To Comparator Module
TMRx(2),(4)
TMRxH
EN
TMRxL
TxCLK
Synchronized
clock input
1
Secondary
Oscillator
Module
See Figure 2-4
TMRxCS<1:0>
TxSYNC
SOSCOUT
Reserved
11
TxCLK_EXT_SRC
(5) ,(6)
TxCKI
TxSOSCEN
Note
(1)
Synchronize(3),(7)
Prescaler
1, 2, 4, 8
det
10
2
TxCKPS<1:0>
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
FOSC/2
Internal
Clock
Sleep input
1:
2:
3:
4:
5:
6:
7:
Synchronized comparator output should not be used in conjunction with synchronized TxCKI.
DS41412F-page 163
PIC18(L)F2X/4XK22
12.1
12.2.1
Timer1/3/5 Operation
TABLE 12-1:
12.2.2
Off
Off
Always On
Count Enabled
Note:
TABLE 12-2:
Timer1/3/5
Operation
TMRxGE
12.2
TIMER1/3/5 ENABLE
SELECTIONS
TMRxON
TMRxCS1
TMRxCS0
TxSOSCEN
DS41412F-page 164
Clock Source
PIC18(L)F2X/4XK22
12.3
Timer1/3/5 Prescaler
12.4
Secondary Oscillator
12.5
Timer1/3/5 Operation in
Asynchronous Counter Mode
12.5.1
12.6
DS41412F-page 165
PIC18(L)F2X/4XK22
FIGURE 12-2:
TIMER1/3/5 16-BIT
READ/WRITE MODE
BLOCK DIAGRAM
From
Timer1
Circuitry
TMR1
High Byte
TMR1L
Set
TMR1IF
on Overflow
Read TMR1L
Write TMR1L
12.7.2
TABLE 12-4:
TxGSS
TMR1H
8
8
01
10
11
Timer1/3/5 Gate
TABLE 12-3:
00
12.7.1
12.7
TxCLK
TxGPOL
TxG
Counts
Holds Count
Holds Count
Counts
DS41412F-page 166
TABLE 12-5:
Timer1/3/5 Resource
Timer1
Timer3
Timer5
12.7.2.1
12.7.2.2
PIC18(L)F2X/4XK22
12.7.2.3
12.7.2.4
12.7.3
12.7.4
12.7.5
12.7.6
DS41412F-page 167
PIC18(L)F2X/4XK22
12.8
Timer1/3/5 Interrupt
12.9
Section 14.0
DS41412F-page 168
PIC18(L)F2X/4XK22
FIGURE 12-3:
TXCKI = 1
when TMRx
Enabled
TXCKI = 0
when TMRX
Enabled
Note 1:
2:
FIGURE 12-4:
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer1/3/5
N+1
N+2
N+3
N+4
DS41412F-page 169
PIC18(L)F2X/4XK22
FIGURE 12-5:
TMRxGE
TxGPOL
TxGTM
TxTxG_IN
TxCKI
TxGVAL
TIMER1/3/5
FIGURE 12-6:
N+4
N+8
TMRxGE
TxGPOL
TxGSPM
TxGGO/
Cleared by hardware on
falling edge of TxGVAL
Set by software
DONE
Counting enabled on
rising edge of TxG
TxG_IN
TxCKI
TxGVAL
TIMER1/3/5
TMRxGIF
DS41412F-page 170
Cleared by software
N+1
N+2
Set by hardware on
falling edge of TxGVAL
Cleared by
software
PIC18(L)F2X/4XK22
FIGURE 12-7:
TMRxGE
TxGPOL
TxGSPM
TxGTM
TxGGO/
Cleared by hardware on
falling edge of TxGVAL
Set by software
DONE
Counting enabled on
rising edge of TxG
TxG_IN
TxCKI
TxGVAL
TIMER1/3/5
TMRxGIF
N+1
Cleared by software
N+2
N+3
Set by hardware on
falling edge of TxGVAL
N+4
Cleared by
software
DS41412F-page 171
PIC18(L)F2X/4XK22
12.13 Register Definitions: Timer1/3/5 Control
REGISTER 12-1:
R/W-0/u
R/W-0/u
TMRxCS<1:0>
R/W-0/u
R/W-0/u
TxCKPS<1:0>
R/W-0/u
R/W-0/u
R/W-0/0
R/W-0/u
TxSOSCEN
TxSYNC
TxRD16
TMRxON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 172
PIC18(L)F2X/4XK22
REGISTER 12-2:
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
TMRxGE
TxGPOL
TxGTM
TxGSPM
TxGGO/DONE
TxGVAL
R/W-0/u
R/W-0/u
TxGSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
DS41412F-page 173
PIC18(L)F2X/4XK22
TABLE 12-6:
Name
ANSELB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
155
155
ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
129
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
130
IPR5
TMR6IP
TMR5IP
TMR4IP
131
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
126
PIE5
TMR6IE
TMR5IE
TMR4IE
127
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
121
123
PIR5
PMD0
UART2MD
T1CON
T1GCON
TMR1CS<1:0>
TMR1GE
T3CON
T3GCON
T1GPOL
TMR3CS<1:0>
TMR3GE
T5CON
T5GCON
UART1MD TMR6MD
T3GPOL
TMR5CS<1:0>
TMR5GE
T5GPOL
TMR6IF
TMR5IF
TMR4IF
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
55
T1SOSCEN
T1SYNC
T1RD16
TMR1ON
172
T1CKPS<1:0>
T1GTM
T1GSPM
T3CKPS<1:0>
T3GTM
T3GSPM
T5CKPS<1:0>
T5GTM
T5GSPM
T1GGO/DONE
T1GVAL
T3SOSCEN
T3SYNC
T3GGO/DONE
T3GVAL
T5SOSCEN
T5SYNC
T5GGO/DONE
T5GVAL
T1GSS<1:0>
T3RD16
TMR3ON
T3GSS<1:0>
T5RD16
TMR5ON
T5GSS<1:0>
173
172
173
172
173
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
TMR3L
TMR5H
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
TMR5L
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TABLE 12-7:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
360
DS41412F-page 174
PIC18(L)F2X/4XK22
13.0
TIMER2/4/6 MODULE
FIGURE 13-1:
FOSC/4
Prescaler
1:1, 1:4, 1:16
2
TMRx
Sets Flag
bit TMRxIF
Reset
Comparator
EQ
Postscaler
1:1 to 1:16
TxCKPS<1:0>
PRx
4
TxOUTPS<3:0>
DS41412F-page 175
PIC18(L)F2X/4XK22
13.1
Timer2/4/6 Operation
13.2
Timer2/4/6 Interrupt
13.3
Timer2/4/6 Output
13.4
13.5
DS41412F-page 176
PIC18(L)F2X/4XK22
13.6
REGISTER 13-1:
U-0
R/W-0
R/W-0
R/W-0
TxOUTPS<3:0>
R/W-0
R/W-0
TMRxON
bit 7
R/W-0
TxCKPS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
DS41412F-page 177
PIC18(L)F2X/4XK22
TABLE 13-1:
Name
CCPTMRS0
Bit 6
C3TSEL<1:0>
Bit 5
Bit 4
Bit 3
C2TSEL<1:0>
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
IPR1
ADIP
RC1IP
TX1IP
IPR5
PIE1
ADIE
RC1IE
TX1IE
CCPTMRS1
INTCON
Bit 2
C5TSEL<1:0>
Bit 1
Bit 0
Register
on Page
C1TSEL<1:0>
208
C4TSEL<1:0>
208
TMR0IF
INT0IF
RBIF
116
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
TMR6IP
TMR5IP
TMR4IP
131
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
127
PIE5
TMR6IE
TMR5IE
TMR4IE
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR5
TMR6IF
TMR5IF
TMR4IF
123
TMR1MD
55
PMD0
UART2MD UART1MD
PR2
PR4
PR6
T2CON
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
172
T4CON
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
172
T6CON
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
172
TMR2
Timer2 Register
TMR4
Timer4 Register
TMR6
Timer6 Register
Legend:
DS41412F-page 178
PIC18(L)F2X/4XK22
14.0
CAPTURE/COMPARE/PWM
MODULES
TABLE 14-1:
Device Name
PWM RESOURCES
ECCP1
ECCP2
PIC18(L)F23K22
PIC18(L)F24K22
PIC18(L)F25K22
PIC18(L)F26K22
Enhanced PWM
Full-Bridge
Enhanced PWM
Half-Bridge
Enhanced PWM
Standard PWM
Standard PWM
Half-Bridge
(Special Event Trigger)
PIC18(L)F43K22
PIC18(L)F44K22
PIC18(L)F45K22
PIC18(L)F46K22
Enhanced PWM
Full-Bridge
Enhanced PWM
Full-Bridge
Enhanced PWM
Standard PWM
Standard PWM
Half-Bridge
(Special Event Trigger)
ECCP3
CCP4
CCP5
DS41412F-page 179
PIC18(L)F2X/4XK22
14.1
Capture Mode
FIGURE 14-1:
Prescaler
1, 4, 16
CCPx
pin
Capture
Enable
CCP OUTPUT
CCP2
CCP2MX
CCP3
CCP3MX
14.1.2
CCPRxL
TMR1/3/5H TMR1/3/5L
Note:
Legend:
CCPRxH
and
Edge Detect
14.1.1
*=
CCPxM<3:0>
System Clock (FOSC)
TABLE 14-2:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Bit Value
RB3
RB3
1(*)
RC1
RC1
0(*)
RC6
RE0
RB5
RB5
Default
14.1.3
DS41412F-page 180
PIC18(L)F2X/4XK22
14.1.4
CCP PRESCALER
14.1.5
EXAMPLE 14-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
//Capture
// Prescale 4th
// rising edge
// Turn the CCP
// Module Off
// Turn CCP module
// on with new
// prescale value
...
CCPxCON = 0;
CCPxCON = NEW_CAPT_PS;
TABLE 14-3:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
205
CCP2CON
P2M<1:0>
DC2B<1:0>
CCP2M<3:0>
205
CCP3CON
DC3B<1:0>
CCP3M<3:0>
205
CCP4CON
P3M<1:0>
DC4B<1:0>
CCP4M<3:0>
205
CCP5CON
DC5B<1:0>
CCP5M<3:0>
205
CCPR1H
CCPR1L
CCPR2H
CCPR2L
CCPR3H
CCPR3L
CCPR4H
CCPR4L
CCPR5H
CCPR5L
CCPTMRS0
CCPTMRS1
C3TSEL<1:0>
C2TSEL<1:0>
208
C4TSEL<1:0>
208
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
129
IPR4
CCP5IP
CCP4IP
CCP3IP
131
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
INTCON
C5TSEL<1:0>
C1TSEL<1:0>
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Capture mode.
Note 1:
These registers/bits are available on PIC18(L)F4XK22 devices.
DS41412F-page 181
PIC18(L)F2X/4XK22
TABLE 14-3:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
PIE4
CCP5IE
CCP4IE
CCP3IE
127
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
PIR4
CCP5IF
CCP4IF
CCP3IF
122
PMD0
UART2MD
UART1MD
TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
55
PMD1
MSSP2MD
MSSP1MD
CCP5MD
Name
T1CON
TMR1CS<1:0>
T1GCON
TMR1GE
T3CON
T1GPOL
T1CKPS<1:0>
T1GTM
TMR3CS<1:0>
T3GCON
TMR3GE
T5CON
T3GPOL
T3CKPS<1:0>
T3GTM
TMR5CS<1:0>
T5GCON
TMR5GE
T5GPOL
TMR1H
T1GSPM
T3GSPM
T5CKPS<1:0>
T5GTM
T5GSPM
CCP4MD
CCP3MD
CCP2MD
CCP1MD
56
T1SOSCEN
T1SYNC
T1RD16
TMR1ON
172
T1GGO/DONE
T1GVAL
T3SOSCEN
T3SYNC
T3GGO/DONE
T3GVAL
T5SOSCEN
T5SYNC
T5GGO/DONE
T5GVAL
T1GSS<1:0>
T3RD16
TMR3ON
T3GSS<1:0>
T5RD16
TMR5ON
T5GSS<1:0>
173
172
173
172
173
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
TMR3L
TMR5H
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
TMR5L
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
156
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
156
TRISE
WPUE3
TRISE2(1)
TRISE1(1)
TRISE0(1)
156
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Capture mode.
Note 1:
These registers/bits are available on PIC18(L)F4XK22 devices.
TABLE 14-4:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
360
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Capture mode.
DS41412F-page 182
PIC18(L)F2X/4XK22
14.2
14.2.1
Compare Mode
FIGURE 14-2:
14.2.2
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMRxH
CCPxM<3:0>
Mode Select
CCPx
Pin
COMPARE MODE
OPERATION BLOCK
DIAGRAM
14.2.3
TMRxL
DS41412F-page 183
PIC18(L)F2X/4XK22
14.2.4
14.2.5
TABLE 14-5:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
205
CCP2CON
P2M<1:0>
DC2B<1:0>
CCP2M<3:0>
205
CCP3CON
P3M<1:0>
DC3B<1:0>
CCP3M<3:0>
205
CCP4CON
DC4B<1:0>
CCP4M<3:0>
205
CCP5CON
DC5B<1:0>
CCP5M<3:0>
205
CCPR1H
CCPR1L
CCPR2H
CCPR2L
CCPR3H
CCPR3L
CCPR4H
CCPR4L
CCPR5H
CCPR5L
CCPTMRS0
C3TSEL<1:0>
CCPTMRS1
INTCON
C2TSEL<1:0>
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
C5TSEL<1:0>
RBIE
TMR0IF
C1TSEL<1:0>
208
C4TSEL<1:0>
208
INT0IF
RBIF
116
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Compare mode.
Note 1:
These registers/bits are available on PIC18(L)F4XK22 devices.
DS41412F-page 184
PIC18(L)F2X/4XK22
TABLE 14-5:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
129
IPR4
CCP5IP
CCP4IP
CCP3IP
131
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
PIE4
CCP5IE
CCP4IE
CCP3IE
127
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
PIR4
CCP5IF
CCP4IF
CCP3IF
122
PMD0
UART2MD
UART1MD
TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
55
PMD1
MSSP2MD
MSSP1MD
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
56
T1SOSCEN
T1SYNC
T1RD16
TMR1ON
T1GGO/DONE
T1GVAL
T3SOSCEN
T3SYNC
T1CON
TMR1CS<1:0>
T1GCON
TMR1GE
T3CON
T1GPOL
T1CKPS<1:0>
T1GTM
TMR3CS<1:0>
T3GCON
TMR3GE
T5CON
T3GPOL
T3CKPS<1:0>
T3GTM
TMR5CS<1:0>
T5GCON
TMR5GE
T5GPOL
T1GSPM
T3GSPM
T5CKPS<1:0>
T5GTM
T5GSPM
T3GGO/DONE
T3GVAL
T5SOSCEN
T5SYNC
T5GGO/DONE
T5GVAL
T1GSS<1:0>
T3RD16
TMR3ON
T3GSS<1:0>
T5RD16
TMR5ON
T5GSS<1:0>
172
173
172
173
172
173
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
TMR3L
TMR5H
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
TMR5L
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
156
156
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
156
TRISE
WPUE3
TRISE2(1)
TRISE1(1)
TRISE0(1)
156
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Compare mode.
Note 1:
These registers/bits are available on PIC18(L)F4XK22 devices.
TABLE 14-6:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
360
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Compare mode.
DS41412F-page 185
PIC18(L)F2X/4XK22
14.3
PWM Overview
FIGURE 14-3:
Period
Pulse Width
TMRx = 0
FIGURE 14-4:
CCPRxH(2) (Slave)
CCPx
TMRx
Comparator
PRx
Note 1:
2:
14.3.2
Clear Timer,
toggle CCPx pin and
latch duty cycle
3.
4.
5.
DS41412F-page 186
(1)
TRIS
Comparator
PRx registers
TxCON registers
CCPRxL registers
CCPxCON registers
CCPxCON<5:4>
CCPRxL
TMRx = PRx
TMRx = CCPRxH:CCPxCON<5:4>
14.3.1
PIC18(L)F2X/4XK22
6.
7.
14.3.5
EQUATION 14-2:
PULSE WIDTH
14.3.3
14.3.4
PWM PERIOD
EQUATION 14-1:
PWM PERIOD
TOSC = 1/FOSC
EQUATION 14-3:
CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = ----------------------------------------------------------------------4 PRx + 1
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMRx register is concatenated with either
the 2-bit internal system clock (FOSC), or two bits of the
prescaler, to create the 10-bit time base. The system
clock is used if the TimerX prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 14-4).
DS41412F-page 187
PIC18(L)F2X/4XK22
14.3.6
PWM RESOLUTION
EQUATION 14-4:
TABLE 14-7:
1.95 kHz
7.81 kHz
31.25 kHz
125 kHz
250 kHz
333.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
0x65
0x65
0x19
0x0C
0x09
14.3.8
PWM Frequency
14.3.7
Note:
PWM Frequency
TABLE 14-9:
log 4 PRx + 1
Resolution = ------------------------------------------ bits
log 2
PWM Frequency
TABLE 14-8:
PWM RESOLUTION
14.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
DS41412F-page 188
PIC18(L)F2X/4XK22
TABLE 14-10: REGISTERS ASSOCIATED WITH STANDARD PWM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
205
CCP2CON
P2M<1:0>
DC2B<1:0>
CCP2M<3:0>
205
CCP3CON
P3M<1:0>
DC3B<1:0>
CCP3M<3:0>
205
205
CCP4CON
DC4B<1:0>
CCP4M<3:0>
CCP5CON
DC5B<1:0>
CCP5M<3:0>
CCPTMRS0
CCPTMRS1
C3TSEL<1:0>
C2TSEL<1:0>
208
C4TSEL<1:0>
208
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
129
INTCON
C5TSEL<1:0>
205
C1TSEL<1:0>
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
IPR4
CCP5IP
CCP4IP
CCP3IP
131
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
PIE4
CCP5IE
CCP4IE
CCP3IE
127
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
122
PIR4
CCP5IF
CCP4IF
CCP3IF
PMD0
UART2MD
UART1MD
TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
55
PMD1
MSSP2MD
MSSP1MD
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
56
PR2
PR4
PR6
T2CON
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
172
T4CON
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
172
T6CON
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
172
TMR2
Timer2 Register
TMR4
Timer4 Register
TMR6
Timer6 Register
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD0
156
TRISE
WPUE3
TRISE0(1)
156
TRISD2
TRISD1
TRISE2(1)
TRISE1(1)
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Standard PWM mode.
Note 1:
These registers/bits are available on PIC18(L)F4XK22 devices.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
360
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Standard PWM mode.
DS41412F-page 189
PIC18(L)F2X/4XK22
14.4
The PWM outputs are multiplexed with I/O pins and are
designated PxA, PxB, PxC and PxD. The polarity of the
PWM pins is configurable and is selected by setting the
CCPxM bits in the CCPxCON register appropriately.
PRx registers
TxCON registers
CCPRxL registers
CCPxCON registers
ECCPxAS registers
PSTRxCON registers
PWMxCON registers
Single PWM
Half-Bridge PWM
Full-Bridge PWM, Forward mode
Full-Bridge PWM, Reverse mode
Single PWM with PWM Steering mode
FIGURE 14-5:
DCxB<1:0>
CCPxM<3:0>
4
PxM<1:0>
2
CCPRxL
CCPx/PxA
CCPx/PxA
TRISx
CCPRxH (Slave)
PxB
Comparator
Output
Controller
PxB
TRISx
PxC(2)
PxC
TMRx
(1)
TRISx
S
PxD
Comparator
Clear Timer,
toggle PWM pin and
latch duty cycle
PRx
Note
PxD(2)
TRISx
PWMxCON
1:
The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time
base.
2:
DS41412F-page 190
PIC18(L)F2X/4XK22
TABLE 14-12: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode
PxM<1:0>
CCPx/PxA
Yes
PxC
(1)
Yes
PxD
(1)
Yes(1)
Single
00
Half-Bridge
10
Yes
Yes
No
No
Full-Bridge, Forward
01
Yes
Yes
Yes
Yes
Full-Bridge, Reverse
11
Yes
Yes
Yes
Yes
Note 1:
Yes
PxB
(1)
FIGURE 14-6:
PxM<1:0>
Signal
PRX+1
Pulse
Width
Period
00
(Single Output)
PxA Modulated
Delay(1)
Delay(1)
PxA Modulated
10
(Half-Bridge)
PxB Modulated
PxA Active
01
(Full-Bridge,
Forward)
PxB Inactive
PxC Inactive
PxD Modulated
PxA Inactive
11
(Full-Bridge,
Reverse)
PxB Modulated
PxC Active
PxD Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
Note 1: Dead-band delay is programmed using the PWMxCON register (Section 14.4.5 Programmable Dead-Band Delay
Mode).
DS41412F-page 191
PIC18(L)F2X/4XK22
FIGURE 14-7:
PxM<1:0>
PRx+1
Pulse
Width
Period
00
(Single Output)
PxA Modulated
PxA Modulated
Delay(1)
10
(Half-Bridge)
Delay(1)
PxB Modulated
PxA Active
01
(Full-Bridge,
Forward)
PxB Inactive
PxC Inactive
PxD Modulated
PxA Inactive
11
(Full-Bridge,
Reverse)
PxB Modulated
PxC Active
PxD Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
Note
1:
DS41412F-page 192
Dead-band delay is programmed using the PWMxCON register (Section 14.4.5 Programmable Dead-Band Delay
Mode).
PIC18(L)F2X/4XK22
14.4.1
HALF-BRIDGE MODE
Since the PxA and PxB outputs are multiplexed with the
PORT data latches, the associated TRIS bits must be
cleared to configure PxA and PxB as outputs.
FIGURE 14-8:
Period
Period
Pulse Width
PxA(2)
td
td
PxB(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
FIGURE 14-9:
PxA
Load
FET
Driver
PxB
FET
Driver
FET
Driver
PxA
FET
Driver
Load
FET
Driver
PxB
DS41412F-page 193
PIC18(L)F2X/4XK22
14.4.2
FULL-BRIDGE MODE
FIGURE 14-10:
FET
Driver
QC
QA
FET
Driver
PxA
Load
PxB
FET
Driver
PxC
FET
Driver
QD
QB
VPxD
DS41412F-page 194
PIC18(L)F2X/4XK22
FIGURE 14-11:
Forward Mode
Period
PxA
(2)
Pulse Width
PxB(2)
PxC(2)
PxD(2)
(1)
(1)
Reverse Mode
Period
Pulse Width
PxA(2)
PxB(2)
PxC(2)
PxD(2)
(1)
Note 1:
2:
(1)
DS41412F-page 195
PIC18(L)F2X/4XK22
14.4.2.1
FIGURE 14-12:
Signal
Period
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
(2)
PxD (Active-High)
Pulse Width
Note 1:
2:
The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is (TimerX Prescale)/FOSC,
where TimerX is Timer2, Timer4 or Timer6.
DS41412F-page 196
PIC18(L)F2X/4XK22
FIGURE 14-13:
t1
Reverse Period
PxA
PxB
PW
PxC
PxD
PW
TON
External Switch C
TOFF
External Switch D
Potential
Shoot-Through Current
Note 1:
14.4.3
T = TOFF TON
2:
3:
DS41412F-page 197
PIC18(L)F2X/4XK22
FIGURE 14-14:
Timer
Overflow
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
Shutdown
Event Occurs
14.4.4
AUTO-RESTART MODE
FIGURE 14-15:
Shutdown
Event Clears
PWM
Resumes
CCPxASE
Cleared by
Firmware
Timer
Overflow
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Resumes
Shutdown
Event Occurs
Shutdown
Event Clears
DS41412F-page 198
CCPxASE
Cleared by
Hardware
PIC18(L)F2X/4XK22
14.4.5
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 14-16:
Period
Period
Pulse Width
PxA(2)
td
td
PxB(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current
from destroying the bridge power switches. The delay
occurs at the signal transition from the non-active state
to the active state. See Figure 14-16 for illustration.
The lower seven bits of the associated PWMxCON
register (Register 14-6) sets the delay period in terms
of microcontroller instruction cycles (TCY or 4 TOSC).
FIGURE 14-17:
2:
+
V
-
PxA
Load
FET
Driver
+
V
-
PxB
V-
DS41412F-page 199
PIC18(L)F2X/4XK22
14.4.6
Note:
FIGURE 14-18:
SIMPLIFIED STEERING
BLOCK DIAGRAM
STRxA
PxA Signal
CCPxM1
PORT Data
PxA pin
STRxB
CCPxM0
PORT Data
CCPxM1
PORT Data
PxC pin
TRIS
STRxD
PORT Data
PxB pin
TRIS
STRxC
CCPxM0
TRIS
PxD pin
1
0
TRIS
Note 1:
2:
14.4.6.1
Steering Synchronization
DS41412F-page 200
PIC18(L)F2X/4XK22
14.4.7
START-UP CONSIDERATIONS
The PxA, PxB, PxC and PxD output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. The Enhanced PWM
FIGURE 14-19:
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
FIGURE 14-20:
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
DS41412F-page 201
PIC18(L)F2X/4XK22
14.4.8
2.
3.
4.
5.
6.
7.
8.
9.
DS41412F-page 202
PIC18(L)F2X/4XK22
TABLE 14-13: REGISTERS ASSOCIATED WITH ENHANCED PWM
Name
ECCP1AS
Bit 7
CCP1ASE
CCP1CON
ECCP2AS
P1M<1:0>
CCPTMRS0
Bit 4
Bit 3
DC1B<1:0>
PSS1BD<1:0>
PSS3AC<1:0>
209
209
205
PSS3BD<1:0>
CCP3M<3:0>
C2TSEL<1:0>
Register
on Page
205
PSS2BD<1:0>
CCP2M<3:0>
DC3B<1:0>
C3TSEL<1:0>
Bit 0
CCP1M<3:0>
CCP3AS<2:0>
P3M<1:0>
Bit 1
PSS2AC<1:0>
DC2B<1:0>
CCP3ASE
Bit 2
PSS1AC<1:0>
CCP2AS<2:0>
P2M<1:0>
CCP3CON
INTCON
Bit 5
CCP1AS<2:0>
CCP2ASE
CCP2CON
ECCP3AS
Bit 6
209
205
C1TSEL<1:0>
208
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
129
IPR4
CCP5IP
CCP4IP
CCP3IP
131
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
PIE4
CCP5IE
CCP4IE
CCP3IE
127
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
PIR4
CCP5IF
CCP4IF
CCP3IF
122
PMD0
UART2MD
UART1MD
TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
55
PMD1
MSSP2MD
MSSP1MD
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
56
PR2
PR4
PR6
PSTR1CON
STR1SYNC
STR1D
STR1C
STR1B
STR1A
210
PSTR2CON
STR2SYNC
STR2D
STR2C
STR2B
STR2A
210
PSTR3CON
STR3SYNC
STR3D
STR3C
STR3B
STR3A
210
PWM1CON
P1RSEN
P1DC<6:0>
210
PWM2CON
P2RSEN
P2DC<6:0>
210
PWM3CON
P3RSEN
P3DC<6:0>
T2CON
T4CON
T6CON
210
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
172
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
172
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
172
TMR2
Timer2 Register
TMR4
Timer4 Register
TMR6
TRISA
Timer6 Register
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
156
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
156
TRISE2(1)
TRISE1(1)
TRISE0(1)
156
TRISE
WPUE3
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Enhanced PWM mode.
Note 1:
These registers/bits are available on PIC18(L)F4XK22 devices.
DS41412F-page 203
PIC18(L)F2X/4XK22
TABLE 14-14: CONFIGURATION REGISTERS ASSOCIATED WITH ENHANCED PWM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
360
Legend: = Unimplemented location, read as 0. Shaded bits are not used by Enhanced PWM mode.
DS41412F-page 204
PIC18(L)F2X/4XK22
14.5
REGISTER 14-1:
U-0
U-0
R/W-0
R/W-0
R/W-0
DCxB<1:0>
R/W-0
R/W-0
R/W-0
CCPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unused
bit 5-4
bit 3-0
1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set)
1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set)
1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected,
CCPxIF is set)
1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set)
TimerX (selected by CxTSEL bits) is reset
ADON is set, starting A/D conversion if A/D module is enabled(1)
11xx =: PWM mode
Note 1:
DS41412F-page 205
PIC18(L)F2X/4XK22
REGISTER 14-2:
R/x-0
PxM<1:0>
R/W-0
R/W-0
DCxB<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
CCPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
Note 1:
DS41412F-page 206
PIC18(L)F2X/4XK22
REGISTER 14-2:
bit 3-0
1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set)
1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set)
1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected,
CCPxIF is set)
1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set)
TimerX is reset
Half-Bridge ECCP Modules(1):
1100 = PWM mode: PxA active-high; PxB active-high
1101 = PWM mode: PxA active-high; PxB active-low
1110 = PWM mode: PxA active-low; PxB active-high
1111 = PWM mode: PxA active-low; PxB active-low
Full-Bridge ECCP Modules(1):
1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high
1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low
1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high
1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low
Note 1:
See Table 14-1 to determine full-bridge and half-bridge ECCPs for the device being used.
DS41412F-page 207
PIC18(L)F2X/4XK22
REGISTER 14-3:
R/W-0
U-0
R/W-0
C3TSEL<1:0>
R/W-0
C2TSEL<1:0>
U-0
R/W-0
R/W-0
C1TSEL<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5
Unused
bit 4-3
bit 2
Unused
bit 1-0
REGISTER 14-4:
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
C5TSEL<1:0>
R/W-0
C4TSEL<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-2
bit 1-0
DS41412F-page 208
PIC18(L)F2X/4XK22
REGISTER 14-5:
R/W-0
CCPxASE
R/W-0
R/W-0
CCPxAS<2:0>
R/W-0
R/W-0
R/W-0
PSSxAC<1:0>
R/W-0
PSSxBD<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3-2
bit 1-0
Note 1:
If C1SYNC or C2SYNC bits in the CM2CON1 register are enabled, the shutdown will be delayed by
Timer1.
DS41412F-page 209
PIC18(L)F2X/4XK22
REGISTER 14-6:
R/W-0
R/W-0
R/W-0
PxRSEN
R/W-0
R/W-0
R/W-0
R/W-0
PxDC<6:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-0
REGISTER 14-7:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
STRxSYNC
STRxD
STRxC
STRxB
STRxA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and
PxM<1:0> = 00.
DS41412F-page 210
PIC18(L)F2X/4XK22
15.0
15.1
MASTER SYNCHRONOUS
SERIAL PORT (MSSP1 AND
MSSP2) MODULE
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy chain connection of slave devices
FIGURE 15-1:
Write
SSPxBUF Reg
SDIx
SSPxSR Reg
SDOx
bit 0
SSx
SSx Control
Enable
Shift
Clock
2 (CKP, CKE)
Clock Select
Edge
Select
SSPxM<3:0>
4
SCKx
Edge
Select
TRIS bit
( TMR22Output )
Prescaler TOSC
4, 16, 64
Baud Rate
Generator
(SSPxADD)
DS41412F-page 211
PIC18(L)F2X/4XK22
The I2C interface supports the following modes and
features:
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited Multi-master support
7-bit and 10-bit addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Address Hold and Data Hold modes
Selectable SDAx hold times
Internal
Data Bus
Read
[SSPxM 3:0]
Write
SSPxBUF
Baud Rate
Generator
(SSPxADD)
Shift
Clock
SDAx
SDAx in
SCLx
SCLx in
Bus Collision
DS41412F-page 212
LSb
Clock Cntl
SSPxSR
MSb
FIGURE 15-2:
PIC18(L)F2X/4XK22
FIGURE 15-3:
Write
SSPxBUF Reg
SCLx
Shift
Clock
SSPxSR Reg
SDAx
MSb
LSb
SSPxMSK Reg
Match Detect
Addr Match
SSPxADD Reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT Reg)
DS41412F-page 213
PIC18(L)F2X/4XK22
15.2
DS41412F-page 214
PIC18(L)F2X/4XK22
FIGURE 15-4:
SPI Master
SCLK
SCLK
SDOx
SDIx
SDIx
SDOx
General I/O
General I/O
SSx
General I/O
SCLK
SDIx
SDOx
SPI Slave
#1
SPI Slave
#2
SSx
SCLK
SDIx
SDOx
SPI Slave
#3
SSx
DS41412F-page 215
PIC18(L)F2X/4XK22
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
set. User software must clear the WCOL bit to allow the
following write(s) to the SSPxBUF register to complete
successfully.
FIGURE 15-5:
SDIx
Shift Register
(SSPxSR)
MSb
LSb
General I/O
DS41412F-page 216
Shift Register
(SSPxSR)
MSb
SCKx
Processor 1
SDOx
Serial Clock
Slave Select
(optional)
LSb
SCKx
SSx
Processor 2
PIC18(L)F2X/4XK22
15.2.3
FIGURE 15-6:
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
Modes
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
SDOx
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDOx
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
DS41412F-page 217
PIC18(L)F2X/4XK22
15.2.4
15.2.5
SLAVE SELECT
SYNCHRONIZATION
DS41412F-page 218
PIC18(L)F2X/4XK22
FIGURE 15-7:
SPI Master
SCLK
SCLK
SDOx
SDIx
SDIx
SDOx
General I/O
SPI Slave
#1
SSx
SCLK
SDIx
SDOx
SPI Slave
#2
SSx
SCLK
SDIx
SDOx
SPI Slave
#3
SSx
FIGURE 15-8:
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR
SDOx
bit 7
bit 6
bit 7
SDIx
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
DS41412F-page 219
PIC18(L)F2X/4XK22
FIGURE 15-9:
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDOx
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDIx
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
FIGURE 15-10:
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDOx
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDIx
bit 7
bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
DS41412F-page 220
PIC18(L)F2X/4XK22
15.2.6 SPI OPERATION IN SLEEP MODE
TABLE 15-1:
Name
ANSELA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA5
ANSA3
ANSA2
ANSA1
ANSA0
154
ANSB4
ANSB3(1)
ANSB2(1)
ANSB1(1)
ANSB0(1)
155
ANSELB
ANSB5
ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
155
ANSELD
ANSD7
ANSD6
ANSD5
ANSD4(2)
ANSD3(2)
ANSD2
ANSD1(2)
ANSD0(2)
155
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
130
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
126
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
121
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
56
PIR3
PMD1
MSSP2MD MSSP1MD
SSP1BUF
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
263
SSP1STAT
SMP
CKE
D/A
R/W
UA
BF
259
SSP2BUF
SSPM<3:0>
260
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSP2CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
263
SSP2STAT
SMP
CKE
D/A
R/W
UA
BF
259
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
156
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3(1)
TRISB2(1)
TRISB1(1)
TRISB0(1)
156
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD5
TRISD4(2)
TRISD3(2)
TRISD2
TRISD1(2)
TRISD0(2)
156
TRISD
Legend:
Note 1:
2:
TRISD7
TRISD6
SSPM<3:0>
260
DS41412F-page 221
PIC18(L)F2X/4XK22
15.3
I2C MASTER/
SLAVE CONNECTION
FIGURE 15-11:
VDD
SCLK
SCLK
DS41412F-page 222
VDD
Master
Slave
SDIx
SDOx
PIC18(L)F2X/4XK22
When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a
logical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCLx line, is called clock stretching.
Clock stretching give slave devices a mechanism to
control the flow of data. When this detection is used on
the SDAx line, it is called arbitration. Arbitration
ensures that there is only one master device
communicating at any single time.
15.3.1
CLOCK STRETCHING
15.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a
transmission on or about the same time. When this
occurs, the process of arbitration begins. Each
transmitter checks the level of the SDAx data line and
compares it to the level that it expects to find. The first
transmitter to observe that the two levels dont match,
loses arbitration, and must stop transmitting on the
SDAx line.
For example, if one transmitter holds the SDAx line to
a logical one (lets it float) and a second transmitter
holds it to a logical zero (pulls it low), the result is that
the SDAx line will be low. The first transmitter then
observes that the level of the line is different than
expected and concludes that another transmitter is
communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDAx
line. If this transmitter is also a master device, it also
must stop driving the SCLx line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDAx line continues with its
original transmission. It can do so without any complications, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins
arbitration. When two master devices send messages
to the same slave address, and addresses can
sometimes refer to multiple slaves, the arbitration
process must continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
DS41412F-page 223
PIC18(L)F2X/4XK22
15.4
DS41412F-page 224
TABLE 15-2:
TERM
Transmitter
PIC18(L)F2X/4XK22
15.4.5 START CONDITION
FIGURE 15-12:
SDAx
SCLx
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
FIGURE 15-13:
Stop
Condition
Sr
Change of
Change of
Data Allowed
Data Allowed
Restart
Condition
DS41412F-page 225
PIC18(L)F2X/4XK22
I2C Slave Mode Operation
15.5
DS41412F-page 226
PIC18(L)F2X/4XK22
15.5.2 SLAVE RECEPTION
DS41412F-page 227
DS41412F-page 228
SSPxOV
BF
SSPxIF
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D4
D3
D2
D1
SSPxBUF is read
Cleared by software
D5
Receiving Data
D6
First byte
of data is
available
in SSPxBUF
D0 ACK D7
D4
D3
D2
D1
D0
Cleared by software
D5
Receiving Data
ACK = 1
FIGURE 15-14:
SCLx
SDAx
Receiving Address
PIC18(L)F2X/4XK22
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
CKP
SSPxOV
BF
SSPxIF
SCLx
A7
A6
A5
A4
A3
A2
A1
R/W=0 ACK
SEN
2
D6
D5
D4
D3
D2
D1
D0
SSPxBUF is read
Cleared by software
D7
Receive Data
ACK
SEN
3
D5
D4
D3
First byte
of data is
available
in SSPxBUF
D2
D1
Cleared by software
D6
D7
Receive Data
D0
ACK
FIGURE 15-15:
SDAx
Receive Address
PIC18(L)F2X/4XK22
DS41412F-page 229
DS41412F-page 230
ACKTIM
CKP
ACKDT
BF
SSPxIF
Receiving Address
Slave software
clears ACKDT to
Address is
read from
SSBUF
If AHEN = 1:
SSPxIF is set
When AHEN=1:
CKP is cleared by hardware
and SCLx is stretched
A7 A6 A5 A4 A3 A2 A1
Receiving Data
9
2
ACKTIM cleared by
hardware in 9th
rising edge of SCLx
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCLx
SSPxIF is set on
9th falling edge of
SCLx, after ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
Received Data
Slave software
sets ACKDT to
not ACK
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt
after not ACK
from Slave
ACK=1
Master sends
Stop condition
FIGURE 15-16:
SCLx
SDAx
PIC18(L)F2X/4XK22
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
ACKTIM
CKP
ACKDT
BF
SSPxIF
Receiving Address
4
5
6 7
When AHEN = 1;
on the 8th falling edge
of SCLx of an address
byte, CKP is cleared
Received
address is loaded into
SSPxBUF
2 3
A7 A6 A5 A4 A3 A2 A1
ACK
Receive Data
2 3
6 7
When DHEN = 1;
on the 8th falling edge
of SCLx of a received
data byte, CKP is cleared
Received data is
available on SSPxBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Receive Data
1
3 4
6 7
Set by software,
release SCLx
Slave sends
not ACK
SSPxBUF can be
read any time before
next byte is loaded
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt after
if not ACK
from Slave
Master sends
Stop condition
FIGURE 15-17:
SCLx
SDAx
R/W = 0
Master releases
SDAx to slave for ACK sequence
PIC18(L)F2X/4XK22
DS41412F-page 231
PIC18(L)F2X/4XK22
15.5.3
SLAVE TRANSMISSION
15.5.3.2
7-bit Transmission
1.
15.5.3.1
DS41412F-page 232
D/A
R/W
ACKSTAT
CKP
BF
SSPxIF
Receiving Address
Indicates an address
has been received
R/W = 1 Automatic
ACK
Received address
is read from SSPxBUF
A7 A6 A5 A4 A3 A2 A1
Transmitting Data
Automatic
Set by software
Data to transmit is
loaded into SSPxBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting Data
CKP is not
held for not
ACK
BF is automatically
cleared after 8th falling
edge of SCLx
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
FIGURE 15-18:
SCLx
SDAx
Master sends
Stop condition
PIC18(L)F2X/4XK22
DS41412F-page 233
PIC18(L)F2X/4XK22
15.5.3.3
DS41412F-page 234
D/A
R/W
ACKTIM
CKP
ACKSTAT
ACKDT
BF
SSPxIF
Receiving Address
Slave clears
ACKDT to ACK
address
ACK
When R/W = 1;
CKP is always
cleared after ACK
R/W = 1
Received address
is read from SSPxBUF
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
A7 A6 A5 A4 A3 A2 A1
3
Cleared by software
Set by software,
releases SCLx
Data to transmit is
loaded into SSPxBUF
Transmitting Data
Automatic
D7 D6 D5 D4 D3 D2 D1 D0 ACK
ACKTIM is cleared
on 9th rising edge of SCLx
Automatic
Transmitting Data
Masters ACK
response is copied
to SSPxSTAT
BF is automatically
cleared after 8th falling
edge of SCLx
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
Master sends
Stop condition
FIGURE 15-19:
SCLx
SDAx
PIC18(L)F2X/4XK22
DS41412F-page 235
PIC18(L)F2X/4XK22
15.5.4 SLAVE MODE 10-BIT ADDRESS
RECEPTION
3.
4.
5.
6.
7.
8.
DS41412F-page 236
CKP
UA
BF
SSPxIF
0 A9 A8
Set by hardware
on 9th falling edge
When UA = 1;
SCLx is held low
ACK
If address matches
SSPxADD it is loaded into
SSPxBUF
A7 A6 A5 A4 A3 A2 A1 A0 ACK
9
1
Data is read
from SSPxBUF
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
Set by software,
When SEN = 1;
releasing SCLx
CKP is cleared after
9th falling edge of received byte
Receive address is
read from SSPxBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
FIGURE 15-20:
SCLx
SDAx
Master sends
Stop condition
PIC18(L)F2X/4XK22
DS41412F-page 237
DS41412F-page 238
ACKTIM
CKP
UA
ACKDT
BF
A9
A8
Set by hardware
on 9th falling edge
If when AHEN = 1;
on the 8th falling edge
of SCLx of an address
byte, CKP is cleared
R/W = 0
ACK
UA
A6
A5
A4
A3
A2
A1
Update to SSPxADD is
not allowed until 9th
falling edge of SCLx
SSPxBUF can be
read anytime before
the next received byte
Cleared by software
A7
A0
ACK
UA
D6
D5
D4
D2
D1
Update of SSPxADD,
clears UA and releases
SCLx
D3
Receive Data
Cleared by software
D7
Received data
is read from
SSPxBUF
D6 D5
Receive Data
D0 ACK D7
FIGURE 15-21:
SSPxIF
SCLx
SDAx
PIC18(L)F2X/4XK22
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
D/A
R/W
ACKSTAT
CKP
UA
BF
SSPxIF
Set by hardware
Indicates an address
has been received
UA indicates SSPxADD
must be updated
SSPxBUF loaded
with received address
SCLx
1
3
7 8
After SSPxADD is
updated, UA is cleared
and SCLx is released
Cleared by software
A7 A6 A5 A4 A3 A2 A1 A0 ACK
1
4
7 8
Set by hardware
2 3
When R/W = 1;
CKP is cleared on
9th falling edge of SCLx
Received address is
read from SSPxBUF
Sr
1 1 1 1 0 A9 A8
ACK
Set by software
releases SCLx
Data to transmit is
loaded into SSPxBUF
D7 D6 D5 D4 D3 D2 D1 D0
Master sends
Stop condition
ACK = 1
Master sends
not ACK
FIGURE 15-22:
SDAx
Master sends
Restart event
PIC18(L)F2X/4XK22
DS41412F-page 239
PIC18(L)F2X/4XK22
15.5.6 CLOCK STRETCHING
FIGURE 15-23:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
DX 1
DX
SCLx
CKP
Master device
asserts clock
Master device
releases clock
WR
SSPxCON1
DS41412F-page 240
PIC18(L)F2X/4XK22
15.5.8 GENERAL CALL ADDRESS SUPPORT
FIGURE 15-24:
SDAx
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
SCLx
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
1
DS41412F-page 241
PIC18(L)F2X/4XK22
15.6
DS41412F-page 242
PIC18(L)F2X/4XK22
15.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<7:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 15-25).
FIGURE 15-25:
SDAx
DX 1
DX
SCLx deasserted but slave holds
SCLx low (clock arbitration)
SCLx
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
03h
02h
DS41412F-page 243
PIC18(L)F2X/4XK22
15.6.4 I2C MASTER MODE START
CONDITION TIMING
FIGURE 15-26:
SDAx = 1,
SCLx = 1
TBRG
TBRG
SDAx
2nd bit
1st bit
TBRG
SCLx
S
DS41412F-page 244
TBRG
PIC18(L)F2X/4XK22
15.6.5 I2C MASTER MODE REPEATED
START CONDITION TIMING
FIGURE 15-27:
SDAx = 1,
SCLx = 1
TBRG
TBRG
TBRG
1st bit
SDAx
TBRG
Repeated Start
DS41412F-page 245
PIC18(L)F2X/4XK22
15.6.6 I2C MASTER MODE TRANSMISSION
15.6.6.3
15.6.6.1
BF Status Flag
7.
8.
9.
10.
11.
12.
13.
15.6.6.2
DS41412F-page 246
R/W
PEN
SEN
BF (SSPxSTAT<0>)
SSPxIF
SCLx
SDAx
A6
A5
A4
A3
A2
A1
Cleared by software
SSPxBUF written
D7
1
SCLx held low
while CPU
responds to SSPxIF
ACK = 0
R/W = 0
A7
D5
D4
D3
D2
D1
D0
D6
ACKSTAT in
SSPxCON2 = 1
Cleared by software
ACK
FIGURE 15-28:
SEN = 0
PIC18(L)F2X/4XK22
DS41412F-page 247
PIC18(L)F2X/4XK22
15.6.7
15.6.7.1
BF Status Flag
6.
7.
8.
9.
10.
11.
15.6.7.2
12.
15.6.7.3
DS41412F-page 248
13.
14.
15.
RCEN
ACKEN
SSPxOV
BF
(SSPxSTAT<0>)
SDAx = 0, SCLx = 1
while CPU
responds to SSPxIF
SSPxIF
SCLx
SDAx
A7
4
5
Cleared by software
A6 A5 A4 A3 A2
7
8
ACK
D0
ACK
RCEN cleared
automatically
5
6
Cleared by software
Cleared in
software
ACK
RCEN cleared
automatically
P
Set SSPxIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPxSTAT<4>)
and SSPxIF
PEN bit = 1
written here
D0
RCEN cleared
automatically
D7 D6 D5 D4 D3 D2 D1
Cleared by software
Cleared by software
D7 D6 D5 D4 D3 D2 D1
A1 R/W
RCEN = 1, start
next receive
FIGURE 15-29:
RCEN cleared
automatically
SEN = 0
Write to SSPxBUF occurs here,
ACK from Slave
start XMIT
Write to SSPxCON2<4>
to start Acknowledge sequence
SDAx = ACKDT (SSPxCON2<5>) = 0
PIC18(L)F2X/4XK22
DS41412F-page 249
PIC18(L)F2X/4XK22
15.6.8
ACKNOWLEDGE SEQUENCE
TIMING
15.6.9
15.6.8.1
15.6.9.1
FIGURE 15-30:
TBRG
SDAx
SCLx
D0
ACK
SSPxIF
SSPxIF set at
the end of receive
Cleared in
software
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
DS41412F-page 250
PIC18(L)F2X/4XK22
FIGURE 15-31:
Write to SSPxCON2,
set PEN
Falling edge of
9th clock
TBRG
SCLx
SDAx
ACK
P
TBRG
TBRG
TBRG
15.6.10
SLEEP OPERATION
2
15.6.11
EFFECTS OF A RESET
15.6.12
MULTI-MASTER MODE
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
DS41412F-page 251
PIC18(L)F2X/4XK22
15.6.13
FIGURE 15-32:
SDAx
SCLx
BCLxIF
DS41412F-page 252
PIC18(L)F2X/4XK22
15.6.13.1
FIGURE 15-33:
The reason that bus collision is not a factor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDAx before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address following the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDAx
SCLx
Set SEN, enable Start
condition if SDAx = 1, SCLx = 1
SEN
BCLxIF
SSPxIF
DS41412F-page 253
PIC18(L)F2X/4XK22
FIGURE 15-34:
TBRG
SDAx
SCLx
SEN
SCLx = 0 before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
by software
S
SSPxIF
FIGURE 15-35:
SDAx
SCLx
TBRG
SEN
BCLxIF
Set SSPxIF
SSPxIF
SDAx = 0, SCLx = 1,
set SSPxIF
DS41412F-page 254
Interrupts cleared
by software
PIC18(L)F2X/4XK22
15.6.13.2
FIGURE 15-36:
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
SDAx
SCLx
BCLxIF
Cleared by software
S
SSPxIF
FIGURE 15-37:
TBRG
SDAx
SCLx
BCLxIF
RSEN
S
SSPxIF
DS41412F-page 255
PIC18(L)F2X/4XK22
15.6.13.3
b)
FIGURE 15-38:
TBRG
TBRG
SDAx sampled
low after TBRG,
set BCLxIF
SDAx
SDAx asserted low
SCLx
PEN
BCLxIF
P
SSPxIF
FIGURE 15-39:
TBRG
TBRG
SDAx
Assert SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
DS41412F-page 256
PIC18(L)F2X/4XK22
TABLE 15-3:
Name
ANSELA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ANSA5
ANSA3
ANSA2
ANSA1
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
Register
on Page
Bit 0
ANSA0
(1)
ANSB0
(1)
154
155
ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
155
ANSELD
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1(2)
ANSD0(2)
155
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
129
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
130
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
126
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
121
CCP5MD CCP4MD
CCP3MD
CCP2MD
CCP1MD
56
PIR3
SSP2IF
BCL2IF
RC2IF
PMD1
MSSP2MD
MSSP1MD
SSP1ADD
SSP1BUF
2C
I2C
Master mode.
265
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
262
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
263
SMP
CKE
D/A
R/W
UA
BF
SSP1MSK
SSPM<3:0>
260
SSP1STAT
264
SSP2 Address Register in I2C Slave mode. SSP2 Baud Rate Reload Register in I2C Master mode.
SSP2ADD
SSP2BUF
SSP2CON1
259
265
WCOL
SSPOV
SSPEN
CKP
SSP2CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
262
SSP2CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
263
SSP2MSK
SSPM<3:0>
260
264
SMP
CKE
D/A
R/W
UA
BF
259
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1(1)
TRISB0(1)
156
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD2
TRISD1(2)
TRISD0(2)
156
SSP2STAT
TRISD
Legend:
Note 1:
2:
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
DS41412F-page 257
PIC18(L)F2X/4XK22
15.7
The MSSPx module has a Baud Rate Generator available for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register (Register 15-6).
When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
EQUATION 15-1:
FOSC
FCLOCK = ------------------------------------------------ SSPxADD + 1 4
FIGURE 15-40:
SSPxM<3:0>
Reload
SSPxADD<7:0>
Reload
Control
SCLx
SSPxCLK
FOSC/2
TABLE 15-4:
Note 1:
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
32 MHz
8 MHz
13h
400 kHz(1)
32 MHz
8 MHz
19h
308 kHz
32 MHz
8 MHz
4Fh
100 kHz
16 MHz
4 MHz
09h
400 kHz(1)
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
The I C interface does not conform to the 400 kHz I C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
DS41412F-page 258
PIC18(L)F2X/4XK22
15.8
REGISTER 15-1:
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
P: Stop bit
(I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is 0 on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
(I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is 0 on Reset)
0 = Start bit was not detected last
bit 2
bit 1
bit 0
DS41412F-page 259
PIC18(L)F2X/4XK22
REGISTER 15-2:
R/C/HS-0
R/C/HS-0
R/W-0
R/W-0
WCOL
SSPxOV
SSPxEN
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPxM<3:0>
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
C = User cleared
bit 7
bit 6
bit 5
bit 4
DS41412F-page 260
PIC18(L)F2X/4XK22
REGISTER 15-2:
bit 3-0
Note 1:
2:
3:
4:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDAx and SCLx pins must be configured as inputs.
SSPxADD values of 0, 1 or 2 are not supported for I2C mode.
DS41412F-page 261
PIC18(L)F2X/4XK22
REGISTER 15-3:
R/W-0
R-0
R/W-0
R/S/HC-0
R/S/HC-0
R/S/HC-0
R/S/HC-0
R/W/HC-0
GCEN
ACKSTAT
ACKDT
ACKEN(1)
RCEN(1)
PEN(1)
RSEN(1)
SEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6
bit 5
bit 4
ACKEN(1): Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
bit 2
PEN(1): Stop Condition Enable bit (in I2C Master mode only)
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN(1): Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN(1): Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
DS41412F-page 262
PIC18(L)F2X/4XK22
REGISTER 15-4:
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCLxIF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the
SSPxCON1 register will be cleared and the SCLx will be held low.
0 = Address holding is disabled
bit 1
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still
set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as
enabled.
The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.
DS41412F-page 263
PIC18(L)F2X/4XK22
REGISTER 15-4:
bit 0
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still
set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as
enabled.
The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.
REGISTER 15-5:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
bit 0
DS41412F-page 264
PIC18(L)F2X/4XK22
SSPXADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE)
REGISTER 15-6:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
Master mode:
bit 7-0
Not used: Unused for Most Significant Address byte. Bit state of this register is a dont care. Bit
pattern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
bit 0
DS41412F-page 265
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 266
PIC18(L)F2X/4XK22
16.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
FIGURE 16-1:
TXxIE
Interrupt
TXxIF
TXREGx Register
8
MSb
LSb
(8)
TXx/CKx pin
Pin Buffer
and Control
TXEN
TRMT
FOSC
+1
SPBRGHx
TX9
BRG16
SPBRGx
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
TX9D
DS41412F-page 267
PIC18(L)F2X/4XK22
FIGURE 16-2:
RXx/DTx pin
Data
Recovery
FOSC
BRG16
SPBRGHx
SPBRGx
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
Stop
RCIDL
RSR Register
MSb
Pin Buffer
and Control
+1
OERR
(8)
LSb
0 START
RX9
FERR
RX9D
RCREGx Register
FIFO
8
Data Bus
RCxIF
RCxIE
Interrupt
DS41412F-page 268
PIC18(L)F2X/4XK22
16.1
16.1.1.2
Transmitting Data
16.1.1.3
16.1.1
16.1.1.4
EUSART ASYNCHRONOUS
TRANSMITTER
16.1.1.1
Note:
DS41412F-page 269
PIC18(L)F2X/4XK22
16.1.1.5
TSR Status
16.1.1.7
16.1.1.6
1.
2.
3.
4.
5.
8.
FIGURE 16-3:
6.
7.
9.
ASYNCHRONOUS TRANSMISSION
Write to TXREGx
BRG Output
(Shift Clock)
TXx/CKx pin
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
DS41412F-page 270
Word 1
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
1 TCY
Word 1
Transmit Shift Reg
PIC18(L)F2X/4XK22
FIGURE 16-4:
Write to TXREGx
Word 2
Word 1
BRG Output
(Shift Clock)
TXx/CKx pin
Start bit
bit 0
bit 1
Word 1
1 TCY
TXxIF bit
(Interrupt Reg. Flag)
bit 7/8
Stop bit
Start bit
bit 0
Word 2
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Word 1
Transmit Shift Reg
Word 2
Transmit Shift Reg
TABLE 16-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on
Page
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
TMR2IP
TMR1IP
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
SSP2IF
BCL2IF
RC2IF
PIR3
PMD0
SPEN
RX9
RCSTA2
SPEN
RX9
TMR2IE
TMR1IE
TMR3GIE TMR1GIE
TMR2IF
128
130
124
126
TMR1IF
119
121
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
55
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
RCSTA1
TMR3GIP TMR1GIP
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TXREG1
TXSTA1
TX9
TXEN
TXREG2
TXSTA2
Legend:
SYNC
SENDB
BRGH
TRMT
TX9D
TX9
TXEN
SYNC
SENDB
277
BRGH
TRMT
TX9D
277
= unimplemented locations, read as 0. Shaded bits are not used for asynchronous transmission.
DS41412F-page 271
PIC18(L)F2X/4XK22
16.1.2
EUSART ASYNCHRONOUS
RECEIVER
16.1.2.1
DS41412F-page 272
16.1.2.2
Receiving Data
16.1.2.3
PIC18(L)F2X/4XK22
16.1.2.4
Receive Interrupts
16.1.2.5
16.1.2.7
16.1.2.8
Address Detection
16.1.2.6
DS41412F-page 273
PIC18(L)F2X/4XK22
16.1.2.9
1.
16.1.2.10
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
DS41412F-page 274
PIC18(L)F2X/4XK22
FIGURE 16-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RXx/DTx pin
bit 1
Rcv Shift
Reg
Rcv Buffer Reg
Start
bit
bit 0
Word 2
RCREGx
Word 1
RCREGx
RCIDL
Start
bit
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RXx/DTx input. The RCREGx (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
TABLE 16-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
279
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
130
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
126
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
121
PMD0
UART2MD
TMR3MD
TMR2MD
TMR1MD
55
OERR
RX9D
278
RCREG1
RCSTA1
SPEN
RX9
RCREG2
RCSTA2
CREN
ADDEN
FERR
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TRISB
(2)
TRISC
(1)
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
156
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
TRISD
Legend:
Note
= unimplemented locations, read as 0. Shaded bits are not used for asynchronous reception.
1:
PIC18(L)F4XK22 devices.
2:
PIC18(L)F2XK22 devices.
DS41412F-page 275
PIC18(L)F2X/4XK22
16.2
DS41412F-page 276
PIC18(L)F2X/4XK22
16.3
REGISTER 16-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS41412F-page 277
PIC18(L)F2X/4XK22
REGISTER 16-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 278
PIC18(L)F2X/4XK22
REGISTER 16-3:
R/W-0
R-1
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
DS41412F-page 279
PIC18(L)F2X/4XK22
16.4
EXAMPLE 16-1:
16000000
-----------------------9600
= ------------------------ 1
64
= 25.042 = 25
16000000
Calculated Baud Rate = --------------------------64 25 + 1
TABLE 16-3:
CALCULATING BAUD
RATE ERROR
= 9615
Calc. Baud Rate Desired Baud Rate
Error = -------------------------------------------------------------------------------------------Desired Baud Rate
9615 9600
= ---------------------------------- = 0.16%
9600
Configuration Bits
BRG/EUSART Mode
8-bit/Asynchronous
FOSC/[64 (n+1)]
8-bit/Asynchronous
16-bit/Asynchronous
SYNC
BRG16
BRGH
0
0
FOSC/[16 (n+1)]
0
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
1
Legend:
FOSC/[4 (n+1)]
DS41412F-page 280
PIC18(L)F2X/4XK22
TABLE 16-4:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
UART2MD
UART1MD
TMR6MD
TMR5MD
TMR4MD
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
PMD0
55
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
PIR1
ADIF
RC1IF
PIR3
SSP2IF
BCL2IF
CSRC
TX9
CSRC
TX9
TXSTA1
TXSTA2
Legend:
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
RC2IF
TX2IF
CTMUIF
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
121
TABLE 16-5:
BAUD
RATE
300
Actual
Rate
%
Error
SPBRxG
value
(decimal)
1200
0.00
239
1202
0.16
207
1200
0.00
143
Actual
Rate
%
Error
SPBRGx
value
(decimal)
Actual
Rate
%
Error
SPBRGx
value
(decimal)
Actual
Rate
%
Error
SPBRGx
value
(decimal)
1200
2400
2400
0.00
119
2404
0.16
103
2400
0.00
71
9600
9615
0.16
103
9600
0.00
29
9615
0.16
25
9600
0.00
17
10417
10417
0.00
95
10286
-1.26
27
10417
0.00
23
10165
-2.42
16
19.2k
19.23k
0.16
51
19.20k
0.00
14
19.23k
0.16
12
19.20k
0.00
57.6k
58.82k
2.12
16
57.60k
0.00
57.60k
0.00
115.2k
111.11k
-3.55
%
Error
SPBRGx
value
(decimal)
%
Error
SPBRGx
value
(decimal)
Actual
Rate
%
Error
SPBRGx
value
(decimal)
Actual
Rate
%
Error
SPBRGx
value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
9600
9615
0.16
12
9600
0.00
10417
10417
0.00
11
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
DS41412F-page 281
PIC18(L)F2X/4XK22
TABLE 16-5:
BAUD
RATE
%
Error
SPBRGx
value
(decimal)
%
Error
SPBRGx
value
(decimal)
%
Error
SPBRGx
value
(decimal)
Actual
Rate
%
Error
SPBRGx
value
(decimal)
300
1200
2400
9600
9600
0.00
119
9615
0.16
103
9600
0.00
71
10417
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
207
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
57.97k
0.64
68
57.60k
0.00
19
58.82k
2.12
16
57.60k
0.00
11
115.2k
114.29k
-0.79
34
115.2k
0.00
111.1k
-3.55
115.2k
0.00
%
Error
SPBRGx
value
(decimal)
Actual
Rate
%
Error
SPBRGx
value
(decimal)
Actual
Rate
%
Error
SxBRGx
value
(decimal)
Actual
Rate
%
Error
SPBRGx
value
(decimal)
207
300
300
0.16
1200
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
%
Error
SPBRGHx:
SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx:
SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx
:SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx:
SPBRGx
(decimal)
300
300.0
0.00
13332
300.0
0.00
3839
300.03
0.01
3332
300.0
0.00
2303
1200
1200.1
0.01
3332
1200
0.00
959
1200.5
0.04
832
1200
0.00
575
2400
2399
-0.02
1666
2400
0.00
479
2398
-0.08
416
2400
0.00
287
9600
9592
-0.08
416
9600
0.00
119
9615
0.16
103
9600
0.00
71
10417
10417
0.00
383
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
207
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
57.97k
0.64
68
57.60k
0.00
19
58.82k
2.12
16
57.60k
0.00
11
115.2k
114.29k
-0.79
34
115.2k
0.00
111.11k
-3.55
115.2k
0.00
DS41412F-page 282
PIC18(L)F2X/4XK22
TABLE 16-5:
BAUD
RATE
Actual
Rate
%
Error
SPBRGHx:
SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx:
SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx
:SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx:
SPBRGx
(decimal)
207
300
299.9
-0.02
1666
300.1
0.04
832
300.0
0.00
767
300.5
0.16
1200
1199
-0.08
416
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
%
Error
SPBRGHx:
SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx:
SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx
:SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx:
SPBRGx
(decimal)
300
300
0.00
53332
300.0
0.00
15359
300.0
0.00
13332
300.0
0.00
9215
1200
1200
0.00
13332
1200
0.00
3839
1200.1
0.01
3332
1200
0.00
2303
2400
2400
0.00
6666
2400
0.00
1919
2399.5
-0.02
1666
2400
0.00
1151
9600
9598.1
-0.02
1666
9600
0.00
479
9592
-0.08
416
9600
0.00
287
10417
10417
0.00
1535
10425
0.08
441
10417
0.00
383
10433
0.16
264
143
19.2k
19.21k
0.04
832
19.20k
0.00
239
19.23k
0.16
207
19.20k
0.00
57.6k
57.55k
-0.08
277
57.60k
0.00
79
57.97k
0.64
68
57.60k
0.00
47
115.2k
115.11k
-0.08
138
115.2k
0.00
39
114.29k
-0.79
34
115.2k
0.00
23
%
Error
SPBRGHx:
SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx:
SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx
:SPBRGx
(decimal)
Actual
Rate
%
Error
SPBRGHx:
SPBRGx
(decimal)
832
300
300.0
0.00
6666
300.0
0.01
3332
300.0
0.00
3071
300.1
0.04
1200
1200
-0.02
1666
1200
0.04
832
1200
0.00
767
1202
0.16
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
0.00
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
115.2k
117.6k
2.12
16
111.1k
-3.55
115.2k
0.00
DS41412F-page 283
PIC18(L)F2X/4XK22
16.4.1
AUTO-BAUD DETECT
TABLE 16-6:
FIGURE 16-6:
BRGH
BRG Base
Clock
BRG ABD
Clock
FOSC/64
FOSC/512
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/4
FOSC/32
Note:
BRG Value
BRG16
RXx/DTx pin
0000h
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCxIF bit
(Interrupt)
Read
RCREGx
SPBRGx
XXh
1Ch
SPBRGHx
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS41412F-page 284
PIC18(L)F2X/4XK22
16.4.2
AUTO-BAUD OVERFLOW
16.4.3
AUTO-WAKE-UP ON BREAK
16.4.3.1
Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all 0s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCxIF bit. The WUE bit is cleared by
hardware by a rising edge on RXx/DTx. The interrupt
condition is then cleared by software by reading the
RCREGx register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
DS41412F-page 285
PIC18(L)F2X/4XK22
FIGURE 16-7:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto Cleared
Note 1:
FIGURE 16-8:
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Note 1
RCxIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
DS41412F-page 286
PIC18(L)F2X/4XK22
16.4.4
16.4.4.1
FIGURE 16-9:
Write to TXREGx
16.4.5
BRG Output
(Shift Clock)
TXx/CKx (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXxIF bit
(Transmit
interrupt Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB Sampled Here
Auto Cleared
SENDB
(send Break
control bit)
DS41412F-page 287
PIC18(L)F2X/4XK22
16.5
16.5.1
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
16.5.1.2
Clock Polarity
16.5.1.3
16.5.1.4
Data Polarity
16.5.1.1
Master Clock
DS41412F-page 288
PIC18(L)F2X/4XK22
16.5.1.5
1.
2.
3.
4.
5.
6.
7.
FIGURE 16-10:
8.
9.
SYNCHRONOUS TRANSMISSION
RXx/DTx
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
TXREGx Reg
Write Word 1
Write Word 2
TXxIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
1
Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words.
FIGURE 16-11:
RXx/DTx pin
bit 0
bit 1
bit 2
bit 6
bit 7
TXx/CKx pin
Write to
TXREGx reg
TXxIF bit
TRMT bit
TXEN bit
DS41412F-page 289
PIC18(L)F2X/4XK22
TABLE 16-7:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
CCP1IP
TMR2IP
TMR1IP
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
TMR2IE
TMR1IE
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
PMD0
CCP1IF
TMR2IF
TMR1IF
128
130
124
126
119
121
UART2MD
UART1MD
TMR6MD
TMR5MD
TMR4MD
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
55
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TRISB(2)
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
156
TXREG1
TXSTA1
CSRC
TX9
TXREG2
TXSTA2
Note
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
TX9
TXEN
SYNC
SENDB
277
BRGH
TRMT
TX9D
277
= unimplemented locations, read as 0. Shaded bits are not used for synchronous master transmission.
1: PIC18(L)F4XK22 devices.
2: PIC18(L)F2XK22 devices.
DS41412F-page 290
PIC18(L)F2X/4XK22
16.5.1.6
16.5.1.7
Slave Clock
16.5.1.8
16.5.1.9
16.5.1.10
1.
DS41412F-page 291
PIC18(L)F2X/4XK22
FIGURE 16-12:
RXx/DTx
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCxIF bit
(Interrupt)
Read
RCREGx
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 16-8:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP TMR1GIP
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
121
TMR4MD
TMR3MD
TMR2MD
TMR1MD
55
PIR3
PMD0
RCREG1
RCSTA1
TMR1IE
TMR3GIE TMR1GIE
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RX9
SREN
CREN
ADDEN
126
278
124
RCREG2
RCSTA2
TMR2IE
130
FERR
OERR
RX9D
278
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
Legend:
= unimplemented locations, read as 0. Shaded bits are not used for synchronous master reception.
DS41412F-page 292
PIC18(L)F2X/4XK22
16.5.2
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
16.5.2.1
5.
16.5.2.2
1.
2.
3.
4.
5.
6.
7.
8.
DS41412F-page 293
PIC18(L)F2X/4XK22
TABLE 16-9:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
130
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
126
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
121
PMD0
UART2MD
UART1MD
RCSTA1
SPEN
RX9
RCSTA2
SPEN
RX9
TMR3MD
TMR2MD
TMR1MD
55
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
SREN
CREN
ADDEN
FERR
OERR
RX9D
278
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TRISB(2)
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
156
TXREG1
TXSTA1
CSRC
TX9
TXREG2
TXSTA2
SYNC
SENDB
BRGH
TRMT
TX9D
277
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
Legend: = unimplemented locations, read as 0. Shaded bits are not used for synchronous slave transmission.
Note
1: PIC18(L)F4XK22 devices.
2: PIC18(L)F2XK22 devices.
DS41412F-page 294
PIC18(L)F2X/4XK22
16.5.2.3
16.5.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
279
279
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
WUE
ABDEN
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
130
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
126
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
121
TMR4MD
TMR3MD
TMR2MD
TMR1MD
55
FERR
OERR
RX9D
278
FERR
OERR
RX9D
278
PMD0
RCREG1
RCSTA1
SPEN
RX9
SREN
SPEN
RX9
SREN
RCREG2
RCSTA2
ADDEN
ADDEN
SPBRG1
SPBRGH1
SPBRG2
SPBRGH2
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
277
Legend:
= unimplemented locations, read as 0. Shaded bits are not used for synchronous slave reception.
DS41412F-page 295
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 296
PIC18(L)F2X/4XK22
17.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 17-1:
FVR BUF2
11111
DAC
11110
CTMU
11101
AN28(1)
AN27(1)
CHS<4:0>
11100
11011
ADCMD
AN5(1)
AN4
AN3
AN2
AN1
AN0
ADON
00101
10-Bit ADC
GO/DONE
00100
10
00011
00010
ADFM
00001
0 = Left Justify
1 = Right Justify
00000
10
2
PVCFG<1:0>
ADRESH
AVDD
VREF+/AN3
01
FVR BUF2
10
Reserved
11
2
AVSS
VREF-/AN2
ADRESL
00
NVCFG<1:0>
00
01
Reserved
10
Reserved
11
Note: Additional ADC channels AN5-AN7 and AN20-AN27 are only available on PIC18(L)F4XK22 devices.
DS41412F-page 297
PIC18(L)F2X/4XK22
17.1
ADC Configuration
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Results formatting
17.1.1
PORT CONFIGURATION
17.1.2
CHANNEL SELECTION
17.1.3
17.1.4
DS41412F-page 298
PIC18(L)F2X/4XK22
17.1.5
CONVERSION CLOCK
17.1.6
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
Note:
TABLE 17-1:
ADCS<2:0>
000
100
ns(2)
62.5
ns(2)
ns(2)
FOSC/8
001
400
FOSC/16
101
250 ns(2)
FOSC/32
010
ns(2)
FOSC/64
110
FRC
Legend:
Note 1:
2:
3:
4:
Note:
INTERRUPTS
x11
500
1.0 s
1-4
s(1,4)
16 MHz
4 MHz
2.0 s
125
250
ns(2)
1.0 s
4.0 s(3)
500
ns(2)
2.0 s
8.0 s(3)
1.0 s
4.0 s(3)
16.0 s(3)
2.0 s
s(3)
32.0 s(3)
16.0 s(3)
64.0 s(3)
s(1,4)
1-4 s(1,4)
4.0 s(3)
1-4
s(1,4)
500
8.0
1-4
ns(2)
1 MHz
ns(2)
DS41412F-page 299
PIC18(L)F2X/4XK22
17.1.7
RESULT FORMATTING
FIGURE 17-2:
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
Unimplemented: Read as 0
MSB
(ADFM = 1)
bit 7
Unimplemented: Read as 0
DS41412F-page 300
bit 0
LSB
bit 0
bit 7
bit 0
10-bit A/D Result
PIC18(L)F2X/4XK22
17.2
ADC Operation
17.2.1
STARTING A CONVERSION
FIGURE 17-3:
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 2 TAD
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Discharge
FIGURE 17-4:
TAD Cycles
TACQT Cycles
1
Automatic
Acquisition
Time
10
11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion starts
(Holding capacitor is disconnected from analog input)
Set GO bit
(Holding capacitor continues
acquiring input)
2 TAD
Discharge
DS41412F-page 301
PIC18(L)F2X/4XK22
17.2.2
COMPLETION OF A CONVERSION
17.2.3
DISCHARGE
17.2.4
TERMINATING A CONVERSION
17.2.5
17.2.6
DS41412F-page 302
17.2.7
17.2.8
17.2.9
PIC18(L)F2X/4XK22
17.2.10
2.
3.
4.
5.
6.
7.
8.
Configure Port:
Disable pin output driver (See TRIS register)
Configure pin as analog
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Select result format
Select acquisition delay
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 17-1:
A/D CONVERSION
DS41412F-page 303
PIC18(L)F2X/4XK22
17.3
Note:
REGISTER 17-1:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
CHS<4:0>
R/W-0
R/W-0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as 0
bit 6-2
bit 1
bit 0
Note 1:
2:
DS41412F-page 304
PIC18(L)F2X/4XK22
REGISTER 17-2:
R/W-0
U-0
U-0
U-0
TRIGSEL
R/W-0
R/W-0
R/W-0
PVCFG<1:0>
R/W-0
NVCFG<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
Unimplemented: Read as 0
bit 3-2
bit 1-0
DS41412F-page 305
PIC18(L)F2X/4XK22
REGISTER 17-3:
R/W-0
U-0
ADFM
R/W-0
R/W-0
R/W-0
R/W-0
ACQT<2:0>
R/W-0
R/W-0
ADCS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
x = Bit is unknown
bit 6
Unimplemented: Read as 0
bit 5-3
ACQT<2:0>: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge
holding capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until
conversions begins.
000 = 0(1)
001 = 2 TAD
010 = 4 TAD
011 = 6 TAD
100 = 8 TAD
101 = 12 TAD
110 = 16 TAD
111 = 20 TAD
bit 2-0
Note 1:
When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction
cycle after the GO/DONE bit is set to allow the SLEEP instruction to be executed.
DS41412F-page 306
PIC18(L)F2X/4XK22
REGISTER 17-4:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 17-5:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
REGISTER 17-6:
x = Bit is unknown
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
REGISTER 17-7:
R/W-x
x = Bit is unknown
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
DS41412F-page 307
PIC18(L)F2X/4XK22
17.4
EQUATION 17-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 5s + T C + Temperature - 25C 0.05s/C
The value for TC can be approximated with the following equations:
1
V AP PLIE D 1 ------------ = V CHOLD
2047
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
V AP P LIED 1 e = V A P PLIE D 1 ------------
2047
T C = C HOLD R IC + R SS + R S ln(1/2047)
= 13.5pF 1k + 700 + 10k ln(0.0004885)
= 1.20 s
Therefore:
T ACQ = 5s + 1.20s + 50C- 25C 0.05 s/ C
= 7.45s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS41412F-page 308
PIC18(L)F2X/4XK22
FIGURE 17-5:
ANx
RIC 1k
CPIN
5 pF
I LEAKAGE(1)
Sampling
Switch
SS Rss
CHOLD = 13.5 pF
Legend: CPIN
= Input Capacitance
I LEAKAGE = Leakage current at the pin due to
various junctions
= Interconnect Resistance
RIC
SS
= Sampling Switch
CHOLD
= Sample/Hold Capacitance
VDD
Discharge
Switch
3.5V
3.0V
2.5V
2.0V
1.5V
.1
Note 1:
VSS/VREF-
1
10
Rss (k)
100
FIGURE 17-6:
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
3FBh
Full-Scale
Transition
004h
003h
002h
001h
000h
VSS/VREF-
Zero-Scale
Transition
VDD/VREF+
DS41412F-page 309
PIC18(L)F2X/4XK22
TABLE 17-2:
Name
Bit 6
Bit 5
ADCON0
ADCON1
TRIGSEL
ADCON2
ADFM
Bit 4
Bit 3
Bit 2
CHS<4:0>
Bit 0
GO/DONE
ADON
PVCFG<1:0>
NVCFG<1:0>
ACQT<2:0>
ADRESH
Bit 1
ADCS<2:0>
307
ANSELA
ANSA5
ANSA3
304
305
306
ADRESL
Register
on Page
307
ANSA2
ANSA1
ANSA0
154
155
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
155
ANSELD(1)
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
155
ANSELE(1)
ANSE2
ANSE1
ANSE0
156
EDGEN
EDGSEQEN
CTTRIG
333
CTMUCONH
CTMUEN
CTMUSIDL
TGEN
INTCON
CCP5CON
DC5B<1:0>
CCP5M<3:0>
IDISSEN
205
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
128
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
130
131
IPR4
CCP5IP
CCP4IP
CCP3IP
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
124
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
126
127
PIE4
CCP5IE
CCP4IE
CCP3IE
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
119
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
121
PIR4
CCP5IF
CCP4IF
CCP3IF
122
PMD1
MSSP2MD
MSSP1MD
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
56
PMD2
CTMUMD
CMP2MD
CMP1MD
ADCMD
57
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
156
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
156
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
156
TRISE
WPUE3
TRISE2(1)
TRISE1(1)
TRISE0(1)
156
Legend:
Note 1:
= unimplemented locations, read as 0. Shaded bits are not used by this module.
Available on PIC18(L)F4XK22 devices.
TABLE 17-3:
Name
CONFIG3H
Legend:
Bit 6
Bit 5
Bit 4
Bit 3
MCLRE
P2BMX
T3CMX
HFOFST
Bit 2
CCP3MX
Bit 1
Bit 0
Register
on Page
PBADEN
CCP2MX
360
= unimplemented locations, read as 0. Shaded bits are not used by the ADC module.
DS41412F-page 310
PIC18(L)F2X/4XK22
18.0
COMPARATOR MODULE
18.1
FIGURE 18-1:
SINGLE COMPARATOR
VIN+
VIN-
Output
VINVIN+
Output
Note:
Comparator Overview
DS41412F-page 311
PIC18(L)F2X/4XK22
FIGURE 18-2:
CxCH<1:0>
CxON(1)
2
C12IN0-
C12IN1-
C12IN2-
D
CxVIN-
C12IN3-
To CMxCON0 (CxOUT)
CM2CON1 (MCxOUT)
CxSP
CxVIN+
Q1
(2),(3)
EN
Cx
+
D
Q3(2)
To Interrupts
(CxIF)
EN
CL
CxR
Read or Write
of CMxCON0
CxIN+
Reset
async_CXOUT
DAC Output
FVR BUF1 1
CxPOL
CxSYNC
CXVREF
to PWM Logic
CxOE
TRIS bit
0
CXRSEL
D
CxOUT
Timer1 Clock
sync_CxOUT
- to SR Latch
- to TxG MUX(4)
Note 1:
2:
3:
4:
When C1ON = 0, the C1 comparator will produce a 0 output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (FOSC).
Q1 is held high during Sleep mode.
Synchronized comparator output should not be used to gate Timer1 in conjunction with synchronized T1CKI.
DS41412F-page 312
PIC18(L)F2X/4XK22
18.2
Comparator Control
Enable
Input selection
Reference selection
Output selection
Output polarity
Speed selection
18.2.1
COMPARATOR ENABLE
18.2.2
18.2.3
COMPARATOR REFERENCE
SELECTION
18.2.4
COMPARATOR OUTPUT
SELECTION
18.2.5
TABLE 18-1:
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
CxPOL
CxOUT
18.2.6
18.3
DS41412F-page 313
PIC18(L)F2X/4XK22
18.4
DS41412F-page 314
18.4.1
FIGURE 18-3:
COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
Q1
Q3
CxIN+
TRT
CxIN
Set CxIF (edge)
CxIF
Reset by Software
FIGURE 18-4:
COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
Q1
Q3
CxIN+
TRT
CxOUT
Set CxIF (edge)
CxIF
Cleared by CMxCON0 Read
Reset by Software
PIC18(L)F2X/4XK22
18.5
18.7
18.6
Effects of a Reset
FIGURE 18-5:
Rs < 10K
RIC
To Comparator
AIN
VA
CPIN
5 pF
VT 0.6V
ILEAKAGE(1)
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
= Interconnect Resistance
RIC
RS
= Source Impedance
= Analog Voltage
VA
= Threshold Voltage
VT
Note 1: See Section 27.0 Electrical Characteristics.
DS41412F-page 315
PIC18(L)F2X/4XK22
18.8
18.8.1
SIMULTANEOUS COMPARATOR
OUTPUT READ
18.8.2
INTERNAL REFERENCE
SELECTION
DS41412F-page 316
18.8.3
COMPARATOR HYSTERESIS
18.8.4
SYNCHRONIZING COMPARATOR
OUTPUT TO TIMER1
PIC18(L)F2X/4XK22
18.9
REGISTER 18-1:
R/W-0
R-0
R/W-0
R/W-0
R/W-1
R/W-0
CxON
CxOUT
CxOE
CxPOL
CxSP
CxR
R/W-0
R/W-0
CxCH<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
x = Bit is unknown
Comparator output requires the following three conditions: CxOE = 1, CxON = 1 and corresponding port
TRIS bit = 0.
DS41412F-page 317
PIC18(L)F2X/4XK22
REGISTER 18-2:
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MC1OUT
MC2OUT
C1RSEL
C2RSEL
C1HYS
C2HYS
C1SYNC
C2SYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41412F-page 318
PIC18(L)F2X/4XK22
TABLE 18-2:
Name
ANSELA
ANSELB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA5
ANSA3
ANSA2
ANSA1
ANSA0
154
ANSB5
ANSB4
CM2CON1
MC1OUT
MC2OUT
CM1CON0
C1ON
C1OUT
C1OE
CM2CON0
C2ON
C2OUT
C2OE
VREFCON1
DACEN
DACLPS
DACOE
VREFCON2
VREFCON0
INTCON
FVREN
GIE/GIEH
FVRST
ANSB3
ANSB2
ANSB1
ANSB0
155
C1HYS
C2HYS
C1SYNC
C2SYNC
318
C1POL
C1SP
C1R
C1CH<1:0>
317
C2POL
C2SP
C2R
C2CH<1:0>
317
C1RSEL C2RSEL
DACNSS
DACR<4:0>
FVRS<1:0>
PEIE/GIEL TMR0IE
DACPSS<1:0>
347
348
344
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
129
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
PMD2
ADCMD
57
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
156
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
Legend: = unimplemented locations, read as 0. Shaded bits are not used by the comparator module.
DS41412F-page 319
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 320
PIC18(L)F2X/4XK22
19.0
CHARGE TIME
MEASUREMENT UNIT (CTMU)
FIGURE 19-1:
CTMUCONH/CTMUCONL
EDGEN
EDGSEQEN
EDG1SELx
EDG1POL
EDG2SELx
EDG2POL
CTED1
CTED2
ECCP2
ECCP1
CTMUICON
ITRIM<5:0>
IRNG<1:0>
EDG1STAT
EDG2STAT
Edge
Control
Logic
Current Source
Current
Control
TGEN
IDISSEN
CTTRIG
CTMU
Control
Logic
Pulse
Generator
CTPLS
Comparator 2 Output
DS41412F-page 321
PIC18(L)F2X/4XK22
19.1
CTMU Operation
19.1.1
THEORY OF OPERATION
19.1.2
CURRENT SOURCE
19.1.3
19.1.4
EDGE STATUS
DS41412F-page 322
PIC18(L)F2X/4XK22
The module uses the edge Status bits to control the
current source output to external analog modules (such
as the A/D Converter). Current is only supplied to
external modules when only one (but not both) of the
Status bits is set, and shuts current off when both bits
are either set or cleared. This allows the CTMU to
measure current only during the interval between
edges. After both Status bits are set, it is necessary to
clear them before another measurement is taken. Both
bits should be cleared simultaneously, if possible, to
avoid re-enabling the CTMU current source.
In addition to being set by the CTMU hardware, the
edge Status bits can also be set by software. This is
also the users application to manually enable or
disable the current source. Setting either one (but not
both) of the bits enables the current source. Setting or
clearing both bits at once disables the source.
19.1.5
INTERRUPTS
19.2
DS41412F-page 323
PIC18(L)F2X/4XK22
19.3
FIGURE 19-2:
19.3.1
4.
5.
6.
PIC18(L)FXXK22 Device
CTMU
Current Source
A/D Converter
ANx
A/D
RCAL
MUX
DS41412F-page 324
PIC18(L)F2X/4XK22
EXAMPLE 19-1:
#include "p18cxxx.h"
/**************************************************************************/
/*Set up CTMU *****************************************************************/
/**************************************************************************/
void setup(void)
{ //CTMUCONH/1 - CTMU Control registers
CTMUCONH = 0x00;
//make sure CTMU is disabled
CTMUCONL = 0x90;
//CTMU continues to run when emulator is stopped,CTMU continues
//to run in idle mode,Time Generation mode disabled, Edges are blocked
//No edge sequence order, Analog current source not grounded, trigger
//output disabled, Edge2 polarity = positive level, Edge2 source =
//source 0, Edge1 polarity = positive level, Edge1 source = source 0,
// ADCON1
ADCON1bits.PVCFG0 =0;
ADCON1bits.NVCFG1 =0;
// ADCON0
ADCON0bits.CHS=2;
ADCON0bits.ADON=1;
// Vref+ = AVdd
// Vref- = AVss
// Select ADC channel
// Turn on ADC
DS41412F-page 325
PIC18(L)F2X/4XK22
EXAMPLE 19-2:
#include "p18cxxx.h"
#define COUNT 500
#define DELAY for(i=0;i<COUNT;i++)
#define RCAL .027
DELAY;
CTMUCONLbits.EDG1STAT = 0;
PIR1bits.ADIF = 0;
ADCON0bits.GO=1;
while(!PIR1bits.ADIF);
Vread = ADRES;
PIR1bits.ADIF = 0;
VTot += Vread;
}
Vavg = (float)(VTot/10.000);
Vcal = (float)(Vavg/ADSCALE*ADREF);
CTMUISrc = Vcal/RCAL;
//Average of 10 readings
//CTMUISrc is in 1/100ths of uA
DS41412F-page 326
PIC18(L)F2X/4XK22
19.3.2
CAPACITANCE CALIBRATION
DS41412F-page 327
PIC18(L)F2X/4XK22
EXAMPLE 19-3:
#include "p18cxxx.h"
#define
#define
#define
#define
bits
#define
#define
COUNT 25
ETIME COUNT*2.5
DELAY for(i=0;i<COUNT;i++)
ADSCALE 1023
ADREF 3.3
RCAL .027
int main(void)
{
int i;
int j = 0;
//index for loop
unsigned int Vread = 0;
float CTMUISrc, CTMUCap, Vavg, VTot, Vcal;
//assume CTMU and A/D have been set up correctly
//see Example 25-1 for CTMU & A/D setup
setup();
CTMUCONHbits.CTMUEN = 1;
CTMUCONLbits.EDG1STAT = 0;
CTMUCONLbits.EDG2STAT = 0;
for(j=0;j<10;j++)
{
CTMUCONHbits.IDISSEN = 1;
DELAY;
CTMUCONHbits.IDISSEN = 0;
CTMUCONLbits.EDG1STAT = 1;
DELAY;
CTMUCONLbits.EDG1STAT = 0;
PIR1bits.ADIF = 0;
ADCON0bits.GO=1;
while(!PIR1bits.ADIF);
Vread = ADRES;
PIR1bits.ADIF = 0;
VTot += Vread;
}
Vavg = (float)(VTot/10.000);
Vcal = (float)(Vavg/ADSCALE*ADREF);
CTMUISrc = Vcal/RCAL;
CTMUCap = (CTMUISrc*ETIME/Vcal)/100;
//Average of 10 readings
//CTMUISrc is in 1/100ths of uA
DS41412F-page 328
PIC18(L)F2X/4XK22
19.4
19.4.1
ABSOLUTE CAPACITANCE
MEASUREMENT
8.
19.4.2
RELATIVE CHARGE
MEASUREMENT
DS41412F-page 329
PIC18(L)F2X/4XK22
EXAMPLE 19-4:
#include "p18cxxx.h"
#define
#define
#define
#define
COUNT 500
DELAY for(i=0;i<COUNT;i++)
OPENSW 1000
TRIP 300
#define HYST 65
#define PRESSED 1
#define UNPRESSED 0
int main(void)
{
unsigned int Vread;
unsigned int switchState;
int i;
CTMUCONLbits.EDG1STAT = 1;
DELAY;
CTMUCONLbits.EDG1STAT = 0;
PIR1bits.ADIF = 0;
ADCON0bits.GO=1;
while(!PIR1bits.ADIF);
Vread = ADRES;
DS41412F-page 330
PIC18(L)F2X/4XK22
19.5
FIGURE 19-3:
EDG1
CTED2
EDG2
Current Source
Output Pulse
ANX
A/D Converter
CAD
RPR
DS41412F-page 331
PIC18(L)F2X/4XK22
19.6
FIGURE 19-4:
4.
5.
Initialize Comparator 2.
Initialize the comparator voltage reference.
Initialize the CTMU and enable time delay
generation by setting the TGEN bit.
Set EDG1STAT.
When CPULSE charges to the value of the voltage
reference trip point, an output pulse is generated
on CTPLS.
EDG1
CTMU
CTPLS
Current Source
Comparator
C12IN1-
CPULSE
19.7
19.7.1
C2
CVREF
19.7.2
IDLE MODE
19.8
DS41412F-page 332
PIC18(L)F2X/4XK22
19.9
19.10 Registers
CTMUCONH
CTMUCONL
CTMUICON
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
CTMUEN
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
x = Bit is unknown
DS41412F-page 333
PIC18(L)F2X/4XK22
REGISTER 19-2:
R/W-0
R/W-0
EDG2POL
R/W-0
EDG2SEL<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG1POL
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-5
bit 4
bit 3-2
bit 1
bit 0
DS41412F-page 334
x = Bit is unknown
PIC18(L)F2X/4XK22
REGISTER 19-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM<5:0>
R/W-0
IRNG<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
TABLE 19-1:
Name
x = Bit is unknown
Bit 6
Bit 5
CTMUSIDL
CTMUCONH
CTMUEN
CTMUCONL
EDG2POL
EDG2SEL<1:0>
CTMUICON
Bit 4
Bit 3
Bit 2
TGEN
EDGEN
EDGSEQEN
EDG1POL
EDG1SEL<1:0>
ITRIM<5:0>
Bit 0
Reset
Values
on Page
IDISSEN
CTTRIG
333
EDG2STAT
EDG1STAT
334
Bit 1
IRNG<1:0>
335
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
126
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
121
PMD2
CTMUMD
CMP2MD
CMP1MD
ADCMD
57
Legend:
130
= unimplemented, read as 0. Shaded bits are not used during CTMU operation.
DS41412F-page 335
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 336
PIC18(L)F2X/4XK22
20.0
SR LATCH
20.1
Latch Operation
20.2
Latch Output
20.3
20.4
Effects of a Reset
DS41412F-page 337
PIC18(L)F2X/4XK22
FIGURE 20-1:
3
SRCLK<2:0>
Programmable
SRCLK divider
1:4 to 1:512
Peripheral
Clock
t0
t0+4
t0+8
DIVSRCLK
4-512 cycles
...
t0+12
Tosc
SRCLK<2:0> = "001"
1:8
FIGURE 20-2:
SRPS
Pulse
Gen(2)
SRQEN
SRI
S
SRSPE
DIVSRCLK
Q
SRQ
SRSCKE
sync_C2OUT(3)
SRSC2E
sync_C1OUT(3)
SRSC1E
SRPR
SR
Latch(1)
Pulse
Gen(2)
SRI
SRRPE
DIVSRCLK
SRRCKE
sync_C2OUT(3)
SRRC2E
Q
SRNQ
SRLEN
SRNQEN
sync_C1OUT(3)
SRRC1E
Note 1:
2:
3:
DS41412F-page 338
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
Pulse generator causes a pulse width of 2 TOSC clock cycles.
Name denotes the connection point at the comparator output.
PIC18(L)F2X/4XK22
TABLE 20-1:
SRCLK<2:0>
Divider
FOSC = 20 MHz
FOSC = 16 MHz
111
512
25.6 s
32 s
64 s
128 s
512 s
110
256
12.8 s
16 s
32 s
64 s
256 s
101
128
6.4 s
8 s
16 s
32 s
128 s
100
64
3.2 s
4 s
8 s
16 s
64 s
011
32
1.6 s
2 s
4 s
8 s
32 s
010
16
0.8 s
1 s
2 s
4 s
16 s
001
0.4 s
0.5 s
1 s
2 s
8 s
000
0.2 s
0.25 s
0.5 s
1 s
4 s
FOSC = 1 MHz
DS41412F-page 339
PIC18(L)F2X/4XK22
20.5
REGISTER 20-1:
R/W-0
SRLEN
R/W-0
R/W-0
SRCLK<2:0>
R/W-0
R/W-0
R/W-0
R/W-0
SRQEN
SRNQEN
SRPS
SRPR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
Set only, always reads back 0.
DS41412F-page 340
PIC18(L)F2X/4XK22
REGISTER 20-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SRSPE
SRSCKE
SRSC2E
SRSC1E
SRRPE
SRRCKE
SRRC2E
SRRC1E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TABLE 20-2:
Name
Bit 6
Bit 5
SRCON0
SRLEN
SRCON1
SRSPE
SRSCKE
TRISA
TRISA7
TRISB
WPUB
Bit 4
SRCLK<2:0>
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
SRQEN
SRNQEN
SRPS
SRPR
340
SRSC2E SRSC1E
SRRPE
SRRCKE
SRRC2E
SRRC1E
341
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
156
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
156
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
157
DS41412F-page 341
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 342
PIC18(L)F2X/4XK22
21.0
21.1
21.2
FIGURE 21-1:
FVR_buf2_enable(1)
x1
x2
x4
FVRS<1:0>
FVR BUF2
to ADC module
2
x1
x2
x4
FVR BUF1
to Comparators, DAC
1.024V
+
FVREN
Fixed
Voltage
Reference
FVRST
DS41412F-page 343
PIC18(L)F2X/4XK22
21.3
REGISTER 21-1:
R/W-0
R/W-0
FVREN
FVRST
R/W-0
R/W-1
U-0
U-0
U-0
U-0
FVRS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
Unimplemented: Read as 0.
TABLE 21-1:
Name
VREFCON0
Legend:
Bit 6
FVREN
FVRST
Bit 5
Bit 4
FVRS<1:0>
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
344
= unimplemented locations, read as 0. Shaded bits are not used by the FVR module.
DS41412F-page 344
PIC18(L)F2X/4XK22
22.0
DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
22.4
22.1
EQUATION 22-1:
DACR<4:0>
VOUT = VSRC+ VSRC- ------------------------------- + VSRC5
22.2
22.3
22.5
22.6
DS41412F-page 345
PIC18(L)F2X/4XK22
FIGURE 22-1:
11
10
FVR BUF1
VREF+
VSRC+
DACR<4:0>
01
00
VDD
5
R
2
R
DACPSS<1:0>
11111
11110
DACEN
DACLPS
R
32
Steps
R
32-to-1 MUX
DAC Output
(to Comparators and
ADC Modules)
R
DACOUT
00001
R
00000
DACOE
DACNSS
FIGURE 22-2:
VREF-
VSS
VSRC-
DAC
Module
R
Voltage
Reference
Output
Impedance
DS41412F-page 346
DACOUT
PIC18(L)F2X/4XK22
22.7
22.8
22.9
Effects of a Reset
REGISTER 22-1:
R/W-0
R/W-0
R/W-0
U-0
DACEN
DACLPS
DACOE
R/W-0
R/W-0
U-0
R/W-0
DACNSS
DACPSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-2
bit 1
Unimplemented: Read as 0
bit 0
DS41412F-page 347
PIC18(L)F2X/4XK22
REGISTER 22-2:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DACR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
TABLE 22-1:
Name
Bit 6
Bit 5
VREFCON0
FVREN
FVRST
VREFCON1
DACEN
DACLPS
DACOE
VREFCON2
Legend:
Bit 4
FVRS<1:0>
Bit 0
Register
on Page
344
DACNSS
Bit 3
Bit 2
Bit 1
DACPSS<1:0>
DACR<4:0>
347
348
= Unimplemented locations, read as 0. Shaded bits are not used by the DAC module.
DS41412F-page 348
PIC18(L)F2X/4XK22
23.0
HIGH/LOW-VOLTAGE DETECT
(HLVD)
The PIC18(L)F2X/4XK22 devices have a High/Low-Voltage Detect module (HLVD). This is a programmable circuit that sets both a device voltage trip point and the
direction of change from that point. If the device experiences an excursion past the trip point in that direction, an
interrupt flag is set. If the interrupt is enabled, the program execution branches to the interrupt vector address
and the software responds to the interrupt.
23.1
REGISTER 23-1:
R/W-0
R-0
R-0
R/W-0
VDIRMAG
BGVST
IRVST
HLVDEN
R/W-0
R/W-1
R/W-0
R/W-1
HLVDL<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
DS41412F-page 349
PIC18(L)F2X/4XK22
The module is enabled by setting the HLVDEN bit
(HLVDCON<4>). Each time the HLVD module is
enabled, the circuitry requires some time to stabilize.
The IRVST bit (HLVDCON<5>) is a read-only bit used
to indicate when the circuit is stable. The module can
only generate an interrupt after the circuit is stable and
IRVST is set.
23.2
Operation
FIGURE 23-1:
Externally Generated
Trip Point
VDD
VDD
HLVDL<3:0>
HLVDCON
Register
HLVDEN
16-to-1 MUX
HLVDIN
VDIRMAG
Set
HLVDIF
HLVDEN
BOREN
DS41412F-page 350
Internal Voltage
Reference
1.024V Typical
PIC18(L)F2X/4XK22
23.3
HLVD Setup
23.4
23.5
Current Consumption
FIGURE 23-2:
CASE 1:
Enable HLVD
TIRVST
IRVST
CASE 2:
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is stable
DS41412F-page 351
PIC18(L)F2X/4XK22
FIGURE 23-3:
CASE 1:
Enable HLVD
TIRVST
IRVST
HLVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is stable
Applications
DS41412F-page 352
FIGURE 23-4:
TYPICAL LOW-VOLTAGE
DETECT APPLICATION
VA
VB
Voltage
23.6
Time
TA
TB
PIC18(L)F2X/4XK22
23.7
23.8
TABLE 23-1:
Effects of a Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
HLVDCON
VDIRMAG
BGVST
IRVST
HLVDEN
INTCON
GIE/GIEH PEIE/GIEL
Bit 3
Bit 2
Bit 1
Bit 0
HLVDL<3:0>
Reset
Values
on page
349
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
116
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
129
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
125
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
120
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
156
Legend: = unimplemented locations, read as 0. Shaded bits are unused by the HLVD module.
DS41412F-page 353
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 354
PIC18(L)F2X/4XK22
24.0
SPECIAL FEATURES OF
THE CPU
24.1
Configuration Bits
DS41412F-page 355
PIC18(L)F2X/4XK22
TABLE 24-1:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
0000 0000
300000h
CONFIG1L
300001h
CONFIG1H
IESO
FCMEN
PRICLKEN
PLLCFG
300002h
CONFIG2L
300003h
CONFIG2H
300004h
CONFIG3L
300005h
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
300006h
CONFIG4L
DEBUG
XINST
LVP(1)
STRVEN
1000 0101
300007h
CONFIG4H
1111 1111
300008h
CONFIG5L
CP3(2)
CP2(2)
CP1
CP0
0000 1111
300009h
CONFIG5H
CPD
CPB
1100 0000
30000Ah
CONFIG6L
WRT3(2)
WRT2(2)
WRT1
WRT0
0000 1111
30000Bh
CONFIG6H
WRTD
WRTB
WRTC(3)
1110 0000
30000Ch
CONFIG7L
EBTR3(2)
EBTR2(2)
EBTR1
EBTR0
0000 1111
EBTRB
0100 0000
FOSC<3:0>
BORV<1:0>
BOREN<1:0>
WDPS<3:0>
0010 0101
PWRTEN
0001 1111
WDTEN<1:0>
0011 1111
0000 0000
1011 1111
30000Dh
CONFIG7H
3FFFFEh
DEVID1(4)
3FFFFFh
DEVID2(4)
Legend:
Note 1:
2:
3:
4:
= unimplemented, q = value depends on condition. Shaded bits are unimplemented, read as '0'.
Can only be changed when in high voltage programming mode.
Available on PIC18(L)FX5K22 and PIC18(L)FX6K22 devices only.
In user mode, this bit is read-only and cannot be self-programmed.
See Register 24-12 and Register 24-13 for DEVID values. DEVID registers are read-only and cannot be programmed by the
user.
DS41412F-page 356
DEV<2:0>
REV<4:0>
DEV<10:3>
qqqq qqqq
0101 qqqq
PIC18(L)F2X/4XK22
24.2
REGISTER 24-1:
R/P-0
R/P-0
R/P-1
R/P-0
IESO
FCMEN
PRICLKEN
PLLCFG
R/P-0
R/P-1
R/P-0
R/P-1
FOSC<3:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
When FOSC<3:0> is configured for HS, XT, or LP oscillator and FCMEN bit is set, then the IESO bit
should also be set to prevent a false failed clock indication and to enable automatic clock switch over from
the internal oscillator block to the external oscillator when the OST times out.
DS41412F-page 357
PIC18(L)F2X/4XK22
REGISTER 24-2:
U-0
U-0
U-0
R/P-1
R/P-1
BORV<1:0>(1)
R/P-1
R/P-1
BOREN<1:0>(2)
R/P-1
PWRTEN(2)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7-5
Unimplemented: Read as 0
bit 4-3
bit 2-1
bit 0
Note
1:
2:
DS41412F-page 358
PIC18(L)F2X/4XK22
REGISTER 24-3:
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS<3:0>
R/P-1
R/P-1
WDTEN<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7-6
Unimplemented: Read as 0
bit 5-2
bit 1-0
DS41412F-page 359
PIC18(L)F2X/4XK22
REGISTER 24-4:
R/P-1
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
DS41412F-page 360
PIC18(L)F2X/4XK22
REGISTER 24-5:
R/P-1
DEBUG
(2)
U-0
XINST
U-0
U-0
R/P-1
LVP
(1)
U-0
R/P-1
STVREN
bit 0
bit 7
Legend:
R = Readable bit
P = Programmable bit
x = Bit is unknown
bit 7
bit 6
bit 5-3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
Note 1:
2:
REGISTER 24-6:
U-0
U-0
U-0
R/C-1
R/C-1
R/C-1
R/C-1
CP3(1)
CP2(1)
CP1
CP0
bit 7
bit 0
Legend:
R = Readable bit
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note 1:
DS41412F-page 361
PIC18(L)F2X/4XK22
REGISTER 24-7:
R/C-1
R/C-1
U-0
U-0
U-0
U-0
U-0
U-0
CPD
CPB
bit 7
bit 0
Legend:
R = Readable bit
bit 7
bit 6
bit 5-0
Unimplemented: Read as 0
REGISTER 24-8:
U-0
U-0
U-0
R/C-1
R/C-1
R/C-1
R/C-1
WRT3(1)
WRT2(1)
WRT1
WRT0
bit 7
bit 0
Legend:
R = Readable bit
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note 1:
DS41412F-page 362
PIC18(L)F2X/4XK22
REGISTER 24-9:
R/C-1
WRTD
WRTB
R-1
(1)
WRTC
U-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
bit 7
bit 6
bit 5
bit 4-0
Note 1:
Unimplemented: Read as 0
This bit is read-only in normal execution mode; it can be written only in Program mode.
U-0
U-0
U-0
R/C-1
R/C-1
R/C-1
R/C-1
EBTR3(1)
EBTR2(1)
EBTR1
EBTR0
bit 7
bit 0
Legend:
R = Readable bit
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note 1:
DS41412F-page 363
PIC18(L)F2X/4XK22
REGISTER 24-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH
U-0
R/C-1
U-0
U-0
U-0
U-0
U-0
U-0
EBTRB
bit 7
bit 0
Legend:
R = Readable bit
bit 7
Unimplemented: Read as 0
bit 6
bit 5-0
Unimplemented: Read as 0
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Readable bit
bit 7-5
bit 4-0
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Readable bit
bit 7-0
DS41412F-page 364
PIC18(L)F2X/4XK22
TABLE 24-2:
DEV<10:3>
0101 0100
0101 0101
0101 0110
0101 0111
DEV<2:0>
Part Number
000
PIC18F46K22
001
PIC18LF46K22
010
PIC18F26K22
011
PIC18LF26K22
000
PIC18F45K22
001
PIC18LF45K22
010
PIC18F25K22
011
PIC18LF25K22
000
PIC18F44K22
001
PIC18LF44K22
010
PIC18F24K22
011
PIC18LF24K22
000
PIC18F43K22
001
PIC18LF43K22
010
PIC18F23K22
011
PIC18LF23K22
DS41412F-page 365
PIC18(L)F2X/4XK22
24.3
FIGURE 24-1:
SWDTEN
WDTEN
LFINTOSC Source
128
Wake-up
from Power
Managed Modes
CLRWDT
Reset
WDT
Reset
Sleep
DS41412F-page 366
PIC18(L)F2X/4XK22
24.3.1
CONTROL REGISTER
24.4
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
SWDTEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-1
Unimplemented: Read as 0
bit 0
Note 1:
x = Bit is unknown
TABLE 24-3:
Name
RCON
WDTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
IPEN
SBOREN
RI
TO
PD
POR
BOR
60
SWDTEN
367
Legend: = unimplemented, read as 0. Shaded bits are not used by the Watchdog Timer.
TABLE 24-4:
Name
Bit 7
Bit 6
CONFIG2H
Bit 5
Bit 4
Bit 3
WDPS<3:0>
Bit 2
Bit 1
Bit 0
WDTEN<1:0>
Reset
Values
on Page
359
Legend: = unimplemented, read as 0. Shaded bits are not used by the Watchdog Timer.
DS41412F-page 367
PIC18(L)F2X/4XK22
24.5
Each of the blocks has three code protection bits associated with them. They are:
FIGURE 24-2:
8 Kbytes
16 Kbytes
32 Kbytes
64 Kbytes
(PIC18(L)FX3K22) (PIC18(L)FX4K22) (PIC18(L)FX5K22) (PIC18(L)FX6K22)
Boot Block
(000h-1FFh)
Boot Block
(000h-7FFh)
Boot Block
(000h-7FFh)
Boot Block
(000h-7FFh)
Block 0
(200h-FFFh)
Block 0
(800h-1FFFh)
Block 0
(800h-1FFFh)
Block 0
(800h-3FFFh)
Block 1
(1000h-1FFFh)
Block 1
(2000h-3FFFh)
Block 1
(2000h-3FFFh)
Block 1
(4000h-7FFFh)
Block 2
(4000h-5FFFh)
Block 2
(8000h-BFFFh)
Block 3
(6000h-7FFFh)
Block 3
(C000h-FFFFh)
Unimplemented
Read 0s
(2000h-1FFFFFh)
Unimplemented
Read 0s
(4000h-1FFFFFh)
Unimplemented
Unimplemented
Read 0s
Read 0s
(8000h-1FFFFFh) (10000h-1FFFFFh)
TABLE 24-5:
(Unimplemented
Memory Space)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CP3(1)
CP2(1)
CP1
CP0
300008h
CONFIG5L
300009h
CONFIG5H
CPD
CPB
30000Ah
CONFIG6L
WRT3(1)
WRT2(1)
WRT1
WRT0
30000Bh
CONFIG6H
WRTD
WRTB
WRTC(2)
30000Ch
CONFIG7L
EBTR3(1)
EBTR2(1)
EBTR1
EBTR0
30000Dh
CONFIG7H
EBTRB
DS41412F-page 368
PIC18(L)F2X/4XK22
24.5.1
PROGRAM MEMORY
CODE PROTECTION
FIGURE 24-3:
Register Values
Program Memory
WRTB, EBTRB = 11
TBLPTR = 0008FFh
WRT0, EBTR0 = 01
PC = 001FFEh
TBLWT*
001FFFh
002000h
WRT1, EBTR1 = 11
003FFFh
004000h
PC = 005FFEh
WRT2, EBTR2 = 11
TBLWT*
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table writes disabled to Blockn whenever WRTn = 0.
DS41412F-page 369
PIC18(L)F2X/4XK22
FIGURE 24-4:
Register Values
Program Memory
WRTB, EBTRB = 11
TBLPTR = 0008FFh
WRT0, EBTR0 = 10
001FFFh
002000h
PC = 003FFEh
TBLRD*
WRT1, EBTR1 = 11
003FFFh
004000h
WRT2, EBTR2 = 11
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of 0.
FIGURE 24-5:
Register Values
Program Memory
TBLPTR = 0008FFh
PC = 001FFEh
WRT0, EBTR0 = 10
TBLRD*
001FFFh
002000h
WRT1, EBTR1 = 11
003FFFh
004000h
WRT2, EBTR2 = 11
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
DS41412F-page 370
PIC18(L)F2X/4XK22
24.5.2
DATA EEPROM
CODE PROTECTION
24.5.3
CONFIGURATION REGISTER
PROTECTION
24.6
ID Locations
24.7
24.8
In-Circuit Debugger
TABLE 24-6:
I/O pins:
MCLR/VPP/RE3
VDD
VSS
RB7
RB6
24.9
DEBUGGER RESOURCES
RB6, RB7
DS41412F-page 371
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 372
PIC18(L)F2X/4XK22
25.0
25.1
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
DS41412F-page 373
PIC18(L)F2X/4XK22
TABLE 25-1:
Field
Description
bbb
BSR
C, DC, Z, OV, N
dest
Destination: either the WREG register or the specified register file location.
8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
fs
12-bit Register file address (000h to FFFh). This is the source address.
fd
12-bit Register file address (000h to FFFh). This is the destination address.
GIE
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label
Label name.
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*+
*-
+*
n
The relative address (2s complement number) for relative branch instructions or the direct address for
CALL/BRANCH and RETURN instructions.
PC
Program Counter.
PCL
PCH
PCLATH
PCLATU
PD
Power-down bit.
PRODH
PRODL
TBLPTR
TABLAT
TO
Time-out bit.
TOS
Top-of-Stack.
Unused or unchanged.
WDT
Watchdog Timer.
WREG
Dont care (0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs
zd
{
Optional argument.
[text]
(text)
[expr]<n>
Assigned to.
< >
italics
DS41412F-page 374
PIC18(L)F2X/4XK22
FIGURE 25-1:
10
9 8 7
OPCODE d
a
Example Instruction
0
f (FILE #)
ADDWF MYREG, W, B
0
f (Source FILE #)
12 11
f (Destination FILE #)
1111
12 11
9 8 7
OPCODE b (BIT #) a
0
f (FILE #)
OPCODE
0
k (literal)
MOVLW 7Fh
8 7
OPCODE
15
0
n<7:0> (literal)
12 11
GOTO Label
0
n<19:8> (literal)
1111
8 7
OPCODE
15
0
CALL MYFUNC
n<7:0> (literal)
12 11
0
n<19:8> (literal)
1111
S = Fast bit
15
11 10
OPCODE
15
OPCODE
0
BRA MYFUNC
n<10:0> (literal)
8 7
n<7:0> (literal)
0
BC MYFUNC
DS41412F-page 375
PIC18(L)F2X/4XK22
TABLE 25-2:
Mnemonic,
Operands
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
SUBWF
SUBWFB
f, d, a
f, d, a
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
Note 1:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an
external device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
2:
3:
4:
DS41412F-page 376
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101
0101
11da
10da
ffff
ffff
1, 2
1
1 (2 or 3)
1
0011
0110
0001
10da
011a
10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
1, 2
1, 2
1, 2
PIC18(L)F2X/4XK22
TABLE 25-2:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, b, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
None
None
None
None
None
None
None
None
None
None
1
1
1
1
2
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
2
2
1
0000
0000
0000
1100
0000
0000
kkkk
0001
0000
1, 2
1, 2
3, 4
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
k, s
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
n
s
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
RETLW
RETURN
SLEEP
k
s
Note 1:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an
external device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
2:
3:
4:
1
1
2
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
DS41412F-page 377
PIC18(L)F2X/4XK22
TABLE 25-2:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
None
None
None
None
C, DC, Z, OV, N
Z, N
2:
3:
4:
Table Read
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an
external device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
DS41412F-page 378
PIC18(L)F2X/4XK22
25.1.1
ADDLW
ADD literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
Syntax:
ADDWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
Operands:
0 k 255
Operation:
(W) + k W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1111
kkkk
kkkk
Description:
Words:
Cycles:
Encoding:
0010
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to W
Example:
ADDLW
25h
ffff
Words:
Cycles:
Before Instruction
ffff
15h
W
= 10h
After Instruction
01da
Description:
Q Cycle Activity:
Decode
f {,d {,a}}
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
=
REG
=
After Instruction
W
REG
Note:
=
=
17h
0C2h
0D9h
0C2h
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS41412F-page 379
PIC18(L)F2X/4XK22
ADDWFC
ANDLW
Syntax:
ADDWFC
Syntax:
ANDLW
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 k 255
Operation:
(W) .AND. k W
Operation:
Status Affected:
N, Z
Status Affected:
N,OV, C, DC, Z
Encoding:
0010
Description:
f {,d {,a}}
Encoding:
00da
ffff
ffff
Add W, the CARRY flag and data memory location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank.
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words:
Cycles:
0000
1011
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
k
Process
Data
Write to W
Example:
ANDLW
05Fh
Before Instruction
W
=
After Instruction
W
A3h
03h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
ADDWFC
Before Instruction
CARRY bit =
REG
=
W
=
After Instruction
CARRY bit =
REG
=
W
=
DS41412F-page 380
REG, 0, 1
1
02h
4Dh
0
02h
50h
PIC18(L)F2X/4XK22
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF
Syntax:
BC
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
-128 n 127
Operation:
if CARRY bit is 1
(PC) + 2 + 2n PC
Status Affected:
None
f {,d {,a}}
Operation:
Status Affected:
N, Z
Encoding:
0001
Description:
Encoding:
01da
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
ANDWF
REG, 0, 0
Before Instruction
W
=
REG
=
After Instruction
W
REG
=
=
17h
C2h
02h
C2h
1110
Description:
0010
nnnn
nnnn
Words:
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
After Instruction
If CARRY
PC
If CARRY
PC
BC
address (HERE)
=
=
=
=
1;
address (HERE + 12)
0;
address (HERE + 2)
DS41412F-page 381
PIC18(L)F2X/4XK22
BCF
Bit Clear f
BN
Branch if Negative
Syntax:
BCF
Syntax:
BN
Operands:
0 f 255
0b7
a [0,1]
Operands:
-128 n 127
Operation:
if NEGATIVE bit is 1
(PC) + 2 + 2n PC
Status Affected:
None
f, b {,a}
Operation:
0 f<b>
Status Affected:
None
Encoding:
Encoding:
1001
Description:
bbba
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
BCF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
DS41412F-page 382
FLAG_REG,
7, 0
1110
Description:
0110
nnnn
nnnn
Words:
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
C7h
47h
Example:
HERE
Before Instruction
PC
After Instruction
If NEGATIVE
PC
If NEGATIVE
PC
BN
Jump
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
PIC18(L)F2X/4XK22
BNC
BNN
Syntax:
BNC
Syntax:
BNN
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if CARRY bit is 0
(PC) + 2 + 2n PC
Operation:
if NEGATIVE bit is 0
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0011
nnnn
nnnn
Encoding:
1110
Description:
Words:
Words:
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0111
nnnn
nnnn
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Decode
Read literal
n
Process
Data
No
operation
If No Jump:
Example:
If No Jump:
HERE
Before Instruction
PC
After Instruction
If CARRY
PC
If CARRY
PC
BNC
Jump
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
Example:
HERE
Before Instruction
PC
After Instruction
If NEGATIVE
PC
If NEGATIVE
PC
BNN
Jump
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
DS41412F-page 383
PIC18(L)F2X/4XK22
BNOV
BNZ
Syntax:
BNOV
Syntax:
BNZ
Operands:
-128 n 127
Operands:
-128 n 127
Operation:
if OVERFLOW bit is 0
(PC) + 2 + 2n PC
Operation:
if ZERO bit is 0
(PC) + 2 + 2n PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0101
nnnn
nnnn
Encoding:
1110
Description:
Words:
Words:
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
0001
nnnn
nnnn
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
Decode
Read literal
n
Process
Data
No
operation
If No Jump:
If No Jump:
Example:
HERE
Before Instruction
PC
=
After Instruction
If OVERFLOW =
PC
=
If OVERFLOW =
PC
=
DS41412F-page 384
BNOV Jump
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
Example:
HERE
Before Instruction
PC
After Instruction
If ZERO
PC
If ZERO
PC
BNZ
Jump
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
PIC18(L)F2X/4XK22
BRA
Unconditional Branch
BSF
Syntax:
BRA
Syntax:
BSF
Operands:
-1024 n 1023
Operands:
0 f 255
0b7
a [0,1]
Operation:
(PC) + 2 + 2n PC
Status Affected:
None
Encoding:
1101
Description:
0nnn
nnnn
nnnn
Words:
Cycles:
Bit Set f
Operation:
1 f<b>
Status Affected:
None
Encoding:
1000
Q1
Q2
Q3
Q4
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
bbba
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Decode
f, b {,a}
Q Cycle Activity:
HERE
Before Instruction
PC
After Instruction
PC
BRA
Jump
address (HERE)
address (Jump)
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
BSF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
FLAG_REG, 7, 1
0Ah
8Ah
DS41412F-page 385
PIC18(L)F2X/4XK22
BTFSC
BTFSS
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 f 255
0b7
a [0,1]
Operands:
0 f 255
0b<7
a [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
None
Status Affected:
None
Encoding:
1011
bbba
ffff
ffff
Encoding:
1010
bbba
ffff
ffff
Description:
Description:
Words:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note:
Q Cycle Activity:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
Decode
Read
register f
Process
Data
No
operation
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
Before Instruction
PC
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
DS41412F-page 386
BTFSC
:
:
FLAG, 1, 0
address (HERE)
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
Example:
HERE
FALSE
TRUE
Before Instruction
PC
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
BTFSS
:
:
FLAG, 1, 0
address (HERE)
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
PIC18(L)F2X/4XK22
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
BTG f, b {,a}
Syntax:
BOV
Operands:
0 f 255
0b<7
a [0,1]
Operands:
-128 n 127
Operation:
if OVERFLOW bit is 1
(PC) + 2 + 2n PC
Status Affected:
None
Operation:
(f<b>) f<b>
Status Affected:
None
Encoding:
0111
Description:
Words:
Cycles:
Encoding:
bbba
ffff
ffff
1110
Description:
0100
nnnn
nnnn
Words:
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
BTG
PORTC,
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
4, 0
Before Instruction:
PORTC =
0111 0101 [75h]
After Instruction:
PORTC =
0110 0101 [65h]
If No Jump:
Example:
HERE
Before Instruction
PC
=
After Instruction
If OVERFLOW =
PC
=
If OVERFLOW =
PC
=
BOV
Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
DS41412F-page 387
PIC18(L)F2X/4XK22
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
BZ
Syntax:
CALL k {,s}
Operands:
-128 n 127
Operands:
Operation:
if ZERO bit is 1
(PC) + 2 + 2n PC
0 k 1048575
s [0,1]
Operation:
(PC) + 4 TOS,
k PC<20:1>,
if s = 1
(W) WS,
(Status) STATUSS,
(BSR) BSRS
Status Affected:
None
Status Affected:
None
Encoding:
1110
Description:
0000
nnnn
nnnn
Words:
Cycles:
1(2)
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Q1
Q2
Q3
Q4
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
No
operation
If No Jump:
Example:
HERE
Before Instruction
PC
After Instruction
If ZERO
PC
If ZERO
PC
DS41412F-page 388
BZ
k7kkk
kkkk
110s
k19kkk
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Jump
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
kkkk0
kkkk8
Description:
Q Cycle Activity:
If Jump:
Decode
1110
1111
No
operation
Example:
No
operation
HERE
Before Instruction
PC
=
After Instruction
PC
=
TOS
=
WS
=
BSRS
=
STATUSS =
No
operation
CALL
Read literal
k<19:8>,
Write to PC
No
operation
THERE, 1
address (HERE)
address (THERE)
address (HERE + 4)
W
BSR
Status
PIC18(L)F2X/4XK22
CLRF
Clear f
Syntax:
CLRF
Operands:
0 f 255
a [0,1]
Operation:
000h f
1Z
Status Affected:
Encoding:
f {,a}
0110
Description:
101a
ffff
ffff
Words:
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
CLRF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Syntax:
CLRWDT
Operands:
None
Operation:
000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected:
TO, PD
Encoding:
FLAG_REG, 1
5Ah
00h
0000
0000
0000
0100
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Example:
Q Cycle Activity:
Example:
CLRWDT
CLRWDT
Before Instruction
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
PD
=
=
=
=
00h
0
1
1
DS41412F-page 389
PIC18(L)F2X/4XK22
COMF
Complement f
CPFSEQ
Syntax:
COMF
Syntax:
CPFSEQ
Operands:
0 f 255
a [0,1]
Operation:
(f) (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
f {,d {,a}}
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
(f) dest
Status Affected:
N, Z
Encoding:
0001
11da
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Encoding:
0110
Description:
f {,a}
001a
ffff
ffff
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Example:
COMF
Before Instruction
REG
=
After Instruction
REG
=
W
=
REG, 0, 0
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
13h
If skip:
13h
ECh
Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation
Example:
DS41412F-page 390
HERE
NEQUAL
EQUAL
Q4
No
operation
Q4
No
operation
No
operation
CPFSEQ REG, 0
:
:
Before Instruction
PC Address
W
REG
After Instruction
=
=
=
HERE
?
?
If REG
PC
If REG
PC
=
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
PIC18(L)F2X/4XK22
CPFSGT
CPFSLT
Syntax:
CPFSGT
Syntax:
CPFSLT
Operands:
0 f 255
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
0110
Description:
Words:
f {,a}
010a
ffff
ffff
Encoding:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q2
Read
register f
Q3
Process
Data
Q4
No
operation
Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation
Q4
No
operation
Example:
HERE
NGREATER
GREATER
CPFSGT REG, 0
:
:
Before Instruction
PC
W
After Instruction
=
=
Address (HERE)
?
If REG
PC
If REG
PC
W;
Address (GREATER)
W;
Address (NGREATER)
ffff
ffff
Words:
Cycles:
1(2)
Note:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
Q4
No
operation
No
operation
000a
Q Cycle Activity:
Q1
Decode
0110
Description:
Cycles:
f {,a}
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Before Instruction
PC
W
After Instruction
=
=
Address (HERE)
?
If REG
PC
If REG
PC
<
=
W;
Address (LESS)
W;
Address (NLESS)
DS41412F-page 391
PIC18(L)F2X/4XK22
DAW
DECF
Syntax:
DAW
Syntax:
Operands:
None
Operands:
Operation:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) 1 dest
Status Affected:
C, DC, N, OV, Z
Decrement f
Encoding:
0000
0000
0000
0000
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example1:
DAW
ffff
Words:
0111
Description:
ffff
Encoding:
01da
Description:
Before Instruction
W
=
C
=
DC
=
After Instruction
W
C
DC
Example 2:
=
=
=
A5h
0
0
05h
1
0
Example:
DECF
Before Instruction
CNT
=
Z
=
After Instruction
CNT
=
Z
=
CNT,
1, 0
01h
0
00h
1
Before Instruction
W
=
C
=
DC
=
After Instruction
W
C
DC
=
=
=
DS41412F-page 392
CEh
0
0
34h
1
0
PIC18(L)F2X/4XK22
DECFSZ
Decrement f, skip if 0
DCFSNZ
Syntax:
Syntax:
DCFSNZ
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) 1 dest,
skip if result = 0
Operation:
(f) 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
Description:
11da
ffff
ffff
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Encoding:
0100
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
DECFSZ
GOTO
Example:
CNT, 1, 1
LOOP
CONTINUE
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC =
If CNT
PC =
Address (HERE)
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
ffff
ffff
Words:
Cycles:
1(2)
Note:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip:
11da
Description:
Q Cycle Activity:
Q1
f {,d {,a}}
If skip:
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
ZERO
NZERO
Before Instruction
TEMP
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
DCFSNZ
:
:
TEMP, 1, 0
=
=
=
TEMP 1,
0;
Address (ZERO)
0;
Address (NZERO)
DS41412F-page 393
PIC18(L)F2X/4XK22
GOTO
Unconditional Branch
INCF
Syntax:
GOTO k
Syntax:
INCF
Operands:
0 k 1048575
Operands:
Operation:
k PC<20:1>
0 f 255
d [0,1]
a [0,1]
Status Affected:
None
Operation:
(f) + 1 dest
Status Affected:
C, DC, N, OV, Z
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
Description:
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Increment f
Encoding:
0010
Cycles:
2
Q1
Q2
Q3
Q4
Read literal
k<7:0>,
No
operation
Read literal
k<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Decode
10da
Description:
f {,d {,a}}
Q Cycle Activity:
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
INCF
Before Instruction
CNT
=
Z
=
C
=
DC
=
After Instruction
CNT
=
Z
=
C
=
DC
=
DS41412F-page 394
CNT, 1, 0
FFh
0
?
?
00h
1
1
1
PIC18(L)F2X/4XK22
INCFSZ
Increment f, skip if 0
INFSNZ
Syntax:
INCFSZ
Syntax:
INFSNZ
0 f 255
d [0,1]
a [0,1]
f {,d {,a}}
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
(f) + 1 dest,
skip if result = 0
Operation:
(f) + 1 dest,
skip if result 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
Description:
11da
ffff
ffff
Encoding:
0100
Description:
Words:
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note:
Q Cycle Activity:
10da
ffff
ffff
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Decode
Read
register f
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip:
If skip:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
=
After Instruction
CNT
=
If CNT
=
PC
=
If CNT
PC
=
INCFSZ
:
:
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
CNT, 1, 0
Example:
HERE
ZERO
NZERO
Before Instruction
PC
=
After Instruction
REG
=
If REG
PC
=
If REG
=
PC
=
INFSNZ
REG, 1, 0
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
DS41412F-page 395
PIC18(L)F2X/4XK22
IORLW
IORWF
Syntax:
IORLW k
Syntax:
IORWF
Operands:
0 k 255
Operands:
Operation:
(W) .OR. k W
0 f 255
d [0,1]
a [0,1]
Status Affected:
N, Z
Operation:
Status Affected:
N, Z
Encoding:
0000
Description:
1001
kkkk
kkkk
Words:
Cycles:
Inclusive OR W with f
Encoding:
0001
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to W
Example:
IORLW
ffff
Words:
Cycles:
35h
9Ah
BFh
ffff
Before Instruction
W
=
After Instruction
00da
Description:
Q Cycle Activity:
Decode
f {,d {,a}}
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
IORWF
Before Instruction
RESULT =
W
=
After Instruction
RESULT =
W
=
DS41412F-page 396
RESULT, 0, 1
13h
91h
13h
93h
PIC18(L)F2X/4XK22
LFSR
Load FSR
MOVF
Syntax:
LFSR f, k
Syntax:
MOVF
Operands:
0f2
0 k 4095
Operands:
Operation:
k FSRf
0 f 255
d [0,1]
a [0,1]
Status Affected:
None
Operation:
f dest
Status Affected:
N, Z
Encoding:
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
Words:
Cycles:
Move f
Encoding:
0101
Q1
Q2
Q3
Q4
Read literal
k MSB
Process
Data
Write
literal k
MSB to
FSRfH
Decode
Read literal
k LSB
Process
Data
Write literal
k to FSRfL
Example:
After Instruction
FSR2H
FSR2L
03h
ABh
ffff
ffff
Words:
Cycles:
LFSR 2, 3ABh
=
=
00da
Description:
Q Cycle Activity:
Decode
f {,d {,a}}
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write W
Example:
MOVF
Before Instruction
REG
W
After Instruction
REG
W
REG, 0, 0
=
=
22h
FFh
=
=
22h
22h
DS41412F-page 397
PIC18(L)F2X/4XK22
MOVFF
Move f to f
MOVLB
Syntax:
MOVFF fs,fd
Syntax:
MOVLW k
Operands:
0 fs 4095
0 fd 4095
Operands:
0 k 255
Operation:
k BSR
Operation:
(fs) fd
Status Affected:
None
Status Affected:
None
Encoding:
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
2 (3)
0000
0001
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
Write literal
k to BSR
MOVLB
Example:
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register f
(dest)
No dummy
read
Example:
MOVFF
Before Instruction
REG1
REG2
After Instruction
REG1
REG2
DS41412F-page 398
REG1, REG2
=
=
33h
11h
=
=
33h
33h
PIC18(L)F2X/4XK22
MOVLW
Move literal to W
MOVWF
Syntax:
MOVLW k
Syntax:
MOVWF
Operands:
0 k 255
Operands:
Operation:
kW
0 f 255
a [0,1]
Status Affected:
None
Operation:
(W) f
Status Affected:
None
Encoding:
0000
1110
kkkk
kkkk
Description:
Words:
Cycles:
Move W to f
Encoding:
0110
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to W
Example:
MOVLW
=
ffff
ffff
Words:
Cycles:
5Ah
After Instruction
W
111a
Description:
Q Cycle Activity:
Decode
f {,a}
5Ah
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
MOVWF
REG, 0
Before Instruction
W
=
REG
=
After Instruction
W
REG
=
=
4Fh
FFh
4Fh
4Fh
DS41412F-page 399
PIC18(L)F2X/4XK22
MULLW
MULWF
Multiply W with f
Syntax:
MULLW
Syntax:
MULWF
Operands:
0 k 255
Operands:
Operation:
(W) x k PRODH:PRODL
0 f 255
a [0,1]
Status Affected:
None
Operation:
Status Affected:
None
Encoding:
0000
Description:
1101
kkkk
kkkk
Words:
Cycles:
Encoding:
0000
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW
W
PRODH
PRODL
E2h
?
?
=
=
=
E2h
ADh
08h
ffff
Words:
Cycles:
0C4h
=
=
=
ffff
Before Instruction
W
PRODH
PRODL
After Instruction
001a
Description:
Q Cycle Activity:
Decode
f {,a}
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
REG
PRODH
PRODL
After Instruction
W
REG
PRODH
PRODL
DS41412F-page 400
=
=
=
=
C4h
B5h
?
?
=
=
=
=
C4h
B5h
8Ah
94h
PIC18(L)F2X/4XK22
NEGF
Negate f
NOP
No Operation
Syntax:
NEGF
Syntax:
NOP
Operands:
0 f 255
a [0,1]
Operands:
None
Operation:
(f)+1f
Status Affected:
N, OV, C, DC, Z
Encoding:
f {,a}
0110
Description:
Cycles:
No operation
Status Affected:
None
Encoding:
110a
ffff
0000
1111
ffff
Words:
Operation:
0000
xxxx
Description:
No operation.
Words:
Cycles:
0000
xxxx
0000
xxxx
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
NEGF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1
DS41412F-page 401
PIC18(L)F2X/4XK22
POP
PUSH
Syntax:
POP
Syntax:
PUSH
Operands:
None
Operands:
None
Operation:
Operation:
(PC + 2) TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
0000
0000
0110
Description:
Words:
Cycles:
Encoding:
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
POP
GOTO
NEW
Before Instruction
TOS
Stack (1 level down)
DS41412F-page 402
0000
0101
Words:
Cycles:
Q Cycle Activity:
Q1
After Instruction
TOS
PC
0000
Q Cycle Activity:
Example:
0000
Description:
Q1
Q2
Q3
Q4
Decode
PUSH
PC + 2 onto
return stack
No
operation
No
operation
Example:
=
=
=
=
0031A2h
014332h
014332h
NEW
PUSH
Before Instruction
TOS
PC
=
=
345Ah
0124h
After Instruction
PC
TOS
Stack (1 level down)
=
=
=
0126h
0126h
345Ah
PIC18(L)F2X/4XK22
RCALL
Relative Call
RESET
Reset
Syntax:
RCALL
Syntax:
RESET
Operands:
-1024 n 1023
Operands:
None
Operation:
(PC) + 2 TOS,
(PC) + 2 + 2n PC
Operation:
Status Affected:
None
Status Affected:
All
Encoding:
1101
Description:
1nnn
nnnn
nnnn
Words:
Cycles:
Encoding:
0000
Q1
Q2
Q3
Q4
Decode
Read literal
n
Process
Data
Write to PC
No
operation
No
operation
1111
1111
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
Reset
No
operation
No
operation
Example:
Q Cycle Activity:
0000
After Instruction
Registers =
Flags*
=
RESET
Reset Value
Reset Value
PUSH PC to
stack
No
operation
Example:
No
operation
HERE
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
Address (Jump)
TOS =
Address (HERE + 2)
DS41412F-page 403
PIC18(L)F2X/4XK22
RETFIE
RETLW
Return literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
s [0,1]
Operands:
0 k 255
Operation:
(TOS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) W,
(STATUSS) Status,
(BSRS) BSR,
PCLATU, PCLATH are unchanged.
Operation:
k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
0000
0000
0001
Cycles:
Q Cycle Activity:
Q2
Q3
Q4
Decode
No
operation
No
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
RETFIE
After Interrupt
PC
W
BSR
Status
GIE/GIEH, PEIE/GIEL
DS41412F-page 404
kkkk
kkkk
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
POP PC
from stack,
Write to W
No
operation
No
operation
No
operation
No
operation
Example:
Q1
Example:
1100
000s
Words:
No
operation
0000
Description:
GIE/GIEH, PEIE/GIEL.
Encoding:
Description:
Encoding:
No
operation
No
operation
1
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
Before Instruction
W
=
After Instruction
W
=
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
07h
value of kn
PIC18(L)F2X/4XK22
RETURN
RLCF
Syntax:
RETURN {s}
Syntax:
RLCF
Operands:
s [0,1]
Operands:
Operation:
(TOS) PC,
if s = 1
(WS) W,
(STATUSS) Status,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
C, N, Z
Status Affected:
None
Encoding:
0000
Encoding:
0000
0001
001s
Description:
Words:
Cycles:
0011
Description:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
from stack
No
operation
No
operation
No
operation
No
operation
f {,d {,a}}
01da
ffff
ffff
C
Words:
Cycles:
Q Cycle Activity:
Example:
RETURN
After Instruction:
PC = TOS
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
RLCF
REG, 0, 0
1110 0110
0
1110 0110
1100 1100
1
DS41412F-page 405
PIC18(L)F2X/4XK22
RLNCF
RRCF
Syntax:
RLNCF
Syntax:
RRCF
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Operation:
Status Affected:
N, Z
Status Affected:
C, N, Z
Encoding:
0100
Description:
f {,d {,a}}
01da
ffff
ffff
Encoding:
0011
Description:
register f
Words:
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Before Instruction
REG
=
After Instruction
REG
=
DS41412F-page 406
00da
RLNCF
Words:
Cycles:
0101 0111
ffff
register f
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
RRCF
REG, 0, 0
REG, 1, 0
1010 1011
ffff
Q Cycle Activity:
Example:
f {,d {,a}}
Example:
Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=
1110 0110
0
1110 0110
0111 0011
0
PIC18(L)F2X/4XK22
RRNCF
SETF
Syntax:
RRNCF
Syntax:
SETF
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
FFh f
Operation:
Status Affected:
None
Status Affected:
f {,d {,a}}
Encoding:
N, Z
Encoding:
0100
Description:
00da
ffff
ffff
Words:
Cycles:
1
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
RRNCF
Before Instruction
REG
=
After Instruction
REG
=
Example 2:
f {,a}
0110
100a
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write
register f
Example:
Q Cycle Activity:
Example 1:
Set f
SETF
Before Instruction
REG
After Instruction
REG
REG, 1
5Ah
FFh
REG, 1, 0
1101 0111
1110 1011
RRNCF
REG, 0, 0
Before Instruction
W
=
REG
=
After Instruction
?
1101 0111
=
=
1110 1011
1101 0111
W
REG
DS41412F-page 407
PIC18(L)F2X/4XK22
SLEEP
SUBFWB
Syntax:
SLEEP
Syntax:
SUBFWB
Operands:
None
Operands:
Operation:
00h WDT,
0 WDT postscaler,
1 TO,
0 PD
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, OV, C, DC, Z
Status Affected:
TO, PD
Encoding:
0000
Encoding:
0000
0000
0011
Description:
Words:
Cycles:
0101
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
Sleep
SLEEP
Before Instruction
TO =
?
PD =
?
After Instruction
1
TO =
0
PD =
If WDT causes wake-up, this bit is cleared.
DS41412F-page 408
f {,d {,a}}
01da
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
SUBFWB
REG, 1, 0
Example 1:
Before Instruction
REG
=
3
W
=
2
C
=
1
After Instruction
REG
=
FF
W
=
2
C
=
0
Z
=
0
N
=
1 ; result is negative
SUBFWB
REG, 0, 0
Example 2:
Before Instruction
REG
=
2
W
=
5
C
=
1
After Instruction
REG
=
2
W
=
3
C
=
1
Z
=
0
N
=
0 ; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
=
1
W
=
2
C
=
0
After Instruction
REG
=
0
W
=
2
C
=
1
Z
=
1 ; result is zero
N
=
0
PIC18(L)F2X/4XK22
SUBLW
SUBWF
Syntax:
SUBLW k
Syntax:
SUBWF
Operands:
0 k 255
Operands:
Operation:
k (W) W
0 f 255
d [0,1]
a [0,1]
Status Affected:
N, OV, C, DC, Z
Operation:
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
Description
1000
kkkk
kkkk
Words:
Cycles:
Subtract W from f
Encoding:
0101
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
Write to W
Example 1:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
W
=
C
=
After Instruction
W
=
C
=
Z
=
N
=
SUBLW
Cycles:
02h
Q Cycle Activity:
02h
?
00h
1
; result is zero
1
0
SUBLW
ffff
Words:
01h
?
SUBLW
ffff
02h
01h
1
; result is positive
0
0
11da
Description:
Q Cycle Activity:
Q1
f {,d {,a}}
02h
03h
?
FFh ; (2s complement)
0
; result is negative
0
1
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
SUBWF
REG, 1, 0
Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
3
2
?
1
2
1
0
0
; result is positive
SUBWF
REG, 0, 0
2
2
?
2
0
1
1
0
SUBWF
; result is zero
REG, 1, 0
1
2
?
FFh ;(2s complement)
2
0
; result is negative
0
1
DS41412F-page 409
PIC18(L)F2X/4XK22
SUBWFB
SWAPF
Swap f
Syntax:
SUBWFB
Syntax:
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Operation:
Status Affected:
N, OV, C, DC, Z
(f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected:
None
Encoding:
0101
Description:
f {,d {,a}}
10da
ffff
ffff
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Q2
Read
register f
Example 1:
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:
Q4
Write to
destination
(0001 1001)
(0000 1101)
0Ch
0Dh
1
0
0
(0000 1100)
(0000 1101)
10da
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
REG, 1, 0
19h
0Dh
1
0011
Example:
SWAPF
Before Instruction
REG
=
After Instruction
REG
=
REG, 1, 0
53h
35h
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
1Bh
1Ah
0
(0001 1011)
(0001 1010)
1Bh
00h
1
1
0
(0001 1011)
SUBWFB
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
C
Z
N
Q3
Process
Data
Encoding:
=
=
=
=
DS41412F-page 410
; result is zero
REG, 1, 0
03h
0Eh
1
(0000 0011)
(0000 1110)
F5h
(1111 0101)
; [2s comp]
(0000 1110)
0Eh
0
0
1
; result is negative
PIC18(L)F2X/4XK22
TBLRD
Table Read
TBLRD
Syntax:
Example1:
TBLRD
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) 1 TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT;
Example2:
0000
0000
0000
TBLRD
=
=
=
55h
00A356h
34h
=
=
34h
00A357h
+* ;
Before Instruction
TABLAT
TBLPTR
MEMORY (01A357h)
MEMORY (01A358h)
After Instruction
TABLAT
TBLPTR
*+ ;
Before Instruction
TABLAT
TBLPTR
MEMORY (00A356h)
After Instruction
TABLAT
TBLPTR
=
=
=
=
AAh
01A357h
12h
34h
=
=
34h
01A358h
10nn
nn=0 *
=1 *+
=2 *=3 +*
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write TABLAT)
DS41412F-page 411
PIC18(L)F2X/4XK22
TBLWT
Table Write
TBLWT
Syntax:
Example1:
TBLWT *+;
Operands:
None
Operation:
if TBLWT*,
(TABLAT) Holding Register;
TBLPTR No Change;
if TBLWT*+,
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR;
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) 1 TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register;
Status Affected:
Before Instruction
TABLAT
=
55h
TBLPTR
=
00A356h
HOLDING REGISTER
(00A356h)
=
FFh
After Instructions (table write completion)
TABLAT
=
55h
TBLPTR
=
00A357h
HOLDING REGISTER
(00A356h)
=
55h
Example 2:
None
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *=3 +*
Description:
Words:
Cycles:
TBLWT +*;
Before Instruction
TABLAT
=
34h
TBLPTR
=
01389Ah
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
FFh
After Instruction (table write completion)
TABLAT
=
34h
TBLPTR
=
01389Bh
HOLDING REGISTER
(01389Ah)
=
FFh
HOLDING REGISTER
(01389Bh)
=
34h
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
No
No
No
operation operation operation
No
No
No
No
operation operation operation operation
(Read
(Write to
TABLAT)
Holding
Register )
DS41412F-page 412
PIC18(L)F2X/4XK22
TSTFSZ
Test f, skip if 0
XORLW
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
Operands:
0 f 255
a [0,1]
Operands:
0 k 255
Operation:
(W) .XOR. k W
Operation:
skip if f = 0
Status Affected:
N, Z
Status Affected:
None
Encoding:
Encoding:
0110
Description:
011a
ffff
ffff
Words:
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
0000
1010
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
Write to W
Example:
XORLW
0AFh
Before Instruction
W
=
After Instruction
W
B5h
1Ah
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
No
operation
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip:
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
Before Instruction
PC
After Instruction
If CNT
PC
If CNT
PC
TSTFSZ
:
:
CNT, 1
Address (HERE)
=
=
00h,
Address (ZERO)
00h,
Address (NZERO)
DS41412F-page 413
PIC18(L)F2X/4XK22
XORWF
Exclusive OR W with f
Syntax:
XORWF
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
Status Affected:
N, Z
Encoding:
0001
f {,d {,a}}
10da
ffff
ffff
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
Example:
XORWF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
DS41412F-page 414
REG, 1, 0
AFh
B5h
1Ah
B5h
PIC18(L)F2X/4XK22
25.2
A summary of the instructions in the extended instruction set is provided in Table 25-3. Detailed descriptions
are provided in Section 25.2.2 Extended Instruction
Set. The opcode field descriptions in Table 25-1 apply
to both the standard and extended PIC18 instruction
sets.
Note:
25.2.1
TABLE 25-3:
Note:
Mnemonic,
Operands
ADDFSR
ADDULNK
CALLW
MOVSF
f, k
k
MOVSS
zs, zd
PUSHL
SUBFSR
SUBULNK
f, k
k
zs, fd
Cycles
MSb
1
2
2
2
LSb
Status
Affected
1000
1000
0000
1011
ffff
1011
xxxx
1010
ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
None
None
None
None
1110
1110
0000
1110
1111
1110
1111
1110
1
2
1110
1110
1001
1001
ffkk
11kk
kkkk
kkkk
None
None
None
None
DS41412F-page 415
PIC18(L)F2X/4XK22
25.2.2
ADDFSR
ADDULNK
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 k 63
f [ 0, 1, 2 ]
Operands:
0 k 63
Operation:
FSR(f) + k FSR(f)
Status Affected:
None
Encoding:
1110
FSR2 + k FSR2,
Operation:
(TOS) PC
Status Affected:
1000
ffkk
kkkk
Description:
Words:
Cycles:
None
Encoding:
1110
Q1
Q2
Q3
Q4
Read
literal k
Process
Data
Write to
FSR
Example:
ADDFSR 2, 23h
Before Instruction
FSR2
=
03FFh
After Instruction
FSR2
=
0422h
kkkk
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal k
Process
Data
Write to
FSR
No
Operation
No
Operation
No
Operation
No
Operation
Example:
Note:
11kk
Q Cycle Activity:
Decode
1000
Description:
ADDULNK 23h
Before Instruction
FSR2
=
PC
=
03FFh
0100h
After Instruction
FSR2
=
PC
=
0422h
(TOS)
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
DS41412F-page 416
PIC18(L)F2X/4XK22
CALLW
MOVSF
Syntax:
CALLW
Syntax:
MOVSF [zs], fd
Operands:
None
Operands:
Operation:
(PC + 2) TOS,
(W) PCL,
(PCLATH) PCH,
(PCLATU) PCU
0 zs 127
0 fd 4095
Operation:
((FSR2) + zs) fd
Status Affected:
None
Status Affected:
None
Encoding:
0000
0000
0001
0100
Description
Words:
Cycles:
Move Indexed to f
Encoding:
1st word (source)
2nd word (destin.)
Q1
Q2
Q3
Q4
Read
WREG
PUSH PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
Before Instruction
PC
=
PCLATH =
PCLATU =
W
=
After Instruction
PC
=
TOS
=
PCLATH =
PCLATU =
W
=
Cycles:
Q Cycle Activity:
Q1
Decode
address (HERE)
10h
00h
06h
zzzzs
ffffd
Words:
CALLW
001006h
address (HERE + 2)
10h
00h
06h
0zzz
ffff
Decode
Example:
1011
ffff
Description:
Q Cycle Activity:
Decode
1110
1111
Q2
Q3
Determine
Determine
source addr source addr
No
operation
No
operation
No dummy
read
Example:
MOVSF
Before Instruction
FSR2
Contents
of 85h
REG2
After Instruction
FSR2
Contents
of 85h
REG2
Q4
Read
source reg
Write
register f
(dest)
[05h], REG2
80h
=
=
33h
11h
80h
=
=
33h
33h
DS41412F-page 417
PIC18(L)F2X/4XK22
MOVSS
PUSHL
Syntax:
Syntax:
PUSHL k
Operands:
Operands:
0k 255
Operation:
Operation:
k (FSR2),
FSR2 1 FSR2
Status Affected:
None
Status Affected:
None
Encoding:
1st word (source)
2nd word (dest.)
1110
1111
Description
1011
xxxx
1zzz
xzzz
zzzzs
zzzzd
Words:
Cycles:
Encoding:
1111
1010
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read k
Process
data
Write to
destination
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
After Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Q Cycle Activity:
Q1
Decode
Decode
Q2
Q3
Determine
Determine
source addr source addr
Determine
dest addr
Example:
Write
to dest reg
Before Instruction
FSR2
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
Contents
of 85h
Contents
of 86h
DS41412F-page 418
Determine
dest addr
Q4
Read
source reg
80h
33h
11h
80h
33h
33h
PIC18(L)F2X/4XK22
SUBFSR
SUBULNK
Syntax:
SUBFSR f, k
Syntax:
SUBULNK k
Operands:
0 k 63
Operands:
0 k 63
f [ 0, 1, 2 ]
Operation:
Operation:
FSR(f) k FSRf
Status Affected:
None
Encoding:
1110
FSR2 k FSR2
(TOS) PC
ffkk
kkkk
Description:
Words:
Cycles:
Encoding:
1110
Q1
Q2
Q3
Q4
Decode
Read
register f
Process
Data
Write to
destination
SUBFSR 2, 23h
1001
11kk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Q Cycle Activity:
Before Instruction
FSR2
=
Q1
Q2
Q3
Q4
03FFh
Decode
After Instruction
FSR2
=
Read
register f
Process
Data
Write to
destination
03DCh
No
Operation
No
Operation
No
Operation
No
Operation
Example:
SUBULNK 23h
Before Instruction
FSR2
=
PC
=
03FFh
0100h
After Instruction
FSR2
=
PC
=
03DCh
(TOS)
DS41412F-page 419
PIC18(L)F2X/4XK22
25.2.3
Note:
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.
25.2.3.1
25.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
DS41412F-page 420
PIC18(L)F2X/4XK22
ADDWF
ADD W to Indexed
(Indexed Literal Offset mode)
BSF
Syntax:
ADDWF
Syntax:
BSF [k], b
Operands:
0 k 95
d [0,1]
Operands:
0 f 95
0b7
Operation:
Operation:
1 ((FSR2) + k)<b>
Status Affected:
N, OV, C, DC, Z
Status Affected:
None
Encoding:
[k] {,d}
0010
Description:
01d0
kkkk
kkkk
Encoding:
1000
bbb0
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Words:
Q1
Q2
Q3
Q4
Cycles:
Decode
Read
register f
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read k
Process
Data
Write to
destination
Example:
ADDWF
[OFST] , 0
Before Instruction
W
OFST
FSR2
Contents
of 0A2Ch
After Instruction
W
Contents
of 0A2Ch
=
=
=
17h
2Ch
0A00h
20h
37h
20h
Example:
BSF
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
After Instruction
Contents
of 0A0Ah
[FLAG_OFST], 7
=
=
0Ah
0A00h
55h
D5h
SETF
Set Indexed
(Indexed Literal Offset mode)
Syntax:
SETF [k]
Operands:
0 k 95
Operation:
FFh ((FSR2) + k)
Status Affected:
None
Encoding:
0110
1000
kkkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read k
Process
Data
Write
register
Example:
SETF
Before Instruction
OFST
FSR2
Contents
of 0A2Ch
After Instruction
Contents
of 0A2Ch
[OFST]
=
=
2Ch
0A00h
00h
FFh
DS41412F-page 421
PIC18(L)F2X/4XK22
25.2.5
DS41412F-page 422
PIC18(L)F2X/4XK22
26.0
DEVELOPMENT SUPPORT
26.1
DS41412F-page 423
PIC18(L)F2X/4XK22
26.2
26.3
26.4
MPASM Assembler
26.5
26.6
DS41412F-page 424
PIC18(L)F2X/4XK22
26.7
26.8
26.9
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
DS41412F-page 425
PIC18(L)F2X/4XK22
26.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
26.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
DS41412F-page 426
PIC18(L)F2X/4XK22
27.0
ELECTRICAL CHARACTERISTICS
DS41412F-page 427
PIC18(L)F2X/4XK22
FIGURE 27-1:
5.5V
Voltage
5.0V
4.0V
3.6V
3.0V
2.7V
2.3V
1.8V
10
16 20
30
40
48
60 64
Frequency (MHz)
Note 1: Maximum Frequency 20 MHz, 1.8V to 2.7V, -40C to +85C
2: Maximum Frequency 64 MHz, 2.7V to 3.6V, -40C to +85C
FIGURE 27-2:
5.5V
Voltage
5.0V
4.0V
3.6V
3.0V
2.7V
2.3V
1.8V
10
16 20
30
40
48
60 64
Frequency (MHz)
Note 1: Maximum Frequency 16 MHz, 1.8V to 2.7V, +85C to +125C
2: Maximum Frequency 48 MHz, 2.7V to 3.6V, +85C to +125C
DS41412F-page 428
PIC18(L)F2X/4XK22
FIGURE 27-3:
5.5V
Voltage
5.0V
4.0V
3.6V
3.0V
2.7V
2.3V
1.8V
10
16 20
30
40
48
60 64
Frequency (MHz)
Note 1: Maximum Frequency 20 MHz, 2.3V to 2.7V, -40C to +85C
2: Maximum Frequency 64 MHz, 2.7V to 5.5V, -40C to +85C
FIGURE 27-4:
5.5V
Voltage
5.0V
4.0V
3.6V
3.0V
2.7V
2.3V
1.8V
10
16 20
30
40
48
60 64
Frequency (MHz)
Note 1: Maximum Frequency 16 MHz, 2.3V to 2.7V, +85C to +125C
2: Maximum Frequency 48 MHz, 2.7V to 5.5V, +85C to +125C
DS41412F-page 429
PIC18(L)F2X/4XK22
27.1
PIC18(L)F2X/4XK22
Param
Symbol
No.
Characteristic
D001
VDD
Supply Voltage
D002
VDR
D003
VPOR
D004
SVDD
D005
VBOR
PIC18LF2X/4XK22
2:
3:
1.8
3.6
2.3
5.5
1.5
0.7
0.05
BORV<1:0> = 11(2)
1.75
1.9 2.05
BORV<1:0> = 10
2.05
2.2 2.35
BORV<1:0> = 01
2.35
2.5 2.65
BORV<1:0> = 00(3)
PIC18F2X/4XK22
Note 1:
Min
Conditions
This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
On PIC18LF2X/4XK22 devices with BOR enabled, operation is supported until a BOR occurs. This is valid
although VDD may be below the minimum rated supply voltage.
With BOR enabled, full-speed operation (FOSC = 64 MHz or 48 MHz) is supported until a BOR occurs. This
is valid although VDD may be below the minimum voltage for this frequency.
DS41412F-page 430
PIC18(L)F2X/4XK22
27.2
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
Typ
Typ
Max
Max
+25C +60C +85C +125C
Device Characteristics
Conditions
Units
VDD
Notes
(1)
Sleep mode
10
1.8V
0.06
10
3.0V
13
25
35
2.3V
13
14
30
40
3.0V
13
14
35
50
5.0V
0.01
0.04
0.01
12
Watchdog Timer
D008
Brown-out
Reset(2)
D010
D011
Secondary Oscillator
Note 1:
2:
3:
0.3
0.3
2.5
2.5
1.8V
0.5
0.5
2.5
2.5
3.0V
0.35
0.35
5.0
5.0
2.3V
0.5
0.5
5.0
5.0
3.0V
0.5
0.5
5.0
5.0
5.0V
8.5
15
16
2.0V
9.5
15
16
3.0V
3.4
3.4
15
16
2.3V
3.8
3.8
15
16
3.0V
5.2
5.2
15
16
5.0V
6.5
6.7
15
15
2.0V
7.5
15
15
3.0V
2.1
2.1
15
15
2.3V
2.4
2.4
15
15
3.0V
3.2
3.2
15
15
5.0V
0.5
10
1.8V
0.6
1.1
10
3.0V
0.5
10
2.3V
0.6
1.1
10
3.0V
0.6
1.1
10
5.0V
32 kHz on SOSC
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
On PIC18LF2X/4XK22 the BOR, HLVD and FVR enable internal band gap reference. With more than one
of these modules enabled, the current consumption will be less than the sum of the specifications. On
PIC18F2X/4XK22, the internal band gap reference is always enabled and its current consumption is
included in the Power-down Base Current (IPD).
A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the
FRC turn off as soon as conversion (if any) is complete.
DS41412F-page 431
PIC18(L)F2X/4XK22
27.2
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
Typ
Typ
Max
Max
+25C +60C +85C +125C
D015
Device Characteristics
Comparators
D016
Comparators
D017
DAC
FVR(2)
D018
D013
A/D
Note 1:
2:
3:
Converter(3)
Conditions
Units
VDD
18
18
1.8V
18
18
3.0V
18
18
2.3V
18
18
3.0V
20
20
5.0V
38
38
95
95
1.8V
40
40
105
105
3.0V
39
39
95
95
2.3V
40
40
105
105
3.0V
40
40
105
105
5.0V
14
14
25
25
2.0V
20
20
35
35
3.0V
15
15
30
30
2.3V
20
20
35
35
3.0V
32
32
60
60
5.0V
15
16
25
25
1.8V
15
16
25
25
3.0V
28
28
45
45
2.3V
31
31
55
55
3.0V
66
66
100
100
5.0V
185
185
370
370
1.8V
210
210
400
400
3.0V
200
200
380
380
2.3V
210
210
400
400
3.0V
250
250
450
450
5.0V
Notes
LP mode
HP mode
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
On PIC18LF2X/4XK22 the BOR, HLVD and FVR enable internal band gap reference. With more than one
of these modules enabled, the current consumption will be less than the sum of the specifications. On
PIC18F2X/4XK22, the internal band gap reference is always enabled and its current consumption is
included in the Power-down Base Current (IPD).
A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the
FRC turn off as soon as conversion (if any) is complete.
DS41412F-page 432
PIC18(L)F2X/4XK22
27.3
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
D020
Device Characteristics
Typ
Max
Units
3.6
23
-40C
3.9
25
+25C
3.9
+60C
3.9
28
+85C
D021
Conditions
4.0
30
125C
8.1
26
-40C
8.4
30
+25C
8.6
+60C
VDD = 1.8V
VDD = 3.0V
8.7
35
+85C
10.7
40
+125C
16
35
-40C
17
35
+25C
18
35
+85C
19
50
+125C
18
50
-40C
20
50
+25C
21
50
+85C
22
60
+125C
19
55
-40C
21
55
+25C
22
55
+85C
23
70
+125C
D025
0.14
0.25
mA
-40C to +125C
VDD = 1.8V
D026
0.17
0.30
mA
-40C to +125C
VDD = 3.0V
D027
0.18
0.25
mA
-40C to +125C
VDD = 2.3V
D028
0.20
0.30
mA
-40C to +125C
VDD = 3.0V
D029
0.25
0.35
mA
-40C to +125C
VDD = 5.0V
D022
D023
D024
Note 1:
2:
FOSC = 31 kHz
(RC_RUN mode,
LFINTOSC
source)
VDD = 2.3V
FOSC = 31 kHz
(RC_RUN mode,
LFINTOSC
source)
VDD = 3.0V
VDD = 5.0V
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to 1.
The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
DS41412F-page 433
PIC18(L)F2X/4XK22
27.3
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
Typ
Max
Units
D030
0.35
0.50
mA
-40C to +125C
VDD = 1.8V
D031
0.45
0.65
mA
-40C to +125C
VDD = 3.0V
D032
0.40
0.60
mA
-40C to +125C
VDD = 2.3V
D033
0.50
0.65
mA
-40C to +125C
VDD = 3.0V
D034
0.55
0.75
mA
-40C to +125C
VDD = 5.0V
D035
1.3
2.0
mA
-40C to +125C
VDD = 1.8V
D036
2.2
3.0
mA
-40C to +125C
VDD = 3.0V
D037
1.7
2.0
mA
-40C to +125C
VDD = 2.3V
D038
2.2
3.0
mA
-40C to +125C
VDD = 3.0V
D039
2.5
3.5
mA
-40C to +125C
VDD = 5.0V
D041
6.2
8.5
mA
-40C to +125C
VDD = 3.0V
FOSC = 64 MHz
(RC_RUN mode,
HFINTOSC + PLL
source)
D043
6.2
8.5
mA
-40C to +125C
VDD = 3.0V
D044
6.8
9.5
mA
-40C to +125C
VDD = 5.0V
FOSC = 64 MHz
(RC_RUN mode,
HFINTOSC + PLL
source)
Note 1:
2:
Device Characteristics
Conditions
FOSC = 1 MHz
(RC_RUN mode,
HFINTOSC
source)
FOSC = 1 MHz
(RC_RUN mode,
HFINTOSC
source)
FOSC = 16 MHz
(RC_RUN mode,
HFINTOSC
source)
FOSC = 16 MHz
(RC_RUN mode,
HFINTOSC
source)
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to 1.
The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
DS41412F-page 434
PIC18(L)F2X/4XK22
27.4
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
D045
Device Characteristics
Typ
0.5
18
-40C
0.6
18
+25C
D046
D047
D048
D049
Max Units
Conditions
0.7
+60C
0.75
20
+85C
2.3
22
+125C
1.1
20
-40C
1.2
20
+25C
1.3
+60C
1.4
22
+85C
3.2
25
+125C
17
30
-40C
13
30
+25C
14
30
+85C
15
45
+125C
19
35
-40C
15
35
+25C
16
35
+85C
17
50
+125C
21
40
-40C
15
40
+25C
16
40
+85C
VDD = 1.8V
VDD = 3.0V
VDD = 2.3V
VDD = 5.0V
18
60
+125C
0.11
0.20
mA
-40C to +125C
VDD = 1.8V
D051
0.12
0.25
mA
-40C to +125C
VDD = 3.0V
D052
0.14
0.21
mA
-40C to +125C
VDD = 2.3V
D053
0.15
0.25
mA
-40C to +125C
VDD = 3.0V
D054
0.20
0.31
mA
-40C to +125C
VDD = 5.0V
2:
FOSC = 31 kHz
(RC_IDLE mode,
LFINTOSC source)
VDD = 3.0V
D050
Note 1:
FOSC = 31 kHz
(RC_IDLE mode,
LFINTOSC source)
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to 1.
The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
DS41412F-page 435
PIC18(L)F2X/4XK22
27.4
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
Device Characteristics
Typ
Max Units
Conditions
D055
0.25
0.40
mA
-40C to +125C
VDD = 1.8V
D056
0.35
0.50
mA
-40C to +125C
VDD = 3.0V
D057
0.30
0.45
mA
-40C to +125C
VDD = 2.3V
D058
0.40
0.50
mA
-40C to +125C
VDD = 3.0V
FOSC = 1 MHz
(RC_IDLE mode,
HFINTOSC source)
FOSC = 1 MHz
(RC_IDLE mode,
HFINTOSC source)
D059
0.45
0.60
mA
-40C to +125C
VDD = 5.0V
D060
0.50
0.7
mA
-40C to +125C
VDD = 1.8V
D061
0.80
1.1
mA
-40C to +125C
VDD = 3.0V
D062
0.65
1.0
mA
-40C to +125C
VDD = 2.3V
D063
0.80
1.1
mA
-40C to +125C
VDD = 3.0V
D064
0.95
1.2
mA
-40C to +125C
VDD = 5.0V
D066
2.5
3.5
mA
-40C to +125C
VDD = 3.0V
FOSC = 64 MHz
(RC_IDLE mode,
HFINTOSC + PLL
source)
D068
2.5
3.5
mA
-40C to +125C
VDD = 3.0V
D069
3.0
4.5
mA
-40C to +125C
VDD = 5.0V
FOSC = 64 MHz
(RC_IDLE mode,
HFINTOSC + PLL
source)
Note 1:
2:
FOSC = 16 MHz
(RC_IDLE mode,
HFINTOSC source)
FOSC = 16 MHz
(RC_IDLE mode,
HFINTOSC source)
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to 1.
The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
DS41412F-page 436
PIC18(L)F2X/4XK22
27.5
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
Device Characteristics
Typ
Max Units
0.11
0.20
mA
-40C to +125C
VDD = 1.8V
D071
0.17
0.25
mA
-40C to +125C
VDD = 3.0V
D072
0.15
0.25
mA
-40C to +125C
VDD = 2.3V
D073
0.20
0.30
mA
-40C to +125C
VDD = 3.0V
D074
0.25
0.35
mA
-40C to +125C
VDD = 5.0V
D075
1.45
2.0
mA
-40C to +125C
VDD = 1.8V
D076
2.60
3.5
mA
-40C to +125C
VDD = 3.0V
D077
1.95
2.5
mA
-40C to +125C
VDD = 2.3V
D078
2.65
3.5
mA
-40C to +125C
VDD = 3.0V
D079
2.95
4.5
mA
-40C to +125C
VDD = 5.0V
D080
7.5
10
mA
-40C to +125C
VDD = 3.0V
FOSC = 64 MHz
(PRI_RUN,
ECH oscillator)
D081
7.5
10
mA
-40C to +125C
VDD = 3.0V
D082
8.5
11.5
mA
-40C to +125C
VDD = 5.0V
FOSC = 64 MHz
(PRI_RUN mode,
ECH source)
D083
1.0
1.5
mA
-40C to +125C
VDD = 1.8V
D084
1.8
3.0
mA
-40C to +125C
VDD = 3.0V
D085
1.4
2.0
mA
-40C to +125C
VDD = 2.3V
D086
1.85
2.5
mA
-40C to +125C
VDD = 3.0V
D087
2.1
3.0
mA
-40C to +125C
VDD = 5.0V
D088
6.35
9.0
mA
-40C to +125C
VDD = 3.0V
FOSC = 16 MHz
64 MHz Internal
(PRI_RUN mode,
ECH + PLL source)
D089
6.35
9.0
mA
-40C to +125C
VDD = 3.0V
D090
7.0
10
mA
-40C to +125C
VDD = 5.0V
FOSC = 16 MHz
64 MHz Internal
(PRI_RUN mode,
ECH + PLL source)
D070
Note 1:
2:
Conditions
FOSC = 1 MHz
(PRI_RUN mode,
ECM source)
FOSC = 1 MHz
(PRI_RUN mode,
ECM source)
FOSC = 20 MHz
(PRI_RUN mode,
ECH source)
FOSC = 20 MHz
(PRI_RUN mode,
ECH source)
FOSC = 4 MHz
16 MHz Internal
(PRI_RUN mode,
ECM + PLL source)
FOSC = 4 MHz
16 MHz Internal
(PRI_RUN mode,
ECM + PLL source)
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to 1.
The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
DS41412F-page 437
PIC18(L)F2X/4XK22
27.6
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
Device Characteristics
Supply Current (IDD)(1),(2)
D100
Typ
Max Units
Conditions
0.030 0.050
mA
-40C to +125C
VDD = 1.8V
D101
0.045 0.065
mA
-40C to +125C
VDD = 3.0V
D102
0.06
0.12
mA
-40C to +125C
VDD = 2.3V
D103
0.08
0.15
mA
-40C to +125C
VDD = 3.0V
D104
0.13
0.20
mA
-40C to +125C
VDD = 5.0V
Fosc = 1 MHz
(PRI_IDLE mode,
ECM source)
Fosc = 1 MHz
(PRI_IDLE mode,
ECM source)
D105
0.45
0.8
mA
-40C to +125C
VDD = 1.8V
D106
0.70
1.0
mA
-40C to +125C
VDD = 3.0V
D107
0.55
0.8
mA
-40C to +125C
VDD = 2.3V
D108
0.75
1.0
mA
-40C to +125C
VDD = 3.0V
D109
0.90
1.2
mA
-40C to +125C
VDD = 5.0V
D110
2.25
3.0
mA
-40C to +125C
VDD = 3.0V
Fosc = 64 MHz
(PRI_IDLE mode,
ECH source)
D111
2.25
3.0
mA
-40C to +125C
VDD = 3.0V
D112
2.60
3.5
mA
-40C to +125C
VDD = 5.0V
Fosc = 64 MHz
(PRI_IDLE mode,
ECH source)
Fosc = 20 MHz
(PRI_IDLE mode,
ECH source)
Fosc = 20 MHz
(PRI_IDLE mode,
ECH source)
D113
0.35
0.6
mA
-40C to +125C
VDD = 1.8V
D114
0.55
0.8
mA
-40C to +125C
VDD = 3.0V
D115
0.45
0.6
mA
-40C to +125C
VDD = 2.3V
D116
0.60
0.9
mA
-40C to +125C
VDD = 3.0V
D117
0.70
1.0
mA
-40C to +125C
VDD = 5.0V
D118
2.2
3.0
mA
-40C to +125C
VDD = 3.0V
Fosc = 16 MHz
64 MHz Internal
(PRI_IDLE mode,
ECH + PLL source)
D119
2.2
3.0
mA
-40C to +125C
VDD = 3.0V
D120
2.5
3.5
mA
-40C to +125C
VDD = 5.0V
Fosc = 16 MHz
64 MHz Internal
(PRI_IDLE mode,
ECH + PLL source)
Note 1:
2:
Fosc = 4 MHz
16 MHz Internal
(PRI_IDLE mode,
ECM + PLL source)
Fosc = 4 MHz
16 MHz Internal
(PRI_IDLE mode,
ECM + PLL source)
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to 1.
The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).
DS41412F-page 438
PIC18(L)F2X/4XK22
.
27.7
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
D130
Device Characteristics
Typ
3.5
23
-40C
3.7
25
+25C
3.8
+60C
4.0
28
+85C
5.1
30
+125C
6.2
26
-40C
6.4
30
+25C
6.5
+60C
6.8
35
+85C
7.8
40
+125C
15
35
-40C
16
35
+25C
17
35
+85C
19
50
+125C
18
50
-40C
19
50
+25C
21
50
+85C
22
60
+125C
19
55
-40C
20
55
+25C
22
55
+85C
23
70
+125C
D131
D132
D133
D134
Note 1:
2:
Max Units
Conditions
VDD = 1.8V
Fosc = 32 kHz
(SEC_RUN mode,
SOSC source)
VDD = 3.0V
VDD = 2.3V
Fosc = 32 kHz
(SEC_RUN mode,
SOSC source)
VDD = 3.0V
VDD = 5.0V
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to 1.
The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
SOSCI / SOSCO = complementary external square wave, from rail-to-rail.
DS41412F-page 439
PIC18(L)F2X/4XK22
27.7
PIC18LF2X/4XK22
PIC18F2X/4XK22
Param
No.
Device Characteristics
D135
D136
D137
D138
D139
Note 1:
2:
Typ
Max Units
Conditions
0.9
18
-40C
1.0
18
+25C
1.1
+60C
1.3
20
+85C
2.3
22
+125C
1.3
20
-40C
1.4
20
+25C
1.5
+60C
1.8
22
+85C
2.9
25
+125C
12
30
-40C
13
30
+25C
14
30
+85C
16
45
+125C
13
35
-40C
14
35
+25C
16
35
+85C
18
50
+125C
14
40
-40C
15
40
+25C
16
40
+85C
18
60
+125C
VDD = 1.8V
Fosc = 32 kHz
(SEC_IDLE mode,
SOSC source)
VDD = 3.0V
VDD = 2.3V
Fosc = 32 kHz
(SEC_IDLE mode,
SOSC source)
VDD = 3.0V
VDD = 5.0V
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
Test condition: All Peripheral Module Control bits in PMD0, PMD1 and PMD2 set to 1.
The test conditions for all IDD measurements in active operation mode are:
All I/O pins set as outputs driven to Vss;
MCLR = VDD;
SOSCI / SOSCO = complementary external square wave, from rail-to-rail.
DS41412F-page 440
PIC18(L)F2X/4XK22
27.8
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Typ
Max
Units
Conditions
0.8
D140
0.15 VDD
0.2 VDD
0.3 VDD
D140A
D141
0.8
D142
0.2 VDD
D142A
0.3 VDD
2.0
0.25 VDD +
0.8
0.8 VDD
0.7 VDD
VIH
D147
D147A
D148
MCLR
D150A
D150B
D155
(1)
Note 1:
2:
3:
4:
0.7 VDD
0.9 VDD
IPU
IPURB
D158
2.1
0.8 VDD
0.1
0.7
4
35
50
100
200
1000
nA
nA
nA
nA
+25C(4)
+60C
+85C
+125C
25
25
85
130
200
300
A
A
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Parameter is characterized but not tested.
DS41412F-page 441
PIC18(L)F2X/4XK22
27.8
DC CHARACTERISTICS
Param
Symbol
No.
VOL
D159
Characteristic
Typ
Max
Units
Conditions
0.6
VDD - 0.7
VOH
D161
Note 1:
2:
3:
4:
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Parameter is characterized but not tested.
DS41412F-page 442
PIC18(L)F2X/4XK22
27.9
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
VPP
Voltage on MCLR/VPPpin
D171
IDDP
10
mA
D172
ED
Byte Endurance
100K
E/W
D173
VDRW
VDDMIN
VDDMAX
D175
TDEW
ms
D176
40
Year
Provided no other
specifications are violated
D177
TREF
1M
10M
E/W
-40C to +85C
-40C to +85C
Using EECON to read/
write
EP
Cell Endurance
D179
VPR
D181
VIW
D182
VIW
D183
TIW
D184
10K
E/W
VDDMIN
VDDMAX
2.2
VDDMAX
PIC18LF2X/4XK22
VDDMIN
VDDMAX
PIC18F2X/4XK22
ms
40
Year
Provided no other
specifications are violated
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions.
2: Refer to Section 7.8 Using the Data EEPROM for a more detailed discussion on data EEPROM
endurance.
3: Required only if single-supply programming is disabled.
4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must
be placed between theMPLAB ICD 2 and target system when programming or debugging with the MPLAB
ICD 2.
5: Self-write and Block Erase.
DS41412F-page 443
PIC18(L)F2X/4XK22
27.10 Analog Characteristics
TABLE 27-1:
COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated)
Param
No.
CM01
Sym
VIOFF
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
40
mV
Comments
High-Power mode
VREF = VDD/2
CM02
VICM
CM04*
TRESP
Response Time(1)
CM05*
*
Note 1:
TMC2OV
60
mV
Low-Power mode
VREF = VDD/2
VSS
VDD
200
400
ns
High-Power mode
600
3500
ns
Low-Power mode
10
TABLE 27-2:
Operating Conditions: 2.0V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
CV01*
CLSB
Step Size(2)
VDD/32
CV02*
CACC
Absolute Accuracy
1/2
LSb
CV03*
CR
5k
CV04*
CST
Settling
Time(1)
10
CV05*
VSRC+
VSRC- +2
VDD
CV06*
VSRC-
VSS
VSRC+ -2
CV07*
VSRC
VDD
*
Note 1:
2:
Comments
VSRC 2.0V
DS41412F-page 444
PIC18(L)F2X/4XK22
TABLE 27-3:
Sym
VROUT
VR02
VROUT
VR04*
TSTABLE
*
Characteristics
VR voltage output to ADC
Settling Time
Min
Typ
Max
Units
Comments
0.973
1.024
1.085
1.946
2.048
2.171
3.891
4.096
4.342
0.942
1.024
1.096
1.884
2.048
2.191
3.768
4.096
4.383
25
100
0 to 125C
TABLE 27-4:
Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ(1)
Max
Units
Comments
CT01
IOUT1
0.55
IRNG<1:0>=01
CT02
IOUT2
5.5
IRNG<1:0>=10
CT03
IOUT3
55
IRNG<1:0>=11
VDD 3.0V
Note 1:
DS41412F-page 445
PIC18(L)F2X/4XK22
FIGURE 27-5:
High/Low-Voltage Detect Characteristics
VDD
(HLVDIF can be
cleared by software)
VHLVD
(HLVDIF set by hardware)
HLVDIF
TABLE 27-5:
Characteristic
HLVDL<3:0>
Min
Typ
Max
Units
0000
1.69
1.84
1.99
0001
1.92
2.07
2.22
0010
2.08
2.28
2.48
0011
2.24
2.44
2.64
0100
2.34
2.54
2.74
0101
2.54
2.74
2.94
0110
2.62
2.87
3.12
0111
2.76
3.01
3.26
1000
3.00
3.30
3.60
1001
3.18
3.48
3.78
1010
3.44
3.69
3.94
1011
3.66
3.91
4.16
1100
3.90
4.15
4.40
1101
4.11
4.41
4.71
1110
4.39
4.74
5.09
1111
V(HLVDIN pin)
Conditions
Production tested at TAMB = 25C. Specifications over temperature limits ensured by characterization.
DS41412F-page 446
PIC18(L)F2X/4XK22
27.11 AC (Timing) Characteristics
27.11.1
3. TCC:ST
2. TppS
4. Ts
T
F
Frequency
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T13CKI
WR
Fall
High
Invalid (High-impedance)
Low
P
R
V
Z
Period
Rise
Valid
High-impedance
output access
Bus free
High
Low
High
Low
Hold
SU
Setup
DAT
STA
STO
Stop condition
ST
DS41412F-page 447
PIC18(L)F2X/4XK22
27.11.2
TIMING CONDITIONS
TABLE 27-6:
AC CHARACTERISTICS
FIGURE 27-6:
Load Condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
DS41412F-page 448
Legend:
RL = 464
CL = 50 pF
PIC18(L)F2X/4XK22
27.11.3
FIGURE 27-7:
Q1
Q2
Q3
Q4
Q1
OSC1
1
CLKOUT
TABLE 27-7:
Param.
No.
1A
Symbol
FOSC
Characteristic
External CLKIN
Frequency(1)
(1)
Oscillator Frequency
TOSC
Oscillator Period
(1)
Min
Max
Units
Conditions
DC
DC
0.5
16
MHz
MHz
DC
64
MHz
DC
MHz
RC Oscillator mode
200
kHz
LP Oscillator mode
0.1
MHz
XT Oscillator mode
MHz
16
MHz
20
MHz
2.0
62.5
s
ns
15.6
ns
250
ns
RC Oscillator mode
200
LP Oscillator mode
0.25
250
10
250
s
ns
XT Oscillator mode
HS Oscillator mode, VDD < 2.7V
62.5
250
ns
50
250
ns
TCY
62.5
ns
TCY = 4/FOSC
TOSL,
TOSH
2.5
LP Oscillator mode
Note 1:
TOSR,
TOSF
30
ns
XT Oscillator mode
10
ns
HS Oscillator mode
50
ns
LP Oscillator mode
20
ns
XT Oscillator mode
7.5
ns
HS Oscillator mode
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All
specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at min. values with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the max. cycle time limit is DC (no
clock) for all devices.
DS41412F-page 449
PIC18(L)F2X/4XK22
TABLE 27-8:
Param.
No.
Sym
F10
F11
F12
FSYS
trc
Characteristic
TABLE 27-9:
Min
Max
Units
Conditions
MHz
MHz
16
MHz
2.7V VDD,
-40C to +85C
12
MHz
2.7V VDD,
+85C to +125C
16
20
MHz
16
16
MHz
16
64
MHz
2.7V VDD,
-40C to +85C
16
48
MHz
2.7V VDD,
+85C to +125C
ms
OA2
OA3
Characteristics
Internal Calibrated
HFINTOSC Frequency(1)
Internal Calibrated
MFINTOSC Frequency(1)
Internal Calibrated
LFINTOSC Frequency(1)
Freq.
Tolerance
Min
Typ
Max
2%
16.0
3%
16.0
5%
16.0
2%
500
kHz
Units
Conditions
3%
500
kHz
5%
500
kHz
-40C TA +125C
20%
31
kHz
-40C TA +125C
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
DS41412F-page 450
PIC18(L)F2X/4XK22
FIGURE 27-8:
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
14
19
12
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
Note:
New Value
Old Value
20, 21
Refer to Figure 27-6 for load conditions.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
10
TosH2ckL
OSC1 to CLKOUT
75
200
ns
(Note 1)
11
TosH2ckH
OSC1 to CLKOUT
75
200
ns
(Note 1)
12
TckR
35
100
ns
(Note 1)
13
TckF
35
100
ns
(Note 1)
14
TckL2ioV
0.5 TCY + 20
ns
(Note 1)
15
TioV2ckH
16
TckH2ioI
17
TosH2ioV
18
TosH2ioI
19
TioV2osH
20
TioR
21
0.25 TCY + 25
ns
(Note 1)
ns
(Note 1)
50
150
ns
100
ns
ns
40
15
72
32
ns
ns
VDD = 1.8V
VDD = 3.3V - 5.0V
TioF
28
15
55
30
ns
ns
VDD = 1.8V
VDD = 3.3V - 5.0V
22
TINP
20
ns
23
TRBP
TCY
ns
Note 1:
These parameters are asynchronous events not related to any internal clock edges.
Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
DS41412F-page 451
PIC18(L)F2X/4XK22
FIGURE 27-9:
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
FIGURE 27-10:
VDD
VIVRST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
DS41412F-page 452
36
PIC18(L)F2X/4XK22
TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol
No.
Characteristic
Min
Typ
Max
Units
4.1
4.7
ms
1:1 prescaler
TOSC = OSC1 period
30
TmcL
31
TWDT
3.5
32
TOST
1024 TOSC
1024 TOSC
33
TPWRT
54.8
64.4
74.1
ms
34
TIOZ
35
TBOR
2001
36
TIVRST
25
35
2001
37
THLVD
38
TCSD
10
39
TIOBST
0.25
ms
Conditions
Note 1: Minimum pulse width that will consistently trigger a reset or interrupt. Shorter pulses may intermittently trigger a response.
FIGURE 27-11:
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
DS41412F-page 453
PIC18(L)F2X/4XK22
TABLE 27-12: TIMER0 AND TIMER1/3/5 EXTERNAL CLOCK REQUIREMENTS
Param.
No.
Symbol
Characteristic
40
Tt0H
No prescaler
41
Tt0L
No prescaler
42
Tt0P
T0CKI Period
Min
Max
Units
0.5 TCY + 20
ns
With prescaler
10
ns
0.5 TCY + 20
ns
With prescaler
With prescaler
45
Tt1H
TxCKI High
Time
10
ns
TCY + 10
ns
Greater of:
20 ns or
(TCY + 40)/N
ns
0.5 TCY + 20
ns
10
ns
No prescaler
Synchronous, no prescaler
Synchronous,
with prescaler
Asynchronous
46
47
Tt1L
ns
ns
10
ns
Synchronous, no prescaler
Asynchronous
30
ns
Tt1P
TxCKI Input
Period
Synchronous
Greater of:
20 ns or
(TCY + 40)/N
ns
Ft1
Tcke2tmrI
Synchronous,
with prescaler
Asynchronous
48
30
0.5 TCY + 5
TxCKI Low
Time
FIGURE 27-12:
60
ns
DC
50
kHz
2 TOSC
7 TOSC
Conditions
N = prescale
value
(1, 2, 4,..., 256)
N = prescale
value (1, 2, 4, 8)
50
51
52
CCPx
(Compare or PWM Mode)
53
Note:
54
DS41412F-page 454
PIC18(L)F2X/4XK22
TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param .
Symbol
No.
50
TccL
51
TccH
Characteristic
Min
Max
Units
0.5 TCY + 20
ns
10
ns
CCPx Input
High Time
0.5 TCY + 20
ns
10
ns
3 TCY + 40
N
ns
No prescaler
With
prescaler
52
TccP
53
TccR
25
ns
54
TccF
25
ns
FIGURE 27-13:
Conditions
N = prescale
value (1, 4 or
16)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
bit 6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
73
Note:
DS41412F-page 455
PIC18(L)F2X/4XK22
TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0 OR 1)
Param.
No.
Symbol
Characteristic
Min
Max Units
70
TssL2scH,
TssL2scL
TCY
ns
73
TdiV2scH,
TdiV2scL
25
ns
74
TscH2diL,
TscL2diL
25
ns
75
TdoR
30
ns
76
TdoF
20
ns
78
TscR
30
ns
79
TscF
20
ns
80
TscH2doV,
TscL2doV
20
ns
81
TCY
ns
FIGURE 27-14:
Conditions
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
MSb
SDO
bit 6 - - - - - -1
LSb
bit 6 - - - -1
LSb In
75, 76
SDI
MSb In
74
Note:
DS41412F-page 456
PIC18(L)F2X/4XK22
FIGURE 27-15:
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
bit 6 - - - - - -1
LSb
77
75, 76
MSb In
SDI
73
Note:
bit 6 - - - -1
LSb In
74
TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0 OR 1)
Param.
No.
Symbol
Characteristic
Min
Max
Units
TCY
ns
70
TssL2scH,
TssL2scL
71
TscH
Continuous
25
ns
72
TscL
Continuous
30
ns
73
TdiV2scH,
TdiV2scL
25
ns
74
TscH2diL,
TscL2diL
25
ns
75
TdoR
30
ns
76
TdoF
20
ns
77
TssH2doZ
10
50
ns
80
TscH2doV,
TscL2doV
60
ns
82
TssL2doV
60
ns
83
TscH2ssH,
TscL2ssH
1.5 TCY + 40
ns
Conditions
DS41412F-page 457
PIC18(L)F2X/4XK22
FIGURE 27-16:
SS
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
bit 6 - - - - - -1
LSb
75, 76
SDI
Note:
MSb In
77
bit 6 - - - -1
LSb In
74
Refer to Figure 27-6 for load conditions.
FIGURE 27-17:
SCL
91
90
93
92
SDA
Start
Condition
Note:
Stop
Condition
DS41412F-page 458
PIC18(L)F2X/4XK22
TABLE 27-16: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
No.
90
TSU:STA
91
THD:STA
Characteristic
Start Condition
Max
Units
Conditions
4700
ns
ns
Setup Time
600
Start Condition
4000
Hold Time
600
Stop Condition
4700
92
TSU:STO
93
Setup Time
Hold Time
FIGURE 27-18:
Min
600
4000
600
ns
ns
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note:
DS41412F-page 459
PIC18(L)F2X/4XK22
TABLE 27-17: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
Symbol
No.
100
THIGH
Characteristic
Clock High Time
Min
Max
Units
Conditions
4.0
0.6
1.5 TCY
4.7
1.3
SSP Module
101
TLOW
1.5 TCY
1000
ns
20 + 0.1 CB
300
ns
300
ns
20 + 0.1 CB
300
ns
CB is specified to be from
10 to 400 pF
4.7
SSP Module
102
TR
103
TF
90
0.6
91
4.0
0.6
THD:DA
ns
106
0.9
250
ns
100
ns
92
4.7
0.6
109
TAA
3500
ns
ns
4.7
1.3
400
pF
107
110
TBUF
D102
CB
Note 1:
2:
CB is specified to be from
10 to 400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement,
TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification), before the SCL line is released.
DS41412F-page 460
PIC18(L)F2X/4XK22
FIGURE 27-19:
SCL
93
91
90
92
SDA
Stop
Condition
Start
Condition
Note:
TSU:STA
Characteristic
ns
ns
2(TOSC)(BRG + 1)
Setup Time
2(TOSC)(BRG + 1)
(1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
93
Units
Hold Time
92
Max
Start Condition
1 MHz mode
91
Min
2(TOSC)(BRG + 1)
1 MHz mode(1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
(1)
2(TOSC)(BRG + 1)
1 MHz mode
Conditions
ns
ns
FIGURE 27-20:
102
100
101
SCL
90
106
91
107
92
SDA
In
109
109
110
SDA
Out
Note:
DS41412F-page 461
PIC18(L)F2X/4XK22
TABLE 27-19: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
Symbol
No.
100
101
THIGH
TLOW
Characteristic
Min
Max
Units
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
(1)
2(TOSC)(BRG + 1)
ms
1000
ns
20 + 0.1 CB
300
ns
300
ns
1 MHz mode
102
TR
(1)
1 MHz mode
103
90
91
TF
TSU:STA
Start Condition
Setup Time
300
ns
20 + 0.1 CB
300
ns
1 MHz mode(1)
100
ns
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
(1)
2(TOSC)(BRG + 1)
ms
ns
0.9
ms
107
TSU:DAT
250
ns
100
ns
92
2(TOSC)(BRG + 1)
ms
2(TOSC)(BRG + 1)
ms
(1)
2(TOSC)(BRG + 1)
ms
3500
ns
1000
ns
(1)
1 MHz mode
ns
4.7
ms
1.3
ms
400
pF
1 MHz mode
106
Data Input
Setup Time
1 MHz mode
109
110
D102
Note 1:
2:
TAA
TBUF
CB
Output Valid
from Clock
Conditions
CB is specified to be
from
10 to 400 pF
CB is specified to be
from
10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the first
clock pulse is generated
(Note 2)
I2C
DS41412F-page 462
PIC18(L)F2X/4XK22
FIGURE 27-21:
TXx/CKx
pin
121
121
RXx/DTx
pin
120
Note:
122
Min
Max
Units
40
ns
121
Tckrf
20
ns
122
Tdtrf
20
ns
120
Symbol
FIGURE 27-22:
Characteristic
Conditions
TXx/CKx
pin
125
RXx/DTx
pin
126
Note:
Symbol
Characteristic
Min
Max
Units
125
TdtV2ckl
10
ns
126
TckL2dtl
15
ns
Conditions
DS41412F-page 463
PIC18(L)F2X/4XK22
TABLE 27-22: A/D CONVERTER CHARACTERISTICS:PIC18(L)F2X/4XK22
Standard Operating Conditions (unless otherwise stated)
Operating temperature
Tested at +25C
PIC18(L)F2X/4XK22
Param.
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
A01
NR
Resolution
10
bits
VREF 3.0V
A03
EIL
0.5
LSb
VREF = 3.0V
A04
EDL
0.5
LSb
VREF 3.0V
A06
EOFF
Offset Error
0.7
LSb
VREF 3.0V
A07
EGN
Gain Error
0.7
LSb
VREF 3.0V
A08
ETOTL
Total Error
0.8
LSb
VREF 3.0V
A20
VREF
VDD
A21
VREFH
VDD/2
VDD + 0.3
A22
VREFL
VSS 0.3V
VDD/2
A25
VAIN
VREFL
VREFH
A30
ZAIN
Recommended Impedance of
Analog Voltage Source
Note:
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
FIGURE 27-23:
BSF ADCON0, GO
(Note 2)
131
Q4
130
132
A/D CLK
A/D DATA
.. .
...
OLD_DATA
ADRES
NEW_DATA
TCY
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
DS41412F-page 464
PIC18(L)F2X/4XK22
TABLE 27-23: A/D CONVERSION REQUIREMENTS PIC18(L)F2X/4XK22
Standard Operating Conditions (unless otherwise stated)
Operating temperature
Tested at +25C
Param.
Symbol
No.
130
TAD
Characteristic
A/D Clock Period
Min
Typ
Max
Units
25
-40C to +85C
+85C to +125C
131
TCNV
Conversion Time
(not including acquisition time) (Note 1)
12
12
TAD
132
TACQ
1.4
135
TSWC
(Note 3)
136
TDIS
Discharge Time
Note 1:
2:
3:
Conditions
VDD = 3V, Rs = 50
TAD
DS41412F-page 465
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 466
PIC18(L)F2X/4XK22
28.0
Note:
DS41412F-page 467
PIC18(L)F2X/4XK22
FIGURE 28-1:
10
Max. 85C
IPD (A)
0.1
Typ. 60C
Typ. 25C
0.01
Limited Accuracy
0.001
1.8
FIGURE 28-2:
2.1
2.4
2.7
VDD (V)
3.3
3.6
40
35
Max. 85C
IPD (A)
30
25
20
15
Typ. 60C
Typ. 25C
10
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 468
PIC18(L)F2X/4XK22
FIGURE 28-3:
3.0
Max.
2.5
IPD (A)
2.0
1.5
1.0
Typ.
0.5
0.0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-4:
Max.
IPD (A)
1
Typical
0
2.3
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
DS41412F-page 469
PIC18(L)F2X/4XK22
FIGURE 28-5:
16
15
Max. 85C
14
13
IPD (A)
12
11
10
9
Typical
8
7
6
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-6:
17
Max. 85C
15
IPD (A)
13
11
Typical
3
2.3
DS41412F-page 470
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
PIC18(L)F2X/4XK22
FIGURE 28-7:
20
18
16
Max.
IPD (A)
14
12
10
8
Typical
6
4
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-8:
16
Max.
14
12
IPD (A)
10
4
Typical
2
0
2.3
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
DS41412F-page 471
PIC18(L)F2X/4XK22
FIGURE 28-9:
4.5
4.0
Max. 85C
3.5
IPD (A)
3.0
2.5
2.0
1.5
Typ. 60C
1.0
Typ. 25C
0.5
0.0
1.8
2.1
2.4
2.7
3.6
3.3
VDD (V)
FIGURE 28-10:
Max. 85C
IPD (A)
1
Typical
0
2.3
DS41412F-page 472
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
PIC18(L)F2X/4XK22
FIGURE 28-11:
20
18
Max.
16
IPD (A)
14
12
10
8
Typical
6
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-12:
40
35
30
IPD (A)
25
20
Max.
15
10
Typical
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 473
PIC18(L)F2X/4XK22
FIGURE 28-13:
120
Max.
100
IPD (A)
80
60
Typ.
40
20
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-14:
120
Max.
100
IPD (A)
80
60
40
Typical
20
0
2.3
DS41412F-page 474
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
PIC18(L)F2X/4XK22
FIGURE 28-15:
50
45
40
Max.
IPD (A)
35
30
25
20
Typical
15
10
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-16:
70
60
Max.
50
IPD (A)
40
30
Typical
20
10
0
2.3
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
DS41412F-page 475
PIC18(L)F2X/4XK22
FIGURE 28-17:
30
28
26
Max.
24
IPD (A)
22
20
18
Typ. 60C
16
Typ. 25C
14
12
10
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-18:
120
Max.
100
IPD (A)
80
Typical
60
40
20
0
2.3
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
DS41412F-page 476
PIC18(L)F2X/4XK22
FIGURE 28-19:
500
450
Max.
400
350
IDD (A)
300
250
Typical
200
150
100
50
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
Note 1: A/D converter differential currents apply only in Run mode. In Sleep or Idle mode, both the
ADC and the FRC turn off as soon as conversion (if any) is complete.
DS41412F-page 477
PIC18(L)F2X/4XK22
FIGURE 28-20:
14
12
125C
IDD (A)
10
25C
8
-40C
85C
1.8
FIGURE 28-21:
2.1
2.4
2.7
VDD (V)
3.3
3.6
55
45
125C
IDD (A)
35
85C
25
25C
-40C
15
1.8
DS41412F-page 478
2.1
2.4
2.7
VDD (V)
3.3
3.6
PIC18(L)F2X/4XK22
FIGURE 28-22:
28
26
24
125C
22
IDD (A)
85C
25C
20
-40C
18
16
14
12
10
2.3
FIGURE 28-23:
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
85
75
125C
65
-40C to +85C
IDD (A)
55
45
35
25
15
5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 479
PIC18(L)F2X/4XK22
FIGURE 28-24:
0.40
0.35
Max
0.30
IDD (mA)
0.25
0.20
Typical
0.15
0.10
0.05
0.00
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-25:
0.4
0.35
Max.
0.3
IDD (mA)
0.25
Typical
0.2
0.15
0.1
0.05
0
2.3
DS41412F-page 480
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
PIC18(L)F2X/4XK22
FIGURE 28-26:
3.50
3.00
2.50
IDD (mA)
16 MHz
2.00
1.50
8 MHz
1.00
4 MHz
2 MHz
1 MHz
0.50
0.00
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-27:
4.5
4.0
3.5
16 MHz
IDD (mA)
3.0
2.5
2.0
8 MHz
1.5
4 MHz
1.0
2 MHz
1 MHz
0.5
0.0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 481
PIC18(L)F2X/4XK22
FIGURE 28-28:
2.5
16 MHz
IDD (mA)
1.5
8 MHz
4 MHz
0.5
2 MHz
1 MHz
0
2.3
FIGURE 28-29:
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
3.5
16 MHz
IDD (mA)
2.5
8 MHz
1.5
4 MHZ
1
2 MHz
1 MHz
0.5
0
2.3
DS41412F-page 482
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
PIC18(L)F2X/4XK22
FIGURE 28-30:
8
7
64 MHz
IDD (mA)
6
5
4
32 MHz
3
16 MHz
2
1
0
1.8
2.1
2.4
2.7
3.6
3.3
VDD (V)
FIGURE 28-31:
12
10
64 MHz
IDD (mA)
6
32 MHz
4
16 MHz
2
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 483
PIC18(L)F2X/4XK22
FIGURE 28-32:
7
64 MHz
6
IDD (mA)
32 MHz
3
16 MHz
2
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
FIGURE 28-33:
12
10
64 MHz
IDD (mA)
6
32 MHz
4
16 MHz
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 484
PIC18(L)F2X/4XK22
FIGURE 28-34:
4
3.5
125C
3
IDD (A)
2.5
2
1.5
85C
25C
-40C
1
0.5
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD(V)
FIGURE 28-35:
35
30
125C
IDD (A)
25
20
15
85C
10
25C
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 485
PIC18(L)F2X/4XK22
FIGURE 28-36:
22
21
-40C
20
19
IDD (A)
18
17
125C
16
15
85C
25C
14
13
12
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
FIGURE 28-37:
70
125C
60
IDD (A)
50
-40C to-40C
+85C
40
30
20
10
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 486
PIC18(L)F2X/4XK22
FIGURE 28-38:
0.3
Max.
0.25
IDD (mA)
0.2
0.15
Typical
0.1
0.05
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-39:
0.35
Max.
0.3
0.25
IDD (mA)
0.2
Typical
0.15
0.1
0.05
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 487
PIC18(L)F2X/4XK22
FIGURE 28-40:
1.2
IDD (mA)
0.8
16 MHz
0.6
8 MHz
4 MHz
0.4
2 MHz
1 MHz
0.2
1.8
2.2
2.4
2.6
2.8
3.2
3.4
3.6
VDD (V)
FIGURE 28-41:
1.6
1.4
1.2
16 MHz
IDD (mA)
0.8
8 MHz
0.6
4 MHz
1 MHz
0.4
0.2
0
1.8
2.2
2.4
2.6
2.8
3.2
3.4
3.6
VDD (V)
DS41412F-page 488
PIC18(L)F2X/4XK22
FIGURE 28-42:
1
16 MHz
0.9
IDD (mA)
0.8
0.7
8 MHz
0.6
4 MHz
0.5
2 MHz
1 MHz
0.4
0.3
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
FIGURE 28-43:
1.4
1.2
16 MHz
IDD (mA)
8 MHz
0.8
4 MHz
0.6
1 MHz
0.4
0.2
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 489
PIC18(L)F2X/4XK22
FIGURE 28-44:
3.5
64 MHz
2.5
IDD (mA)
1.5
32 MHz
1
16 MHz
0.5
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-45:
5
4.5
4
64 MHz
IDD(mA)
3.5
3
2.5
2
32 MHz
1.5
16 MHz
1
0.5
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 490
PIC18(L)F2X/4XK22
FIGURE 28-46:
64 MHz
2.5
IDD (mA)
32 MHz
1.5
16 MHz
0.5
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.5
5.1
VDD (V)
FIGURE 28-47:
5
64 MHz
4.5
4
IDD (mA)
3.5
3
2.5
2
32 MHz
1.5
16 MHz
1
0.5
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 491
PIC18(L)F2X/4XK22
FIGURE 28-48:
3.0
2.5
16 MHz
IDD (mA)
2.0
1.5
10 MHz
1.0
4 MHz
0.5
1 MHz
0.0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-49:
4.0
3.5
3.0
16 MHz
IDD (mA)
2.5
2.0
10 MHz
1.5
1.0
4 MHz
0.5
1 MHz
0.0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 492
PIC18(L)F2X/4XK22
FIGURE 28-50:
2.5
16 MHz
2
1.5
IDD (mA)
10 MHz
4 MHz
0.5
1 MHz
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
FIGURE 28-51:
3.5
3
16 MHz
IDD (mA)
2.5
2
10 MHz
1.5
1
4 MHz
0.5
1 MHz
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 493
PIC18(L)F2X/4XK22
FIGURE 28-52:
12
10
IDD (mA)
64 MHz
6
40 MHz
4
20 MHz
16 MHz
10 MHz
4 MHz
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-53:
16
14
12
64 MHz
IDD (mA)
10
8
40 MHz
6
4
20 MHz
16 MHz
10 MHz
4 MHz
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 494
PIC18(L)F2X/4XK22
FIGURE 28-54:
9
64 MHz
8
7
6
IDD (mA)
40 MHz
5
4
20 MHz
16 MHz
2
10 MHz
1
4 MHz
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
FIGURE 28-55:
14
12
64 MHz
IDD (mA)
10
8
40 MHz
6
20 MHz
4
16 MHz
10 MHz
4 MHz
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 495
PIC18(L)F2X/4XK22
FIGURE 28-56:
10
9
8
7
64 MHz
IDD (mA)
6
5
4
32 MHz
3
2
16 MHz
1
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-57:
14
12
10
IDD (mA)
64 MHz
8
32 MHz
16 MHz
2
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 496
PIC18(L)F2X/4XK22
FIGURE 28-58:
64 MHz
IDD (mA)
4
32 MHz
3
16 MHz
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
FIGURE 28-59:
12
10
64 MHz
IDD (mA)
6
32 MHz
4
16 MHz
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 497
PIC18(L)F2X/4XK22
FIGURE 28-60:
0.9
0.8
0.7
IDD (mA)
0.6
16 MHz
0.5
0.4
10 MHz
0.3
0.2
4 MHz
0.1
1 MHz
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-61:
1.2
0.8
IDD (mA)
16 MHz
0.6
10 MHz
0.4
0.2
4 MHz
1 MHz
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 498
PIC18(L)F2X/4XK22
FIGURE 28-62:
0.8
16 MHz
0.7
0.6
IDD (mA)
0.5
10 MHz
0.4
0.3
4 MHz
0.2
1 MHz
0.1
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
FIGURE 28-63:
1.2
1
16 MHz
IDD (mA)
0.8
10 MHz
0.6
0.4
4 MHz
0.2
1 MHz
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 499
PIC18(L)F2X/4XK22
FIGURE 28-64:
3.5
2.5
IDD (mA)
64 MHz
2
1.5
40 MHz
1
20 MHz
16 MHz
0.5
10 MHz
4 MHz
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-65:
5
4.5
4
IDD (mA)
3.5
64 MHz
3
2.5
2
40 MHz
1.5
1
20 MHz
0.5
16 MHz
10 MHz
4 MHz
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 500
PIC18(L)F2X/4XK22
FIGURE 28-66:
64 MHz
2.5
IDD (mA)
40 MHz
1.5
1
20 MHz
16 MHz
0.5
10 MHz
4 MHz
0
2.3
FIGURE 28-67:
2.7
3.1
3.5
3.9
VDD (V)
4.3
4.7
5.1
5.5
3.5
64 MHz
IDD (mA)
2.5
40 MHz
1.5
20 MHz
1
16 MHz
10 MHz
0.5
4 MHz
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 501
PIC18(L)F2X/4XK22
FIGURE 28-68:
3.5
2.5
IDD (mA)
64 MHz
2
1.5
32 MHz
16 MHz
0.5
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-69:
4.5
4
3.5
64 MHz
IDD (mA)
3
2.5
2
1.5
32 MHz
1
16 MHz
0.5
0
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 502
PIC18(L)F2X/4XK22
FIGURE 28-70:
2.5
64 MHz
IDD (mA)
1.5
32 MHz
1
16 MHz
0.5
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
5.1
5.5
VDD (V)
FIGURE 28-71:
3.5
64 MHz
IDD (mA)
2.5
1.5
32 MHz
16 MHz
0.5
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
VDD (V)
DS41412F-page 503
PIC18(L)F2X/4XK22
FIGURE 28-72:
IDD (A)
125C
85C
60C
25C
-40C
3
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-73:
50
45
40
85C
IDD (A)
35
25C
30
-40C
25
20
15
10
5
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
DS41412F-page 504
PIC18(L)F2X/4XK22
FIGURE 28-74:
22
21
85C
20
25C
IDD (A)
19
-40C
18
17
16
15
14
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
FIGURE 28-75:
85
75
125C
65
-40C to +85C
IDD (A)
55
45
35
25
15
5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 505
PIC18(L)F2X/4XK22
FIGURE 28-76:
2.3
2.1
1.9
85C
1.7
IDD (A)
60C
1.5
25C
-40C
1.3
1.1
0.9
0.7
0.5
1.8
2.1
2.4
2.7
3.3
3.6
VDD (V)
FIGURE 28-77:
25
20
85C
25C
IDD (A)
15
-40C
10
0
1.8
DS41412F-page 506
2.2
2.4
2.6
2.8
VDD (V)
3.2
3.4
3.6
PIC18(L)F2X/4XK22
FIGURE 28-78:
18
17
16
85C
IDD (A)
15
25C
14
-40C
13
12
11
10
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
FIGURE 28-79:
63
125C
58
53
IDD (A)
48
43
-40C to +85C
38
33
28
23
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 507
PIC18(L)F2X/4XK22
FIGURE 28-80:
1.5
1.3
25C
1.1
VIL (V)
-40C
0.9
85C
125C
0.7
Max.
0.5
0.3
0.1
1.8
FIGURE 28-81:
2.2
2.6
3.4
3.8
VDD (V)
4.2
4.6
5.4
2.0
1.8
1.6
-40C
25C
1.4
VIL (V)
1.2
85C
1.0
125C
Max.
0.8
0.6
0.4
0.2
1.8
DS41412F-page 508
2.3
2.8
3.3
3.8
VDD (V)
4.3
4.8
5.3
PIC18(L)F2X/4XK22
FIGURE 28-82:
2.1
1.9
Min.
1.7
VIH (V)
1.5
-40C
1.3
25C
85C
1.1
125C
0.9
0.7
0.5
1.8
2.2
2.6
3.4
3.8
4.2
4.6
5.4
VDD (V)
FIGURE 28-83:
4.5
4.0
3.5
VIH (V)
Min.
3.0
2.5
2.0
25C
-40C
1.5
125C
85C
1.0
1.8
2.2
2.6
3.4
3.8
4.2
4.6
5.4
VDD (V)
DS41412F-page 509
PIC18(L)F2X/4XK22
FIGURE 28-84:
1.00E-05
1.00E-06
Max.
Input Leakage (A)
1.00E-07
1.00E-08
Typical
1.00E-09
1.00E-10
1.00E-11
25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125
Temperature (C)
DS41412F-page 510
PIC18(L)F2X/4XK22
FIGURE 28-85:
1.6
1.4
1.2
Max. 2V
Typ. 2V
Typ. 3V
VOL (V)
Max. 3V
0.8
Max. 5V
Typ. 5V
0.6
0.4
0.2
10
15
20
25
30
IOL (mA)
FIGURE 28-86:
Typ. 5V
VOH(V)
3
Min. 5V
2
Min. 3V
1
Typ. 3V
Min. 2V Typ. 2V
10
15
20
25
IOH (mA)
DS41412F-page 511
PIC18(L)F2X/4XK22
FIGURE 28-87:
60
50
40
6 sigma
30
20
Typical
10
0
0
0.5
1.5
2.5
3.5
4.5
5.5
VREF (V)
FIGURE 28-88:
45
40
35
30
6 sigma
25
20
15
10
Typical
5
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VREF (V)
DS41412F-page 512
PIC18(L)F2X/4XK22
FIGURE 28-89:
35
30
25
Abs. Offset (mV)
6 sigma
20
15
10
Typical
0
0
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VREF (V)
DS41412F-page 513
PIC18(L)F2X/4XK22
FIGURE 28-90:
90
80
70
60
50
6 sigma
40
30
20
Typical
10
0
0
0.5
1.5
2.5
3.5
4.5
5.5
VREF (V)
FIGURE 28-91:
80
70
60
50
40
6 sigma
30
20
10
Typical
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VREF (V)
DS41412F-page 514
PIC18(L)F2X/4XK22
FIGURE 28-92:
60
50
40
6 sigma
30
20
10
Typical
0
0
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VREF (V)
DS41412F-page 515
PIC18(L)F2X/4XK22
FIGURE 28-93:
PIC18(L)F2X/4XK22 TYPICAL DAC ABS. ERROR VDD = 2.5V, 3.0V, & 5.5V
1.7
1.6
1.5
1.4
Minimum VREF
Limit
1.3
Absolute Error (LSb)
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
2.5V
0.3
3.0V
0.2
5.5V
0.1
0.0
0.5
1.5
2.5
3.5
4.5
5.5
VREF (V)
DS41412F-page 516
PIC18(L)F2X/4XK22
FIGURE 28-94:
1.035
1.030
5.5V
FVR x1 (V)
1.025
2.5V
1.020
1.015
1.010
1.005
-40
-20
20
40
60
80
100
120
Temperature (C)
FIGURE 28-95:
1.10
Max.
1.08
FVR x1 (V)
1.06
1.04
40C
25C
1.02
85C
125C
1.00
0.98
Min.
0.96
2.5
3.5
4.5
5.5
VDD (V)
DS41412F-page 517
PIC18(L)F2X/4XK22
FIGURE 28-96:
2.065
2.055
5.5V
FVR x2 (V)
2.045
2.5V
2.035
2.025
2.015
-40
-20
20
40
60
80
100
120
Temperature (C)
FIGURE 28-97:
2.20
Max.
2.15
FVR x2 (V)
2.10
-40C
2.05
25C
85C
125C
2.00
1.95
Min.
1.90
2.5
3.5
4.5
5.5
VDD (V)
DS41412F-page 518
PIC18(L)F2X/4XK22
FIGURE 28-98:
4.13
4.11
FVR x4 (V)
5.5V
4.09
4.5V
4.07
4.05
4.03
-40
-20
20
40
60
80
100
120
Temperature (C)
FIGURE 28-99:
4.40
4.35
Max.
4.30
4.25
FVR x4 (V)
4.20
4.15
40C
4.10
25C
85C
4.05
125C
4.00
3.95
3.90
Min.
3.85
4.5
4.7
4.9
5.1
5.3
5.5
VDD (V)
DS41412F-page 519
PIC18(L)F2X/4XK22
FIGURE 28-100:
16.80
16.64
16.48
Max.
16.32
Freq (MHz)
16.16
16.00
15.84
Typical
Min.
15.68
15.52
15.36
15.20
-40
-30
-20
-10
10
20
30
40
50
60
70
80
90
100
110
120
Temp (C)
DS41412F-page 520
PIC18(L)F2X/4XK22
FIGURE 28-101:
32.5
32.0
25C
31.5
-40C
Frequency (kHz)
85C
31.0
30.5
125C
30.0
29.5
29.0
1.8
2.2
2.4
2.6
2.8
3.2
3.4
3.6
VDD (V)
FIGURE 28-102:
32.5
32.0
Frequency (kHz)
31.5
25C
-40C
31.0
30.5
85C
30.0
29.5
125C
29.0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
DS41412F-page 521
PIC18(L)F2X/4XK22
FIGURE 28-103:
32.5
1.8V
32.0
31.5
Frequency (kHz)
3V
31.0
3.6V
30.5
30.0
29.5
29.0
-40
-20
20
40
60
80
100
120
Temperature (C)
FIGURE 28-104:
32.5
32.0
2.5V
Frequency (kHz)
31.5
3.0V
5.5V
31.0
30.5
30.0
29.5
29.0
-40
-20
20
40
60
80
100
120
Temperature (C)
DS41412F-page 522
PIC18(L)F2X/4XK22
29.0
PACKAGING INFORMATION
29.1
Example
PIC18F25K22
-E/SP e3
0810017
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC18F25K22
-E/SO e3
0810017
Example
PIC18F25K22
-E/SS e3
0810017
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS41412F-page 523
PIC18(L)F2X/4XK22
Package Marking Information (Continued)
28-Lead QFN (6x6 mm)
PIN 1
Example
PIN 1
XXXXXXXX
XXXXXXXX
YYWWNNN
18F25K22
-E/ML e3
0610017
PIN 1
Example
PIN 1
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
DS41412F-page 524
PIC18
F23K22
E/MV e
810017
Example
PIC18F45K22
-E/P e3
0810017
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
PIC18(L)F2X/4XK22
Package Marking Information (Continued)
40-Lead UQFN (5x5x0.5 mm)
PIN 1
Example
PIN 1
PIC18F
45K22
-I/MV e
0810017
3
PIN 1
Example
PIN 1
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
1845K22
-E/ML e3
0810017
Example
18F45K22
-E/PT e3
0810017
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS41412F-page 525
PIC18(L)F2X/4XK22
29.2
Package Details
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DS41412F-page 526
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 527
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 528
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 529
PIC18(L)F2X/4XK22
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DS41412F-page 530
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 531
PIC18(L)F2X/4XK22
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DS41412F-page 532
PIC18(L)F2X/4XK22
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DS41412F-page 533
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 534
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 535
PIC18(L)F2X/4XK22
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DS41412F-page 536
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 537
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 538
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 539
PIC18(L)F2X/4XK22
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PIC18(L)F2X/4XK22
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DS41412F-page 541
PIC18(L)F2X/4XK22
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DS41412F-page 542
PIC18(L)F2X/4XK22
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41412F-page 543
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 544
PIC18(L)F2X/4XK22
APPENDIX A:
REVISION HISTORY
DS41412F-page 545
PIC18(L)F2X/4XK22
APPENDIX B:
DEVICE
DIFFERENCES
TABLE B-1:
DEVICE DIFFERENCES
Features(1)
PIC18F23K22 PIC18F24K22
PIC18LF23K22 PIC18LF24K22
PIC18F25K22
PIC18LF25K22
PIC18F26K22
PIC18LF26K22
PIC18F43K22
PIC18LF43K22
PIC18F44K22
PIC18LF44K22
PIC18F45K22
PIC18LF45K22
PIC18F46K22
PIC18LF46K22
Program Memory
(Bytes)
8192
16384
32768
65536
8192
16384
32768
65536
SRAM (Bytes)
512
768
1536
3896
512
768
1536
3896
EEPROM (Bytes)
256
256
256
1024
256
256
256
1024
Interrupt Sources
26
26
33
33
26
26
33
33
Ports A, B, C,
D, E
Ports A, B, C,
D, E
I/O Ports
Ports A, B, C, Ports A, B, C,
(E)
(E)
Capture/Compare/PWM
Modules (CCP)
ECCP Module
Half Bridge
17 input
channels
17 input
channels
17 input
channels
17 input
channels
28 input
channels
28 input
channels
28 input
channels
28 input
channels
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
40-pin UQFN
44-pin TQFP
44-pin QFN
40-pin PDIP
40-pin UQFN
44-pin TQFP
44-pin QFN
40-pin PDIP
40-pin UQFN
44-pin TQFP
44-pin QFN
40-pin PDIP
40-pin UQFN
44-pin TQFP
44-pin QFN
10-bit Analog-to-Digital
Module
Packages
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin UQFN
DS41412F-page 546
PIC18(L)F2X/4XK22
INDEX
A
A/D
Analog Port Pins, Configuring .................................. 310
Associated Registers ............................................... 310
Conversions ............................................................. 301
Converter Characteristics ........................................ 464
Discharge ................................................................. 302
Selecting and Configuring Acquisition Time ............ 298
Absolute Maximum Ratings ............................................. 427
AC (Timing) Characteristics ............................................. 447
Load Conditions for Device Timing Specifications ... 448
Parameter Symbology ............................................. 447
Temperature and Voltage Specifications ................. 448
Timing Conditions .................................................... 448
AC Characteristics
Internal RC Accuracy ............................................... 450
Access Bank
Mapping with Indexed Literal Offset Mode ................. 94
ACKSTAT ........................................................................ 246
ACKSTAT Status Flag ..................................................... 246
ADC ................................................................................. 297
Acquisition Requirements ........................................ 308
Block Diagram .......................................................... 297
Calculating Acquisition Time .................................... 308
Channel Selection .................................................... 298
Configuration ............................................................ 298
Conversion Clock ..................................................... 299
Conversion Procedure ............................................. 303
Internal Sampling Switch (RSS) IMPEDANCE ............. 308
Interrupts .................................................................. 299
Operation ................................................................. 301
Operation During Sleep ........................................... 302
Port Configuration .................................................... 298
Power Management ................................................. 302
Reference Voltage (VREF) ........................................ 298
Result Formatting ..................................................... 300
Source Impedance ................................................... 308
Special Event Trigger ............................................... 302
Starting an A/D Conversion ..................................... 300
ADCON0 Register ............................................................ 304
ADCON1 Register ............................................................ 305
ADCON2 Register ............................................................ 306
ADDFSR .......................................................................... 416
ADDLW ............................................................................ 379
ADDULNK ........................................................................ 416
ADDWF ............................................................................ 379
ADDWFC ......................................................................... 380
ADRESH Register (ADFM = 0) ........................................ 307
ADRESH Register (ADFM = 1) ........................................ 307
ADRESL Register (ADFM = 0) ......................................... 307
ADRESL Register (ADFM = 1) ......................................... 307
Analog Input Connection Considerations ......................... 315
Analog-to-Digital Converter. See ADC
ANDLW ............................................................................ 380
ANDWF ............................................................................ 381
Assembler
MPASM Assembler .................................................. 424
B
Bank Select Register (BSR) ............................................... 76
BAUDCON Register ......................................................... 279
BC .................................................................................... 381
BCF .................................................................................. 382
C
C Compilers
DS41412F-page 547
PIC18(L)F2X/4XK22
MPLAB C18 ............................................................. 424
CALL ................................................................................ 388
CALLW ............................................................................. 417
Capture Module. See Enhanced Capture/Compare/
PWM(ECCP)
Capture/Compare/PWM ................................................... 179
Capture/Compare/PWM (CCP)
Associated Registers w/ Capture ..................... 181, 182
Associated Registers w/ Compare ................... 184, 185
Associated Registers w/ Enhanced PWM ................ 204
Associated Registers w/ PWM ......................... 189, 203
Associated Registers w/ Standard PWM ................. 189
Capture Mode .......................................................... 180
CCPx Pin Configuration ........................................... 180
Compare Mode ........................................................ 183
CCPx Pin Configuration ................................... 183
Software Interrupt Mode .......................... 180, 183
Special Event Trigger ....................................... 184
Timer1 Mode Resource ........................... 180, 183
Prescaler .................................................................. 181
PWM Mode
Duty Cycle ........................................................ 187
Effects of Reset ................................................ 188
Example PWM Frequencies and
Resolutions, 20 MHZ ............................... 188
Example PWM Frequencies and
Resolutions, 32 MHZ ............................... 188
Example PWM Frequencies and
Resolutions, 8 MHz .................................. 188
Operation in Sleep Mode ................................. 188
Resolution ........................................................ 188
System Clock Frequency Changes .................. 188
PWM Operation ....................................................... 186
PWM Overview ........................................................ 186
PWM Period ............................................................. 187
PWM Setup .............................................................. 186
CCPTMRS0 Register ....................................................... 208
CCPTMRS1 Register ....................................................... 208
CCPxCON (ECCPx) Register .......................................... 205
Clock Accuracy with Asynchronous Operation ................ 276
Clock Sources
External Modes .......................................................... 34
EC ...................................................................... 34
HS ...................................................................... 35
LP ....................................................................... 35
OST .................................................................... 34
RC ...................................................................... 36
XT ...................................................................... 35
Internal Modes ........................................................... 36
Frequency Selection .......................................... 38
INTOSC ............................................................. 36
INTOSCIO .......................................................... 36
LFINTOSC ......................................................... 38
Selecting the 31 kHz Source ...................................... 29
Selection Using OSCCON Register ........................... 29
Clock Switching .................................................................. 41
CLRF ................................................................................ 389
CLRWDT .......................................................................... 389
CM1CON0 Register ......................................................... 317
CM2CON1 Register ......................................................... 318
Code Examples
16 x 16 Signed Multiply Routine .............................. 112
16 x 16 Unsigned Multiply Routine .......................... 112
8 x 8 Signed Multiply Routine .................................. 111
8 x 8 Unsigned Multiply Routine .............................. 111
DS41412F-page 548
PIC18(L)F2X/4XK22
Measuring Time with ................................................ 331
Operation ................................................................. 322
Operation During Idle Mode ..................................... 332
Operation During Sleep Mode ................................. 332
Customer Change Notification Service ............................ 557
Customer Notification Service .......................................... 557
Customer Support ............................................................ 557
CVREF Voltage Reference Specifications ........................ 444
D
Data Addressing Modes ..................................................... 90
Comparing Addressing Modes with the Extended
Instruction Set Enabled ..................................... 93
Direct .......................................................................... 90
Indexed Literal Offset ................................................. 92
Instructions Affected .......................................... 92
Indirect ....................................................................... 90
Inherent and Literal .................................................... 90
Data EEPROM
Code Protection ....................................................... 371
Data EEPROM Memory
Associated Registers ............................................... 109
EEADR and EEADRH Registers ............................. 105
EECON1 and EECON2 Registers ........................... 105
Operation During Code-Protect ............................... 108
Protection Against Spurious Write ........................... 108
Reading .................................................................... 107
Using ........................................................................ 108
Write Verify .............................................................. 107
Writing ...................................................................... 107
Data Memory ..................................................................... 76
Access Bank .............................................................. 82
and the Extended Instruction Set ............................... 92
Bank Select Register (BSR) ....................................... 76
General Purpose Registers ........................................ 82
Map for PIC18F/LF23K22 and PIC18F/LF43K22
Devices .............................................................. 77
Map for PIC18F/LF24K22 and PIC18F/LF44K22
Devices .............................................................. 78
Special Function Registers ........................................ 82
DAW ................................................................................. 392
DC and AC Characteristics .............................................. 467
DC Characteristics
Input/Output ............................................................. 441
Power-Down Current ............................................... 431
Primary Idle Supply Current ..................................... 438
Primary Run Supply Current .................................... 437
RC Idle Supply Current ............................................ 435
RC Run Supply Current ........................................... 433
Secondary Oscillator Supply Current ....................... 439
Supply Voltage ......................................................... 430
DCFSNZ .......................................................................... 393
DECF ............................................................................... 392
DECFSZ ........................................................................... 393
Development Support ...................................................... 423
Device Differences ........................................................... 546
Device Overview
Details on Individual Family Members ....................... 14
Features (table) .......................................................... 15
New Core Features .................................................... 13
Other Special Features .............................................. 14
Device Reset Timers .......................................................... 63
PLL Lock Time-out ..................................................... 63
Power-up Timer (PWRT) ........................................... 63
Time-out Sequence .................................................... 63
DEVID1 Register .............................................................. 364
E
ECCP/CCP. See Enhanced Capture/Compare/PWM
ECCPxAS Register .......................................................... 209
EECON1 Register ...................................................... 97, 106
Effect on Standard PIC Instructions ................................. 420
Effects of Power Managed Modes on Various
Clock Sources ........................................................... 40
Effects of Reset
PWM mode .............................................................. 188
Electrical Characteristics ................................................. 427
Enhanced Capture/Compare/PWM (ECCP) .................... 179
Enhanced PWM Mode ............................................. 190
Auto-Restart .................................................... 198
Auto-shutdown ................................................ 197
Direction Change in Full-Bridge Output Mode . 196
Full-Bridge Application ..................................... 194
Full-Bridge Mode ............................................. 194
Half-Bridge Application .................................... 193
Half-Bridge Application Examples ................... 199
Half-Bridge Mode ............................................. 193
Output Relationships (Active-High and
Active-Low) .............................................. 191
Output Relationships Diagram ......................... 192
Programmable Dead Band Delay .................... 199
Shoot-through Current ..................................... 199
Start-up Considerations ................................... 201
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) ............................. 267
Errata ................................................................................. 12
EUSART .......................................................................... 267
Asynchronous Mode ................................................ 269
12-bit Break Transmit and Receive ................. 287
Associated Registers, Receive ........................ 275
Associated Registers, Transmit ....................... 271
Auto-Wake-up on Break .................................. 285
Baud Rate Generator (BRG) ........................... 280
Clock Accuracy ................................................ 276
Receiver .......................................................... 272
Setting up 9-bit Mode with Address Detect ..... 274
Transmitter ...................................................... 269
Baud Rate Generator (BRG)
Associated Registers ....................................... 281
Auto Baud Rate Detect .................................... 284
Baud Rate Error, Calculating ........................... 280
Baud Rates, Asynchronous Modes ................. 281
Formulas .......................................................... 280
High Baud Rate Select (BRGH Bit) ................. 280
Clock polarity
Synchronous Mode .......................................... 288
Data polarity
Asynchronous Receive .................................... 272
Asynchronous Transmit ................................... 269
Synchronous Mode .......................................... 288
Interrupts
Asychronous Receive ...................................... 273
Asynchronous Receive .................................... 273
Asynchronous Transmit ................................... 269
Synchronous Master Mode .............................. 288, 293
Associated Registers, Receive ........................ 292
Associated Registers, Transmit ............... 289, 294
DS41412F-page 549
PIC18(L)F2X/4XK22
Reception ......................................................... 291
Transmission .................................................... 288
Synchronous Slave Mode
Associated Registers, Receive ........................ 295
Reception ......................................................... 295
Transmission .................................................... 293
Extended Instruction Set
ADDFSR .................................................................. 416
ADDULNK ................................................................ 416
and Using MPLAB Tools .......................................... 422
CALLW ..................................................................... 417
Considerations for Use ............................................ 420
MOVSF .................................................................... 417
MOVSS .................................................................... 418
PUSHL ..................................................................... 418
SUBFSR .................................................................. 419
SUBULNK ................................................................ 419
Syntax ...................................................................... 415
F
Fail-Safe Clock Monitor .............................................. 44, 355
Fail-Safe Condition Clearing ...................................... 44
Fail-Safe Detection .................................................... 44
Fail-Safe Operation .................................................... 44
Reset or Wake-up from Sleep .................................... 44
Fast Register Stack ............................................................ 72
Fixed Voltage Reference (FVR)
Associated Registers ............................................... 344
Flash Program Memory ...................................................... 95
Associated Registers ............................................... 103
Control Registers ....................................................... 96
EECON1 and EECON2 ..................................... 96
TABLAT (Table Latch) Register ......................... 98
TBLPTR (Table Pointer) Register ...................... 98
Erase Sequence ...................................................... 100
Erasing ..................................................................... 100
Operation During Code-Protect ............................... 103
Reading ...................................................................... 99
Table Pointer
Boundaries Based on Operation ........................ 98
Table Pointer Boundaries .......................................... 98
Table Reads and Table Writes .................................. 95
Write Sequence ....................................................... 101
Writing To ................................................................. 101
Protection Against Spurious Writes ................. 103
Unexpected Termination .................................. 103
Write Verify ...................................................... 103
G
GOTO ............................................................................... 394
H
Hardware Multiplier .......................................................... 111
Introduction .............................................................. 111
Operation ................................................................. 111
Performance Comparison ........................................ 111
High/Low-Voltage Detect ................................................. 349
Applications .............................................................. 352
Associated Registers ............................................... 353
Characteristics ......................................................... 446
Current Consumption ............................................... 351
Effects of a Reset ..................................................... 353
Operation ................................................................. 350
During Sleep .................................................... 353
Setup ........................................................................ 351
Start-up Time ........................................................... 351
DS41412F-page 550
I
I2C Mode (MSSPx)
Acknowledge Sequence Timing .............................. 250
Bus Collision
During a Repeated Start Condition .................. 255
During a Stop Condition .................................. 256
Effects of a Reset .................................................... 251
I2C Clock Rate w/BRG ............................................. 258
Master Mode
Operation ......................................................... 242
Reception ........................................................ 248
Start Condition Timing ............................. 244, 245
Transmission ................................................... 246
Multi-Master Communication, Bus Collision and
Arbitration ........................................................ 252
Multi-Master Mode ................................................... 251
Read/Write Bit Information (R/W Bit) ....................... 227
Slave Mode
Transmission ................................................... 232
Sleep Operation ....................................................... 251
Stop Condition Timing ............................................. 250
ID Locations ............................................................. 355, 371
INCF ................................................................................ 394
INCFSZ ............................................................................ 395
In-Circuit Debugger .......................................................... 371
In-Circuit Serial Programming (ICSP) ...................... 355, 371
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 420
Indexed Literal Offset Mode ............................................. 420
Indirect Addressing ............................................................ 91
INFSNZ ............................................................................ 395
Instruction Cycle ................................................................ 74
Clocking Scheme ....................................................... 74
Instruction Flow/Pipelining ................................................. 74
Instruction Set .................................................................. 373
ADDLW .................................................................... 379
ADDWF .................................................................... 379
ADDWF (Indexed Literal Offset Mode) .................... 421
ADDWFC ................................................................. 380
ANDLW .................................................................... 380
ANDWF .................................................................... 381
BC ............................................................................ 381
BCF ......................................................................... 382
BN ............................................................................ 382
BNC ......................................................................... 383
BNN ......................................................................... 383
BNOV ...................................................................... 384
BNZ ......................................................................... 384
BOV ......................................................................... 387
BRA ......................................................................... 385
BSF .......................................................................... 385
BSF (Indexed Literal Offset Mode) .......................... 421
BTFSC ..................................................................... 386
BTFSS ..................................................................... 386
BTG ......................................................................... 387
BZ ............................................................................ 388
CALL ........................................................................ 388
CLRF ....................................................................... 389
CLRWDT ................................................................. 389
COMF ...................................................................... 390
CPFSEQ .................................................................. 390
CPFSGT .................................................................. 391
CPFSLT ................................................................... 391
PIC18(L)F2X/4XK22
DAW ......................................................................... 392
DCFSNZ .................................................................. 393
DECF ....................................................................... 392
DECFSZ ................................................................... 393
Extended Instruction Set .......................................... 415
General Format ........................................................ 375
GOTO ...................................................................... 394
INCF ......................................................................... 394
INCFSZ .................................................................... 395
INFSNZ .................................................................... 395
IORLW ..................................................................... 396
IORWF ..................................................................... 396
LFSR ........................................................................ 397
MOVF ....................................................................... 397
MOVFF .................................................................... 398
MOVLB .................................................................... 398
MOVLW ................................................................... 399
MOVWF ................................................................... 399
MULLW .................................................................... 400
MULWF .................................................................... 400
NEGF ....................................................................... 401
NOP ......................................................................... 401
Opcode Field Descriptions ....................................... 374
POP ......................................................................... 402
PUSH ....................................................................... 402
RCALL ..................................................................... 403
RESET ..................................................................... 403
RETFIE .................................................................... 404
RETLW .................................................................... 404
RETURN .................................................................. 405
RLCF ........................................................................ 405
RLNCF ..................................................................... 406
RRCF ....................................................................... 406
RRNCF .................................................................... 407
SETF ........................................................................ 407
SETF (Indexed Literal Offset Mode) ........................ 421
SLEEP ..................................................................... 408
SUBFWB .................................................................. 408
SUBLW .................................................................... 409
SUBWF .................................................................... 409
SUBWFB .................................................................. 410
SWAPF .................................................................... 410
TBLRD ..................................................................... 411
TBLWT ..................................................................... 412
TSTFSZ ................................................................... 413
XORLW .................................................................... 413
XORWF .................................................................... 414
INTCON Register ............................................................. 116
INTCON Registers ........................................................... 115
INTCON2 Register ........................................................... 117
INTCON3 Register ........................................................... 118
Internal Oscillator Block
HFINTOSC Frequency Drift ....................................... 38
PLL in HFINTOSC Modes .......................................... 39
Internal RC Oscillator
Use with WDT .......................................................... 366
Internal Sampling Switch (RSS) IMPEDANCE ..................... 308
Internet Address ............................................................... 557
Interrupt Sources ............................................................. 355
ADC ......................................................................... 299
Interrupt-on-Change (RB7:RB4) .............................. 140
INTn Pin ................................................................... 132
PORTB, Interrupt-on-Change .................................. 132
TMR0 ....................................................................... 132
TMR0 Overflow ........................................................ 161
Interrupts
L
LFSR ............................................................................... 397
Low-Voltage ICSP Programming. See Single-Supply
ICSP Programming
M
Map .............................................................................. 79, 80
Master Clear (MCLR) ......................................................... 61
Master Synchronous Serial Port. See MSSPx
Memory Organization
Data Memory ............................................................. 76
Program Memory ....................................................... 69
Microchip Internet Web Site ............................................. 557
MOVF .............................................................................. 397
MOVFF ............................................................................ 398
MOVLB ............................................................................ 398
MOVLW ........................................................................... 399
MOVSF ............................................................................ 417
MOVSS ............................................................................ 418
MOVWF ........................................................................... 399
MPLAB ASM30 Assembler, Linker, Librarian .................. 424
MPLAB Integrated Development Environment Software . 423
MPLAB PM3 Device Programmer ................................... 426
MPLAB REAL ICE In-Circuit Emulator System ............... 425
MPLINK Object Linker/MPLIB Object Librarian ............... 424
MSSPx ............................................................................. 211
SPI Mode ................................................................. 214
SSPxBUF Register .................................................. 217
SSPxSR Register .................................................... 217
MULLW ............................................................................ 400
MULWF ............................................................................ 400
N
NEGF ............................................................................... 401
NOP ................................................................................. 401
O
OSCCON Register ....................................................... 32, 33
Oscillator Configuration
EC .............................................................................. 27
ECIO .......................................................................... 27
HS .............................................................................. 27
HSPLL ....................................................................... 27
LP .............................................................................. 27
RC ............................................................................. 27
XT .............................................................................. 27
Oscillator Selection .......................................................... 355
Oscillator Start-up Timer (OST) ................................... 40, 63
Oscillator Switching
Fail-Safe Clock Monitor ............................................. 44
Two-Speed Clock Start-up ........................................ 42
OSCTUNE Register ........................................................... 37
P
P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/
PWM (ECCP) .......................................................... 190
DS41412F-page 551
PIC18(L)F2X/4XK22
Packaging Information ..................................................... 523
Marking .................................................................... 523
PIE Registers ................................................................... 115
PIE1 Register ................................................................... 124
PIE2 Register ................................................................... 125
PIE3 Register3 ................................................................. 126
PIE4 Register ................................................................... 127
PIE5 Register ................................................................... 127
PIR1 Register ................................................................... 119
PIR2 Register ................................................................... 120
PLL Frequency Multiplier ................................................... 39
POP .................................................................................. 402
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 137
PORTA Register ...................................................... 135
TRISA Register ........................................................ 135
PORTB
Associated Registers ............................................... 143
PORTB Register ...................................................... 140
PORTC
Associated Registers ............................................... 147
PORTC Register ...................................................... 144
PORTD
Associated Registers ............................................... 151
PORTD Register ...................................................... 148
TRISD Register ........................................................ 148
PORTE
Associated Registers ............................................... 152
PORTE Register ...................................................... 151
Power Managed Modes ..................................................... 47
and A/D Operation ................................................... 302
Effects on Clock Sources ........................................... 40
Entering ...................................................................... 47
Exiting Idle and Sleep Modes .................................... 54
by Interrupt ......................................................... 54
by Reset ............................................................. 54
by WDT Time-out ............................................... 54
Without a Start-up Delay .................................... 54
Idle Modes ................................................................. 51
PRI_IDLE ........................................................... 52
RC_IDLE ............................................................ 53
SEC_IDLE .......................................................... 52
Multiple Sleep Functions ............................................ 48
Run Modes ................................................................. 48
PRI_RUN ........................................................... 48
SEC_RUN .......................................................... 48
Selecting .................................................................... 47
Sleep Mode ................................................................ 51
Summary (table) ........................................................ 47
Power-on Reset (POR) ...................................................... 61
Power-up Timer (PWRT) ........................................... 63
Time-out Sequence .................................................... 63
Power-up Delays ................................................................ 40
Power-up Timer (PWRT) .................................................... 40
Prescaler, Timer0 ............................................................. 161
PRI_IDLE Mode ................................................................. 52
PRI_RUN Mode ................................................................. 48
Program Counter ................................................................ 70
PCL, PCH and PCU Registers ................................... 70
PCLATH and PCLATU Registers .............................. 70
Program Memory
and Extended Instruction Set ..................................... 94
Code Protection ....................................................... 369
Instructions ................................................................. 75
DS41412F-page 552
Two-Word .......................................................... 75
Interrupt Vector .......................................................... 69
Look-up Tables .......................................................... 73
Map and Stack (diagram) .......................................... 70
Reset Vector .............................................................. 69
Program Verification and Code Protection ...................... 368
Associated Registers ............................................... 368
PSTRxCON Register ....................................................... 210
PUSH ............................................................................... 402
PUSH and POP Instructions .............................................. 72
PUSHL ............................................................................. 418
PWM (ECCP Module)
PWM Steering .......................................................... 200
Steering Synchronization ......................................... 200
PWM Mode. See Enhanced Capture/Compare/PWM ..... 190
PWM Steering .................................................................. 200
PWMxCON Register ........................................................ 210
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 53
RC_RUN ............................................................................ 48
RCALL ............................................................................. 403
RCON Register .................................................................. 60
Bit Status During Initialization .................................... 67
RCREG ............................................................................ 274
RCSTA Register .............................................................. 278
Reader Response ............................................................ 558
Register
RCREG Register ..................................................... 284
Register File ....................................................................... 82
Registers
ADCON0 (ADC Control 0) ....................................... 304
ADCON1 (ADC Control 1) ....................................... 305
ADCON2 (ADC Control 2) ....................................... 306
ADRESH (ADC Result High) with ADFM = 0) ......... 307
ADRESH (ADC Result High) with ADFM = 1) ......... 307
ADRESL (ADC Result Low) with ADFM = 0) ........... 307
ADRESL (ADC Result Low) with ADFM = 1) ........... 307
BAUDCON (Baud Rate Control) .............................. 279
BAUDCON (EUSART Baud Rate Control) .............. 279
CCPTMRS0 (PWM Timer Selection Control 0) ....... 208
CCPTMRS1 (PWM Timer Selection Control 1) ....... 208
CCPxCON (ECCPx Control) .................................... 205
CM1CON0 (C1 Control) ........................................... 317
CM2CON1 (C2 Control) ........................................... 318
CONFIG1H (Configuration 1 High) .......................... 357
CONFIG2H (Configuration 2 High) .......................... 359
CONFIG2L (Configuration 2 Low) ........................... 358
CONFIG3H (Configuration 3 High) .......................... 360
CONFIG4L (Configuration 4 Low) ........................... 361
CONFIG5H (Configuration 5 High) .......................... 362
CONFIG5L (Configuration 5 Low) ........................... 361
CONFIG6H (Configuration 6 High) .......................... 363
CONFIG6L (Configuration 6 Low) ........................... 362
CONFIG7H (Configuration 7 High) .......................... 364
CONFIG7L (Configuration 7 Low) ........................... 363
CTMUCONH (CTMU Control High) ......................... 333
CTMUCONL (CTMU Control Low) .......................... 334
CTMUICON (CTMU Current Control) ...................... 335
DEVID1 (Device ID 1) .............................................. 364
DEVID2 (Device ID 2) .............................................. 364
ECCPxAS (CCPx Auto-Shutdown Control) ............. 209
EECON1 (Data EEPROM Control 1) ................. 97, 106
HLVDCON (High/Low-Voltage Detect Control) ....... 349
INTCON (Interrupt Control) ...................................... 116
PIC18(L)F2X/4XK22
INTCON2 (Interrupt Control 2) ................................. 117
INTCON3 (Interrupt Control 3) ................................. 118
IPR1 (Peripheral Interrupt Priority 1) ........................ 128
IPR2 (Peripheral Interrupt Priority 2) ........................ 129
IPR3 (Peripheral Interrupt Priority) ........................... 130
IPR4 (Peripheral Interrupt Priority) ........................... 131
IPR5 (Peripheral Interrupt Priority) ........................... 131
OSCCON (Oscillator Control) .............................. 32, 33
OSCTUNE (Oscillator Tuning) ................................... 37
PIE1 (Peripheral Interrupt Enable 1) ........................ 124
PIE2 (Peripheral Interrupt Enable 2) ........................ 125
PIE3 (Peripheral Interrupt Enable] ........................... 126
PIE4 (Peripheral Interrupt Enable) ........................... 127
PIE5 (Peripheral Interrupt Enable) ........................... 127
PIR1 (Peripheral Interrupt Request 1) ..................... 119
PIR2 (Peripheral Interrupt Request 2) ..................... 120
PSTRxCON (PWM Steering Control) ...................... 210
PWMxCON (Enhanced PWM Control) .................... 210
RCON (Reset Control) ....................................... 60, 131
RCSTA (Receive Status and Control) ...................... 278
SLRCON (PORT Slew Rate Control) ....................... 158
SRCON0 (SR Latch Control 0) ................................ 340
SRCON1 (SR Latch Control 1) ................................ 341
SSPxADD (MSSPx Address and Baud Rate,
I2C Mode) ........................................................ 265
SSPxCON1 (MSSPx Control 1) ............................... 260
SSPxCON2 (SSPx Control 2) .................................. 262
SSPxMSK (SSPx Mask) .......................................... 264
SSPxSTAT (SSPx Status) ....................................... 259
STATUS ..................................................................... 89
STKPTR (Stack Pointer) ............................................ 72
T0CON (Timer0 Control) .......................................... 159
TxCON ..................................................................... 177
TxCON (Timer1/3/5 Control) .................................... 172
TxGCON (Timer1/3/5 Gate Control) ........................ 173
TXSTA (Transmit Status and Control) ..................... 277
VREFCON0 ............................................................. 344
VREFCON1 ............................................................. 347
VREFCON2 ............................................................. 348
WDTCON (Watchdog Timer Control) ...................... 367
RESET ............................................................................. 403
Reset State of Registers .................................................... 67
Resets .............................................................................. 355
Brown-out Reset (BOR) ........................................... 355
Oscillator Start-up Timer (OST) ............................... 355
Power-on Reset (POR) ............................................ 355
Power-up Timer (PWRT) ......................................... 355
RETFIE ............................................................................ 404
RETLW ............................................................................ 404
RETURN .......................................................................... 405
Return Address Stack ........................................................ 70
Return Stack Pointer (STKPTR) ........................................ 71
Revision History ............................................................... 545
RLCF ................................................................................ 405
RLNCF ............................................................................. 406
RRCF ............................................................................... 406
RRNCF ............................................................................ 407
S
SEC_IDLE Mode ................................................................ 52
SEC_RUN Mode ................................................................ 48
SETF ................................................................................ 407
Shoot-through Current ..................................................... 199
Single-Supply ICSP Programming.
SLEEP ............................................................................. 408
Sleep
T
T0CON Register .............................................................. 159
Table Pointer Operations (table) ........................................ 98
Table Reads/Table Writes ................................................. 73
TBLRD ............................................................................. 411
TBLWT ............................................................................ 412
Time-out in Various Situations (table) ................................ 64
Timer0 ............................................................................. 159
Associated Registers ............................................... 161
Operation ................................................................. 160
Overflow Interrupt .................................................... 161
Prescaler ................................................................. 161
Prescaler Assignment (PSA Bit) .............................. 161
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 161
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 160
Source Edge Select (T0SE Bit) ............................... 160
Source Select (T0CS Bit) ........................................ 160
Switching Prescaler Assignment ............................. 161
Timer1/3/5 ....................................................................... 163
Associated registers ................................................ 174
Asynchronous Counter Mode .................................. 165
Reading and Writing ........................................ 165
Clock Source Selection ........................................... 164
Interrupt ................................................................... 168
Operation ................................................................. 164
Operation During Sleep ........................................... 168
Oscillator .................................................................. 165
DS41412F-page 553
PIC18(L)F2X/4XK22
Prescaler .................................................................. 165
Timer1/3/5 Gate
Selecting Source .............................................. 166
TMRxH Register ...................................................... 163
TMRxL Register ....................................................... 163
Timer2/4/6 ........................................................................ 175
Associated registers ................................................. 178
Timers
Timer1/3/5
TxCON ............................................................. 172
TxGCON .......................................................... 173
Timer2/4/6
TxCON ............................................................. 177
Timing Diagrams
A/D Conversion ........................................................ 464
Acknowledge Sequence .......................................... 250
Asynchronous Reception ......................................... 275
Asynchronous Transmission .................................... 270
Asynchronous Transmission (Back to Back) ........... 271
Auto Wake-up Bit (WUE) During Normal Operation 286
Auto Wake-up Bit (WUE) During Sleep ................... 286
Automatic Baud Rate Calculator .............................. 285
Baud Rate Generator with Clock Arbitration ............ 243
BRG Reset Due to SDA Arbitration During Start
Condition .......................................................... 254
Brown-out Reset (BOR) ........................................... 452
Bus Collision During a Repeated Start Condition
(Case 1) ........................................................... 255
Bus Collision During a Repeated Start Condition
(Case 2) ........................................................... 255
Bus Collision During a Start Condition (SCL = 0) .... 254
Bus Collision During a Stop Condition (Case 1) ...... 256
Bus Collision During a Stop Condition (Case 2) ...... 256
Bus Collision During Start Condition (SDA only) ..... 253
Bus Collision for Transmit and Acknowledge ........... 252
Capture/Compare/PWM (CCP) ................................ 454
CLKO and I/O .......................................................... 451
Clock Synchronization ............................................. 240
Clock/Instruction Cycle .............................................. 74
Comparator Output .................................................. 311
EUSART Synchronous Receive (Master/Slave) ...... 463
EUSART Synchronous Transmission
(Master/Slave) .................................................. 463
Example SPI Master Mode (CKE = 0) ..................... 455
Example SPI Master Mode (CKE = 1) ..................... 456
Example SPI Master Mode Timing .......................... 455
Example SPI Slave Mode (CKE = 0) ....................... 457
Example SPI Slave Mode (CKE = 1) ....................... 458
External Clock (All Modes except PLL) .................... 449
Fail-Safe Clock Monitor (FSCM) ................................ 45
First Start Bit Timing ................................................ 244
Full-Bridge PWM Output .......................................... 195
Half-Bridge PWM Output ................................. 193, 199
High/Low-Voltage Detect Characteristics ................ 446
High-Voltage Detect Operation (VDIRMAG = 1) ...... 352
I2C Bus Data ............................................................ 459
I2C Bus Start/Stop Bits ............................................. 458
I2C Master Mode (7 or 10-Bit Transmission) ........... 247
I2C Master Mode (7-Bit Reception) .......................... 249
I2C Stop Condition Receive or Transmit Mode ........ 251
Internal Oscillator Switch Timing ................................ 43
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 351
Master SSP I2C Bus Data ........................................ 461
Master SSP I2C Bus Start/Stop Bits ........................ 461
PWM Auto-shutdown ............................................... 198
DS41412F-page 554
PIC18(L)F2X/4XK22
BRGH Bit ................................................................. 280
V
Voltage Reference (VR)
Specifications ........................................................... 445
VREF. SEE ADC Reference Voltage
VREFCON0 Register ....................................................... 344
VREFCON1 (Digital-to-Analog Converter Control 0)
Register .................................................................... 347
VREFCON2 (Digital-to-Analog Converter Control 1)
Register .................................................................... 348
W
Wake-up on Break ........................................................... 285
Watchdog Timer (WDT) ........................................... 355, 366
Associated Registers ............................................... 367
Control Register ....................................................... 367
Programming Considerations .................................. 366
WCOL ...................................................... 243, 246, 248, 250
WCOL Status Flag ................................... 243, 246, 248, 250
WDTCON Register .......................................................... 367
WWW Address ................................................................. 557
WWW, On-Line Support .................................................... 12
X
XORLW ............................................................................ 413
XORWF ............................................................................ 414
DS41412F-page 555
PIC18(L)F2X/4XK22
NOTES:
DS41412F-page 556
PIC18(L)F2X/4XK22
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included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
DS41412F-page 557
PIC18(L)F2X/4XK22
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
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Questions:
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DS41412F-page 558
PIC18(L)F2X/4XK22
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
[X](2)
/XX
XXX
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
c)
PIC18F46K22, PIC18LF46K22
PIC18F45K22, PIC18LF45K22
PIC18F44K22, PIC18LF44K22
PIC18F43K22, PIC18LF43K22
PIC18F26K22, PIC18LF26K22
PIC18F25K22, PIC18LF25K22
PIC18F24K22, PIC18LF24K22
PIC18F23K22, PIC18LF23K22
d)
Temperature
Range:
E
I
Package:
ML
MV
P
PT
SO
SP
SS
Pattern:
Note 1:
= -40C to +125C
= -40C to +85C
(Extended)
(Industrial)
2:
=
=
=
=
=
=
=
QFN
UQFN
PDIP
TQFP (Thin Quad Flatpack)
SOIC
Skinny Plastic DIP
SSOP
DS41412F-page 559
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DS41412F-page 560
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11/29/11