Introduction to

FPGA Design
Getting Started with Xilinx FPGAs
Version 2.1i

1999 Xilinx, Inc.

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Intro to FPGA Design 6-1

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express written permission of the Director of XilinxCustomer Education.

Outline

Hierarchical Design
Synchronous Design for XilinxFPGAs
Summary

1999 Xilinx, Inc.

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Intro to FPGA Design 6-9

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express written permission of the Director of XilinxCustomer Education.

Synchronous Design

W hy Synchronous Design?
Xilinx FPGA Design Tips

1999 Xilinx, Inc.

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Intro to FPGA Design 6-10

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express written permission of the Director of XilinxCustomer Education.

W hy Synchronous Design?

Synchronous circuits are m ore reliable

Events are triggered by clock edges which occur at welldefined intervals
Outputs from one logic stage have a full clock cycle to
propagate to the next stage
Skew between data arrival timesistolerated within the same
clockperiod

Asynchronous circuits are less reliable

A delay may need to be a specific amount (e.g.12ns)
Multiple delays may need to hold a specific relationship (e.g.
DATA arrives 5ns before SELECT)

1999 Xilinx, Inc.

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Intro to FPGA Design 6-11

No part of this document may be reproduced or transmitted without the
express written permission of the Director of XilinxCustomer Education.

Case Studies

The design I did two years ago no longer works.W hat

did Xilinx change in their FPGAs?
SRAM process improvements and geometry shrinks
increase speed
Normalvariations between wafer l
ots

My design was working,but I re-routed m y FPGA and

now m y design fails.W hat is happening?
Logic pl
acement has changed,which affects internalrouting
del
ays

My design passes a back-annotated tim ing sim ulation

but fails in circuit.Is the tim ing sim ulation accurate?
Yes,the simul
ation is accurate
Timing simul
ation uses worst-case del
ays
Actualboard-l
evelconditions are usual
l
y better
1999 Xilinx, Inc.
All Rights Reserved

Intro to FPGA Design 6-12

No part of this document may be reproduced or transmitted without the
express written permission of the Director of XilinxCustomer Education.

Design Tips
Xilinx FPGA Design

Reduce clock skew

Clock dividers
Avoid glitches on clocks and asynchronous
set/reset signals
The GlobalSet/Reset network
Select a state m achine encoding schem e
Access carry logic
Build efficient counters

1999 Xilinx, Inc.

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Intro to FPGA Design 6-13

No part of this document may be reproduced or transmitted without the
express written permission of the Director of XilinxCustomer Education.

Clock Skew
INPUT

3.1

D Q_A

CLOCK
3.0

3.1 D Q_B

3.0

12.5

3.3 D Q_C

This shift register willnot work because ofclock

skew!
2 cycles
3 cycles
A&C
Clock

Clock

B Clock
Q_A

Expected operation

Q_B
Q_C

Q_A
Q_B

Clockskewed version

Q_C

1999 Xilinx, Inc.

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Intro to FPGA Design 6-14

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express written permission of the Director of XilinxCustomer Education.

Use GlobalBuffers to Reduce

Clock Skew

Globalbuffers are connected to dedicated routing

This routing network is balanced to minimize skew

AllXilinx FPGAs have globalbuffers

Different types ofglobalbuffers
XC4000E/L and Spartan have 4 BUFGPs and 4 BUFGSs
XC4000EX/XL/XV have 8 BUFGLSs
Virtexhas 4 BUFGs or BUFGDLLs

You can always use a BUFG sym boland the software

willchoose an appropriate buffer type
Most synthesis tools can infer global buffers onto clock
signals
1999 Xilinx, Inc.
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Intro to FPGA Design 6-15

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express written permission of the Director of XilinxCustomer Education.

TraditionalClock Divider

Introduces clock skew between CLK1 and CLK2

Uses an extra BUFG to reduce skew on CLK2

CLK2

BUFG

CLK1
BUFG
1999 Xilinx, Inc.
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Intro to FPGA Design 6-16

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express written permission of the Director of XilinxCustomer Education.

Recom m ended Clock Divider

No clock skew between flip-flops

CLK2_CE
D

CLK1
BUFG

1999 Xilinx, Inc.

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Intro to FPGA Design 6-17

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express written permission of the Director of XilinxCustomer Education.

D
CE

Avoid Clock Glitches

Because flip-flops in todays FPGAs are very fast,they

can respond to very narrow clock pulses
Never source a clock signalfrom com binatoriallogic
Also known as gating the clock

MSB

0111
0111

1000 transition can become

1000 due to fasterMSB

1111

MSB

Shorter routing

FF
LSB

Gl
itch mayoccur here

Binary
Counter
1999 Xilinx, Inc.
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Intro to FPGA Design 6-18

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express written permission of the Director of XilinxCustomer Education.

Avoid Clock Glitches:Answer

Com plete in the circuit to create the sam e function,

but without glitches on the clock
D

INPUT

Q3
Q2

CE

Q1
Q0

FF

CLOCK
Counter

1999 Xilinx, Inc.

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Intro to FPGA Design 6-21

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express written permission of the Director of XilinxCustomer Education.

Avoid Set/Reset Glitches

Glitches on asynchronous clear or preset inputs can

lead to incorrect circuit behavior
FF

INPUT

Asynchronous Clear

Binary
Counter

CLR

Q[x]

RESET

Q[0]

CLOCK

1999 Xilinx, Inc.

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Intro to FPGA Design 6-22

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express written permission of the Director of XilinxCustomer Education.

Avoid Set/Reset Glitches

Convert to synchronous set or reset when possible

FF

INPUT

Synchronous Reset

Binary
Counter

Q[x]

RESET

Q[0]

CLOCK

1999 Xilinx, Inc.

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Intro to FPGA Design 6-23

No part of this document may be reproduced or transmitted without the
express written permission of the Director of XilinxCustomer Education.