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  • Circuit Os Electronic Os

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    Herless Bardales Villanueva
    17 views6 pages
    The document discusses the construction of logic gates. It describes NAND gates with 2, 3, and 4 inputs, and provides the logic circuit, electronic circuit, processes, and truth tables for each. NOR gates with 2, 3, and 4 inputs are also described along with XNOR gates with 2, 3, and 4 inputs. For each gate, the logic circuit, electronic circuit, processes, and a truth table are provided.

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    The document discusses the construction of logic gates. It describes NAND gates with 2, 3, and 4 inputs, and provides the logic circuit, electronic circuit, processes, and truth tables for each. NOR gates with 2, 3, and 4 inputs are also described along with XNOR gates with 2, 3, and 4 inputs. For each gate, the logic circuit, electronic circuit, processes, and a truth table are provided.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    17 views6 pages

    Circuit Os Electronic Os

    Uploaded by

    Herless Bardales Villanueva
    The document discusses the construction of logic gates. It describes NAND gates with 2, 3, and 4 inputs, and provides the logic circuit, electronic circuit, processes, and truth tables for each. NOR gates with 2, 3, and 4 inputs are also described along with XNOR gates with 2, 3, and 4 inputs. For each gate, the logic circuit, electronic circuit, processes, and a truth table are provided.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 6

    Construccin de Compuertas Lgicas

    Por

    Mayo 11 del 2016

    1. Compuerta NAND
    1.1 NAND_21
    a. Circuito Lgico
    b. Circuito Electrnico

    c. Procesos
    d. Tabla de Estados
    a

    0V

    0V

    0V

    +5

    +5
    V
    +5

    V
    0V

    +5
    V
    +5
    V

    V
    +5
    V
    0V

    +5
    V

    1.2 NAND_31
    a. Circuito Lgico
    b. Circuito Electrnico
    c. Procesos
    d. Tabla de Estados
    a

    0V

    0V

    0V

    0V

    0V

    0V

    +5
    V
    +5
    V
    0V

    +5
    V
    0V

    +5
    V
    +5
    V
    +5
    V
    +5
    V
    +5
    V
    +5
    V
    +5
    V
    0V

    0V
    +5
    V
    +5
    V
    +5
    V
    +5
    V

    0V
    +5
    V
    +5
    V

    +5
    V
    0V
    +5
    V
    0V
    +5
    V

    1.3 NAND_41
    a. Circuito Lgico
    b. Circuito Electrnico

    c. Procesos
    d. Tabla de Estados
    a

    0V
    0V
    0V
    0V

    0V
    0V
    0V
    0V

    0V
    0V
    +5V
    +5V

    0V
    +5V
    0V
    +5V

    +5V
    +5V
    +5V
    +5V

    0V
    0V
    0V
    0V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V

    +5V
    +5V
    +5V
    +5V
    0V
    0V
    0V
    0V
    +5V
    +5V
    +5V
    +5V

    0V
    0V
    +5V
    +5V
    0V
    0V
    +5V
    +5V
    0V
    0V
    +5V
    +5V

    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V

    0V

    0V

    0V

    +5
    V
    0V

    +5
    V
    0V

    2. Compuerta NOR
    2.1 NOR_21
    a. Circuito Lgico
    b. Circuito Electrnico

    c. Procesos
    d. Tabla de Estados

    +5
    V
    +5
    V

    0V

    +5
    V

    0V

    2.2 NOR_31
    a. Circuito Lgico
    b. Circuito Electrnico
    c. Procesos
    d. Tabla de Estados
    a

    0V

    0V

    0V

    0V

    0V

    +5

    +5
    V
    0V

    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    0V

    0V
    0V
    +5
    V
    +5
    V
    +5
    V
    +5
    V

    +5
    V
    +5
    V
    0V
    0V
    +5
    V
    +5
    V

    V
    0V

    0V

    +5
    V
    0V

    0V

    +5
    V
    0V

    0V

    +5
    V

    0V

    0V

    0V

    2.3 NOR_41
    a. Circuito Lgico
    b. Circuito Electrnico

    c. Procesos
    d. Tabla de Estados
    a

    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V

    0V
    0V
    0V
    0V
    +5V
    +5V
    +5V
    +5V
    0V
    0V
    0V
    0V
    +5V
    +5V
    +5V
    +5V

    0V
    0V
    +5V
    +5V
    0V
    0V
    +5V
    +5V
    0V
    0V
    +5V
    +5V
    0V
    0V
    +5V
    +5V

    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V

    +5V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V

    3. Compuerta XNOR
    3.1 XNOR_21
    a. Circuito Lgico
    b. Circuito Electrnico
    c. Procesos
    d. Tabla de Estados

    0V

    0V

    0V

    +5
    V
    0V

    +5
    V
    0V

    +5
    V
    +5
    V

    0V

    +5
    V

    +5
    V

    3.2 XNOR_31
    a. Circuito Lgico
    b. Circuito Electrnico
    c. Procesos
    d. Tabla de Estados
    a

    0V

    0V

    0V

    0V

    0V

    0V

    +5
    V
    +5
    V
    0V

    +5
    V
    0V

    +5
    V
    0V

    0V
    +5
    V
    +5
    V
    +5
    V
    +5
    V
    3.3 XNOR_41
    a. Circuito Lgico
    b. Circuito Electrnico
    c. Procesos
    d. Tabla de Estados

    0V
    +5
    V
    +5
    V

    0V

    +5
    V
    0V

    +5
    V
    0V

    +5
    V
    0V

    +5
    V
    +5
    V
    0V

    +5
    V

    0V
    0V
    0V
    0V
    0V
    0V
    0V
    0V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V
    +5V

    0V
    0V
    0V
    0V
    +5V
    +5V
    +5V
    +5V
    0V
    0V
    0V
    0V
    +5V
    +5V
    +5V
    +5V

    0V
    0V
    +5V
    +5V
    0V
    0V
    +5V
    +5V
    0V
    0V
    +5V
    +5V
    0V
    0V
    +5V
    +5V

    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V
    0V
    +5V

    +5V
    0V
    0V
    +5V
    0V
    +5V
    +5V
    0V
    0V
    +5V
    +5V
    0V
    +5V
    0V
    0V
    +5V

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